CN102163559A - 堆叠装置的制造方法及装置晶片处理方法 - Google Patents

堆叠装置的制造方法及装置晶片处理方法 Download PDF

Info

Publication number
CN102163559A
CN102163559A CN2010102466864A CN201010246686A CN102163559A CN 102163559 A CN102163559 A CN 102163559A CN 2010102466864 A CN2010102466864 A CN 2010102466864A CN 201010246686 A CN201010246686 A CN 201010246686A CN 102163559 A CN102163559 A CN 102163559A
Authority
CN
China
Prior art keywords
adhesion coating
wafer
loading plate
thinning
marginal zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010102466864A
Other languages
English (en)
Other versions
CN102163559B (zh
Inventor
吴文进
邱文智
眭晓林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102163559A publication Critical patent/CN102163559A/zh
Application granted granted Critical
Publication of CN102163559B publication Critical patent/CN102163559B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Abstract

本发明揭示一种堆叠装置的制造方法及装置晶片处理方法，该堆叠装置的制造方法包括经由第一粘着层及第二粘着层而将一晶片接合至一承载板，其中晶片与承载板的边缘区被第一粘着层覆盖，但未被第二粘着层覆盖。进行晶片边缘清洁工艺，以去除邻近晶片边缘的第一粘着层而露出承载板的边缘区，接着自承载板处去除第二粘着层。自晶片卸离承载板之后，去除余留在晶片上的第一粘着层。本发明容易在不发生损害的情形下自薄化的装置晶片卸离承载板。

Description

堆叠装置的制造方法及装置晶片处理方法
技术领域
本发明涉及一种半导体装置的制作，特别涉及一种半导体装置制造期间处理(handle)薄化的晶片所使用的临时承载板的接合与卸离(detaching)方法。
背景技术
由于各个电子部件(即，晶体管、二极管、电阻、电容等等)的集成度(integration density)持续不断的改进，使半导体业持续的快速成长发展。主要来说，集成度的改进来自于最小特征尺寸(minimum feature size)不断缩小而容许更多的部件整合至既有的芯片面积内。因此创造出三维集成电路(three-dimensional integrated circuit，3DIC)来解决装置数量增加时，存在于装置之间内连线长度及数量的限制因素。裸片对晶片(die to wafer)堆叠接合为形成3DIC的一种方式，其中一或一个以上的裸片接合至一晶片上，而裸片的尺寸可小于晶片上的芯片(chip)。为了减少半导体封装的厚度、增加芯片的速度，以及高密度元件制作，因而致力于缩减半导体晶片的厚度。因此，重要的3D技术工艺其中之一在于如何处理晶片薄化。用于临时性接合的典型工艺包括在承载晶片及/或装置晶片上涂覆一粘着剂、将装置晶片与承载板接合、对装置晶片进行加工以及接着去除承载板。
厚度缩减即为对背向于半导体晶片中含有电路图案(pattern-formed circuity)的表面进行所谓的晶背研磨，半导体晶片上通常通过一粘着材料来贴附一载板，以协助晶片的处理。由于薄化的晶片强度不足且较容易发生变形，例如弯曲(bending)及/或翘曲(warping)，因此在利用切割工艺使晶片分割成个别的芯片封装之前，晶片表面先以成型材料(molding compound)进行封胶(例如，热固型环氧树脂)。传统成型工艺中晶片边缘会露出一部分的粘着材料，使晶片边缘在进行后续工艺(例如时蚀刻或干蚀刻)期间容易受损，例如在卸离承载板之后发生破片(chipped)。特别是使用热固性(thermosetting)的粘着材料时，装置晶片所进行的高温背侧工艺，使粘着强度大于装置晶片中的低介电常数材料层而在承载板卸离工艺期间造成低介电常数材料层的损害。同样地，在进行背侧工艺期间，粘着材料的粘度降低，使粘着材料流入玻璃承载板而引发其他的问题。
发明内容
本发明的目的在于克服现有技术中的缺陷。
本发明一实施例中，一种堆叠装置的制造方法，包括：提供一晶片，其具有一第一表面及与其相对的一第二表面，其中第一表面上涂覆了一第一粘着层；提供涂覆了一第二粘着层的一承载板，而露出承载板的一边缘区；经由第一粘着层及第二粘着层将晶片的第一表面接合至承载板，其中承载版的边缘区被第一粘着层覆盖；自第二表面薄化晶片，以形成一薄化的晶片；将多个裸片接合至薄化的晶片上；去除邻近于薄化的晶片边缘的第一粘着层，而露出承载板的边缘区以及邻近于承载板的边缘区的该二粘着层；施加一光能或热能，以分解第二粘着层；自晶片卸离承载板；以及去除余留于晶片的第一表面上的第一粘着层。
本发明另一实施例中，一种堆叠装置的制造方法，包括：提供一晶片，其具有一第一表面及与其相对的一第二表面，其中第一表面上涂覆了一第一粘着层；提供涂覆了一第二粘着层的一承载板，而露出承载板的一边缘区；经由第一粘着层及第二粘着层将晶片的第一表面接合至承载板，其中承载版的边缘区被第一粘着层覆盖；自第二表面薄化晶片，以形成一薄化的晶片；将多个裸片接合至薄化的晶片上，以形成一裸片对晶片的堆叠；在裸片对晶片的堆叠上形成一成型材料；在邻近成型材料的边缘形成一通道，其中通道穿过成型材料、晶片的边缘以及一部分的第一粘着层；去除成型材料、晶片的边缘以及第一粘着层中环绕通道的部分，而露出承载板的边缘区以及邻近于承载板的该边缘区的第二粘着层；去除第二粘着层；自晶片卸离该承载板；以及去除余留于晶片的第一表面上的第一粘着层。
本发明又一实施例中，一种装置晶片的处理方法，包括：提供一装置晶片，其包括具有一前表面及一背表面的一半导体基底，其中一填有导电材料的通孔电极形成于半导体基底内且从前表面往被表面延伸入半导体基底至一深度；在半导体基底的前表面形成一第一粘着层，以覆盖装置晶片的边缘；提供涂覆了一第二粘着层的一承载板，而露出承载板的一边缘区；经由第一粘着层及第二粘着层将装置晶片接合至承载板，其中承载版的边缘区被第一粘着层覆盖；自半导体基底的背表面薄化装置晶片，以露出通孔电极的一端点；在半导体基底的背表面上方形成一金属化结构，以电性连接至通孔电极的露出的端点；将一裸片接合至装置晶片上，以电性连接金属化结构；去除邻近装置晶片边缘的第一粘着层，以露出承载板的该边缘区；去除第二粘着层；自晶片卸离承载板；以及去除第一粘着层。
本发明能在后续进行薄化及背侧工艺期间轻易处理装置晶片，更容易在不发生损害的情形下自薄化的装置晶片卸离承载板。
附图说明
图1示出根据一实施例的垂直式裸片对裸片堆叠的制造流程图，其包括临时承载板的接合及卸离。
图2A至图2K示出根据图1的方法来制造裸片对裸片堆叠的各个阶段的一实施例的剖面示意图。
图3A至图3C示出根据临时承载板的接合及卸离方法来处理具有通孔电极的装置晶片的方法的一实施例的剖面示意图。
图4示出根据一实施例的垂直式裸片对裸片堆叠的制造流程图，其包括临时承载板的接合及卸离。
图5A至图5G示出根据图4的方法来制造裸片对裸片堆叠的各个阶段的一实施例的剖面示意图。
其中，附图标记说明如下：
100、500～方法；
102、104、106、108、112、114、116、118、120、122、124、126、510、512、514、516、518～步骤；
200～装置晶片；
200”～薄化的装置晶片；
200a～第一侧；
200b、200b”～第二侧；
200e～边缘；
202～第一粘着层；
204～金属化结构；
210～半导体基底；
210”～薄化的基底；
210a～前表面；
210b、210”～背表面；
220～通孔电极；
220a～端点；
240～内连结构；
250～背侧隔离层；
260～接垫；
280～导电结构；
300～承载板；
300e～边缘区；
302～第二粘着层；
400～裸片；
402～裸片对晶片的堆叠；
402a～成型堆叠；
404～成型材料；
405～通道；
406～光源；
408～裸片对裸片的堆叠。
具体实施方式
在以下说明中，提出了许多特定细节部分，以充分了解本发明。然而，任何所属技术领域中普通技术人员将会了解本发明能够在没有这些特定细节情形下实行。在一些范例中，并未详述公知结构及工艺，以避免使本发明产生不必要的混淆。
本说明书全文中所提及关于“一实施例”的意思是指有关于本实施例中所提及特定的特征(feature)、结构、或特色包含于本发明的至少一实施例中。因此，本说明书全文中各处所出现的“在一实施例中”用语所指的并不全然表示为相同的实施例。再者，特定的特征、结构、或特色能以任何适当方式而与一或多个实施例作结合。可以理解的是以下的附图并未依照比例示出，而仅仅提供说明之用。
请参照图1，其示出根据一实施例的垂直式裸片对裸片(die to die)堆叠的制造流程图，其包括临时承载板(temporary caiier)的接合及卸离。请参照图2A至图2K，其示出根据图1的方法来制造裸片对裸片堆叠的各个阶段的一实施例。
方法100的起始步骤102为在一装置晶片上涂覆一第一粘着层，且接着进行步骤104，在一承载板上涂覆一第二粘着层。图2A示出一实施例的在一装置晶片200上涂覆一第一粘着层202的剖面示意图，用以贴附于涂覆第二粘着层302的承载板300。装置晶片200内具有多个半导体芯片，其中每一芯片包括一基底，其上形成有公知的电子装置。基底可由半导体材料、硅、砷化锗、白水晶(rock crystal)晶片、蓝宝石、玻璃、石英、陶瓷、热固性材料等等所构成。基底上通常覆盖一或多层介电层及导电层。导电层提供下方电子装置的连接及布线(routing)。装置晶片200具有第一侧200a及相对于第一侧200a的第二侧200b。在第一侧200a上，形成有集成电路，包括有源(active)及无源(passive)装置，例如晶体管、电阻、电容等等，用以连接接垫及/或其他内连结构。
第一粘着层202置于第一侧200a上方，以将装置晶片200贴附承载板300。在一实施例中，第一粘着层202覆盖装置晶片200的第一侧200a的边缘200e。第一粘着层202可为一单层、多层粘着结构、或复合层而应用于旋涂(spin on)或多层贴合(lamination)工艺，其中至少一粘着层包括施化学去除型粘着材料，例如热塑性(thermal plastic)材料、溶剂可溶型材料。也可使用其他类型的粘着材料，例如压力敏感性粘着材料、光固化性粘着材料、环氧化物、或其组合等等。粘着材料可置于半液状或胶体的表面上，其在受压之下可立即变形。第一粘着层202可轻易进行物理性或化学性剥除。
承载板300由可去除或可溶材料所构成，例如，硅、玻璃、石英、陶瓷、氧化硅、氧化铝、高分子、塑胶、丙烯酸基(acrylic-based)材料、任何其他透明材料、或其组合。承载板300为平整的，使其能够贴附于装置晶片200。承载板300的厚度在550微米(μm)至850微米的范围。承载板300的直径大于装置晶片200的直径，然而承载板300的尺寸不尽然取决于装置晶片200的尺寸。在进行处理或加工期间，承载板300提供装置晶片200的物理性支撑，且承载板300为透明的，以容许光线的穿透，例如激光或紫外光(UV)。
第二粘着层302置于承载板300上方，以将装置晶片200贴附承载板300。在一实施例中，除了承载板300的边缘区300e之外，第二粘着层302覆盖承载板300的主要部分。第二粘着层302可为一单层或复合层而应用于旋涂或多层贴合工艺。在一实施例中，第二粘着层302由光分解性粘着材料所构成，例如激光敏感性材料、UV敏感性材料或热分解性材料，其能够在暴露于光能或热能(例如，红外光(IR)、激光、UV等等)时被分解而失去粘性。在另一实施例中，第二粘着层302由溶剂分解性粘着材料所构成，例如热塑性材料，其能够以溶剂进行分解，例如光致抗蚀剂相关溶剂(如，丙二醇单甲基醚酯(propylene glycol methyl ether acetate，PGMEA)或N-甲基吡咯酮(N-methyl pyrrolidinone，NMP))。
进行方法100的步骤106，将装置晶片与承载板接合。图2B示出将装置晶片200倒置且经由粘着层202及302而接合至承载板300上的剖面示意图，使其能在后续进行薄化及背侧工艺期间轻易处理装置晶片200。第一粘着层302覆盖第二粘着层302以及承载板300的边缘区300e。
进行方法100的步骤108，对装置晶片的背侧进行薄化。图2C示出装置晶片200进行晶片薄化工艺的剖面示意图。在贴合至承载板300之后，对装置晶片200的无结构(structure-free)区(第二侧200b)进行加工至所需的最终厚度。举例来说，可通过磨削(grinding)、蚀刻及/或磨抛的方式来进行而形成具有既定厚度(取决于半导体封装使用目的)的薄化晶片200”。在一实施例中，装置晶片200薄化至约5微米至50微米的厚度。在另一实施例中，装置晶片200薄化至约25微米至250微米的厚度。
进行方法100的步骤110，在装置晶片的背侧形成金属化结构。图2D示出在薄化的装置晶片200”的第二侧200b”上形成金属化结构204的剖面示意图。背侧的金属化结构204包括内连结构(例如，重布线(re-distribution line，RDL))、外部接触结构(例如，个别的半导体芯片的焊料凸块(solder bump)或含铜凸块)及/或作为电源线、电感、电容或任何无源部件的其它结构。金属化结构204可由电镀、无电电镀、溅镀(sputtering)、化学气相沉积(chemical vapor deposition)等方法所形成的铜、铝、铜合金或其他导电材料所构成。
进行方法100的步骤112，将芯片接合至装置晶片的背侧上。图2E示出将多个裸片400接合以及电性连接至薄化的装置晶片200”的第二侧200b”上的金属化结构400而形成裸片对晶片的堆叠402的剖面示意图。接合方法包括一般所使用的方法，例如氧化层对氧化层接合、氧化层对硅层接合、铜对铜接合、粘着接合以及焊料凸块接合等等。裸片400可包括存储器芯片、射频(radio frequency，RF)芯片、逻辑芯片、或其他芯片。每一裸片400具有第一表面及第二表面，且集成电路形成于第一表面上。在一实施例中，裸片400的第一表面接合至薄化的装置晶片200”。在一实施例中，裸片400的第二表面14b接合至薄化的装置晶片200”。
进行方法100的步骤114，将裸片对晶片的堆叠进行成型(molding)。图2F示出将裸片对晶片的堆叠402进行成型工艺而形成一成型堆叠402a的剖面示意图。一成型材料404涂覆于裸片对晶片的堆叠402上，且填入相邻的裸片400之间的空间。成型工艺在薄化的装置晶片200”的边缘保留一未覆盖区。成型材料404可由固化材料所构成，例如高分子材料、树脂材料、聚酰亚胺(polyimide)、氧化硅、环氧化物、苯并环丁烯(benzocyclobutene，BCB)、SilkTM(陶式化学公司(Dow Chemical))、或其组合。成型工艺包括射出成型、压缩成型、钢板印刷、旋转涂布或是未来所发展的成型工艺。在涂覆成型材料404之后，进行固化或烘烤步骤，以凝固成型材料404。
进行方法100的步骤116，自成型堆叠402a卸离承载板300。图2G至图2I示出承载板卸离工艺的各个阶段剖面示意图。开始进行步骤116的步骤118，通过一清洁方法来去除位于薄化的装置晶片200”的边缘200e的第一粘着层202，以露出承载板300的边缘区300e以及邻近于边缘区300e的第二粘着层302，如图2G所示。清洁方法可为化学喷洗(jetting)工艺或湿式槽洗(wet bench)工艺。进行步骤116的步骤120，去除第二粘着层302。在一实施例中，通过光源406分解来去除第二粘着层302，如图2H所示。光源406通往承载板300并穿过承载板300，使第二粘着层302在吸收光能之后被分解。光源406可包括红外光(IR)、激光、照射灯等等。在其他实施例中，可通过溶剂分解法来去除第二粘着层302，例如NH4OH。
通常在完成晶片级测试之后，进行步骤116的步骤122，分开承载板300及成型堆叠402a，如图2I所示。由于第二粘着层302通过分解或溶剂而去除，因此更容易在不发生损害的情形下自薄化的装置晶片200”卸离承载板300。卸离工艺可为任何适当的剥离(de-bonding)工艺，使薄化的装置晶片200”中的半导体结构保有其完整性。举例来说，利用溶剂、UV照射、或拉脱(pulled off)方式来进行卸离工艺，以自第一粘着层202去除承载板300。
进行方法100的步骤124，去除留在薄化的装置晶片200”上第一粘着层202。图2J示出对薄化的装置晶片200”的第一侧200a进行晶片清洁工艺以去除第一粘着层202的剖面示意图。在一实施例中，晶片清洁工艺为湿式工艺，以化学剥除第一粘着层302。在其他实施中，可通过热分解、剥离、等离子体清洁、粒剂清洁(pellet cleaning)等等来去除第一粘着层202，因而露出了个别的半导体芯片中用以接合至电性接头且形成于薄化的装置晶片200”的第一侧200a的外部接触。
进行方法100的步骤126，以惯用方法沿着切割道将成型堆叠402a切割成个别的裸片对裸片的堆叠408。图2K示出多个裸片对裸片的堆叠408的剖面示意图。在进行切割工艺之后，堆叠的晶片可通过异方性导电膜(anisotropically conductive connection film)而组装于IC卡上。
装置晶片200的一或多个裸片可具有一或多个基底通孔电极(through substrate via，TSV)形成于内。图3A至图3C示出根据图1及图2A至图2K的方法来制造具有通孔电极的装置晶片的一实施例，其中省略相同或相似部分的解释说明。
根据方法100的步骤102至106，图3A示出具有多个硅通孔电极(through silicon via，TSV)的装置晶片200通过粘着层202及302而接合至承载板300的剖面示意图。
装置晶片200包括具有前表面210a及背表面210b的一半导体基底210，其中集成电路及内连结构形成于前表面210a上，且多个通孔电极220穿过至少一部分的半导体基底210。每一通孔电极220充填金属的插塞，自前表面210a往背表面210b延伸至一预定深度。通孔电极220可电性连接形成于内连结构240上的接垫260。通孔电极220的制作可在制作“第一层位内连线”(其表示位于接触窗结构(via structure)与晶体管上方的最底层金属层间介电(inter-metal dielectric，IMD)层中最底层金属图案层)之前进行。另外，金属填充通孔(metal-filled via)工艺可在制作内连线结构之后进行。
根据方法100的步骤108至112，图3B示出包括多个硅通孔电极(TSV)的成型堆叠402a的剖面示意图。在进行背侧薄化工艺之后，通孔电极220的一端点220a露出及/或突出于薄化的基底210”的背表面210b”，如图2B所示。形成背侧隔离层250，以覆盖薄化的晶片210”的背侧。导电结构280，例如焊料凸块或铜凸块，形成于通孔电极220的端点220a上方，以接合至裸片400。导电结构280也包括重布局层(RDL)及接垫，其可在制作焊料凸块或铜凸块之前形成。
根据方法100的步骤114至124，图3C示出承载板300自承型堆叠402a卸离的剖面示意图。再将成型材料404涂覆于裸片对晶片的堆叠402上方之后，通过一清洁方法来去除位于薄化的装置晶片200”边缘的第一粘着层202，以露出承载板300的边缘区300e以及邻近边缘区300e的第二粘着层302(未示出于图3C)。接着利用光源406来分解去除第二粘着层302，如图2H所示。另外，可通过溶剂分解法来去除第二粘着层302。接下来，自成型堆叠402a卸离承载板300而无造成损害。接着进行以下步骤，通过晶片清洁工艺去除余留于薄化的装置晶片200”上的第一粘着层202，例如以湿式工艺，化学性剥除第一粘着层202。
以上说明了许多实施例的特征，虽然所揭示的临时承载板的使用是有关于TSV装置晶片的制作，然而可以理解的是此处所揭示的方法可实施于其他需使用临时性承载板的应用类型，例如图像传感器、微机电系统(microelectromechanical systems，MEMS)、或其他3DIC应用。
请参照图4，其示出根据一实施例的垂直式裸片对裸片堆叠的制造流程图，其包括临时承载板的接合及卸离。请参照图5A至图5G，其示出根据图4的方法来制造裸片对裸片堆叠的各个阶段的一实施例的剖面示意图，其中省略相同或相似于图1至图3的解释说明。
方法500起始于步骤102及104，接着进行步骤106至114，形成以成型材料404封胶的成型堆叠402a，如图5A所示。
接着，方法500进行步骤510，自裸片对晶片的堆叠402卸离承载板300。图5A至图5G示出承载板卸离工艺的各个阶段剖面示意图。开始进行步骤510的步骤512，微削(trimming)薄化的装置晶片200”的边缘，以形成环绕且邻近成型堆叠402a边缘的通道405，如图5B所示。通过切割法，例如激光切割工具，使通道405切穿成型材料404及薄化的装置晶片200”，且延伸置一部分的第一粘着层202而未接触承载板300及/或第二粘着层302。另外，也可使用蚀刻工艺来形成通道405。通道405的直径小于5毫米(mm)。
进行步骤510的步骤514，通过一清洁方法来去除位于薄化的装置晶片200”的边缘200e的第一粘着层202，以露出承载板300的边缘区300e以及邻近于边缘区300e的第二粘着层302，如图5C所示。清洁方法可为化学喷洗工艺或湿式槽洗工艺，用以去除环绕通道405的部分，包括了邻近成型堆叠402a边缘的成型材料404、薄化的装置晶片200”以及第一粘着层202，因而露出邻近承载板300的边缘区300e的第二粘着层302，同样也露出了承载板300的边缘区300e。
进行步骤510的步骤516，去除第二粘着层302。在一实施例中，通过光源406分解来去除第二粘着层302，如图5D所示。光源406通往承载板300并穿过承载板300，使第二粘着层302在吸收光能之后被分解。光源406可包括红外光(IR)、激光、照射灯等等。在其他实施例中，可通过溶剂分解法来去除第二粘着层302。
通常在完成晶片级测试之后，进行步骤510的步骤518，分开承载板300及裸片对晶片的堆叠402，如图5E所示。由于第二粘着层302通过分解或溶剂而去除，因此更容易在不发生损害的情形下自薄化的装置晶片200”卸离承载板300。卸离工艺可为任何适当的剥离工艺，使薄化的装置晶片200”中的半导体结构保有其完整性。举例来说，利用溶剂、UV照射、或拉脱方式来进行卸离工艺，以自第一粘着层202去除承载板300。
进行方法500的步骤124，去除留在薄化的装置晶片200”上第一粘着层202。图5F示出对薄化的装置晶片200”的第一侧200a进行晶片清洁工艺以去除第一粘着层202的剖面示意图。在一实施例中，晶片清洁工艺为湿式工艺，以化学剥除第一粘着层302。因此，露出了个别的半导体芯片中用以接合至电性接头且形成于薄化的装置晶片200”的第一侧200a的外部接触。进行方法500的步骤126，以惯用方法沿着切割道将成型堆叠402a切割成个别的裸片对裸片的堆叠408。图5G示出多个裸片对裸片的堆叠408的剖面示意图。在进行切割工艺之后，堆叠的晶片可通过异方性导电膜组装于IC卡上。
以上的详细说明中，本发明对照其特定实施例作说明。然而，很清楚的是在不脱离本发明的精神和范围内，当可作出各种更动、结构、工艺及改变，如权利要求所述。因此，说明书及附图用于范例说明而不是用以限定本发明。可以理解的是本发明能够使用其他不同的组合与环境，且能够在此处所表达的发明概念范围内作改变与更动。

Claims (10)

1.一种堆叠装置的制造方法，包括：
提供一晶片，其具有一第一表面及与其相对的一第二表面，其中该第一表面上涂覆了一第一粘着层；
提供涂覆了一第二粘着层的一承载板，而露出该承载板的一边缘区；
经由该第一粘着层及该第二粘着层将该晶片的该第一表面接合至该承载板，其中该承载版的该边缘区被该第一粘着层覆盖；
自该第二表面薄化该晶片，以形成一薄化的晶片；
将多个裸片接合至该薄化的晶片上；
去除邻近于该薄化的晶片边缘的该第一粘着层，而露出该承载板的该边缘区以及邻近于该承载板的该边缘区的该第二粘着层；
施加一光能或热能，以分解该第二粘着层；
自该晶片卸离该承载板；以及
去除余留于该晶片的该第一表面上的该第一粘着层。
2.如权利要求1所述的堆叠装置的制造方法，其中该光能包括红外光、激光、或紫外光。
3.如权利要求1所述的堆叠装置的制造方法，其中该第一粘着层由湿化学去除型粘着材料所构成。
4.如权利要求1所述的堆叠装置的制造方法，其中该第二粘着层由光分解型或热分解型或溶剂分解型粘着材料所构成。
5.一种堆叠装置的制造方法，包括：
提供一晶片，其具有一第一表面及与其相对的一第二表面，其中该第一表面上涂覆了一第一粘着层；
提供涂覆了一第二粘着层的一承载板，而露出该承载板的一边缘区；
经由该第一粘着层及该第二粘着层将该晶片的该第一表面接合至该承载板，其中该承载版的该边缘区被该第一粘着层覆盖；
自该第二表面薄化该晶片，以形成一薄化的晶片；
将多个裸片接合至该薄化的晶片上，以形成一裸片对晶片的堆叠；
在该裸片对晶片的堆叠上形成一成型材料；
在邻近该成型材料的边缘形成一通道，其中该通道穿过该成型材料、该晶片的边缘以及一部分的该第一粘着层；
去除该成型材料、该晶片的边缘以及该第一粘着层中环绕该通道的部分，而露出该承载板的该边缘区以及邻近于该承载板的该边缘区的该第二粘着层；
去除该第二粘着层；
自该晶片卸离该承载板；以及
去除余留于该晶片的该第一表面上的该第一粘着层。
6.如权利要求5所述的堆叠装置的制造方法，其中该通道的直径小于5毫米。
7.如权利要求5所述的堆叠装置的制造方法，其中去除该第二粘着层的步骤包括施加一光能或热能或溶剂以分解该第二粘着层。
8.如权利要求5所述的堆叠装置的制造方法，其中该第一粘着层由湿化学去除型粘着材料所构成。
9.一种装置晶片的处理方法，包括：
提供一装置晶片，其包括具有一前表面及一背表面的一半导体基底，其中一填有导电材料的通孔电极形成于该半导体基底内且从该前表面往该被表面延伸入该半导体基底至一深度；
在该半导体基底的该前表面形成一第一粘着层，以覆盖该装置晶片的边缘；
提供涂覆了一第二粘着层的一承载板，而露出该承载板的一边缘区；
经由该第一粘着层及该第二粘着层将该装置晶片接合至该承载板，其中该承载版的该边缘区被该第一粘着层覆盖；
自该半导体基底的该背表面薄化该装置晶片，以露出该通孔电极的一端点；
在该半导体基底的该背表面上方形成一金属化结构，以电性连接至该通孔电极的该露出的端点；
将一裸片接合至该装置晶片上，以电性连接该金属化结构；
去除邻近该装置晶片边缘的该第一粘着层，以露出该承载板的该边缘区；
去除该第二粘着层；
自该晶片卸离该承载板；以及
去除该第一粘着层。
10.如权利要求9所述的装置晶片的处理方法，其中去除该第二粘着层的步骤为施加一光能或热能以分解该第二粘着层。
CN2010102466864A 2010-02-18 2010-08-04 堆叠装置的制造方法及装置晶片处理方法 Active CN102163559B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/707,752 US7883991B1 (en) 2010-02-18 2010-02-18 Temporary carrier bonding and detaching processes
US12/707,752 2010-02-18

Publications (2)

Publication Number Publication Date
CN102163559A true CN102163559A (zh) 2011-08-24
CN102163559B CN102163559B (zh) 2013-01-30

Family

ID=43531937

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010102466864A Active CN102163559B (zh) 2010-02-18 2010-08-04 堆叠装置的制造方法及装置晶片处理方法

Country Status (3)

Country Link
US (1) US7883991B1 (zh)
CN (1) CN102163559B (zh)
TW (1) TWI446419B (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021888A (zh) * 2011-09-23 2013-04-03 格罗方德半导体公司 用于制造包括高可靠性晶粒底填充的集成电路系统的方法
CN105190844A (zh) * 2013-05-24 2015-12-23 富士电机株式会社 半导体装置的制造方法
CN105659356A (zh) * 2013-08-01 2016-06-08 国际商业机器公司 使用中波长红外辐射烧蚀的晶片去接合
CN107403755A (zh) * 2016-05-19 2017-11-28 胡川 芯片制作方法
CN107912069A (zh) * 2015-05-04 2018-04-13 由普莱克斯有限公司 不具有裸片附接垫的引线载体结构和由此形成的封装
TWI628707B (zh) * 2013-11-20 2018-07-01 東京應化工業股份有限公司 處理方法
CN108242393A (zh) * 2016-12-23 2018-07-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN109390281A (zh) * 2017-08-11 2019-02-26 美光科技公司 半导体装置结构和其处理方法与系统
CN110178212A (zh) * 2016-12-28 2019-08-27 英帆萨斯邦德科技有限公司 堆栈基板的处理

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7951816B2 (en) * 2004-08-27 2011-05-31 Ono Pharmaceutical Co., Ltd. Compound containing basic group and use thereof
PT1961744E (pt) 2005-11-18 2013-05-15 Ono Pharmaceutical Co Composto que contém um grupo básico e sua utilização
EP2042503B1 (en) * 2006-05-16 2013-01-30 Ono Pharmaceutical Co., Ltd. Compound having acidic group which may be protected, and use thereof
JP2011040419A (ja) * 2008-05-22 2011-02-24 Fuji Electric Systems Co Ltd 半導体装置の製造方法及びそのための装置
US8232140B2 (en) * 2009-03-27 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for ultra thin wafer handling and processing
US9768305B2 (en) 2009-05-29 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
TWI419302B (zh) * 2010-02-11 2013-12-11 Advanced Semiconductor Eng 封裝製程
FR2957190B1 (fr) * 2010-03-02 2012-04-27 Soitec Silicon On Insulator Procede de realisation d'une structure multicouche avec detourage par effets thermomecaniques.
JP6116476B2 (ja) * 2010-05-20 2017-04-19 エーファウ・グループ・エー・タルナー・ゲーエムベーハー チップスタックを製造するための方法及びその方法を実施するためのキャリア
US8722540B2 (en) * 2010-07-22 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling defects in thin wafer handling
US9263314B2 (en) 2010-08-06 2016-02-16 Brewer Science Inc. Multiple bonding layers for thin-wafer handling
US8324105B2 (en) * 2010-08-13 2012-12-04 Victory Gain Group Corporation Stacking method and stacking carrier
JP5756334B2 (ja) 2010-10-29 2015-07-29 東京応化工業株式会社 積層体、およびその積層体の分離方法
JP2012109538A (ja) 2010-10-29 2012-06-07 Tokyo Ohka Kogyo Co Ltd 積層体、およびその積層体の分離方法
JP5802106B2 (ja) * 2010-11-15 2015-10-28 東京応化工業株式会社 積層体、および分離方法
JP6001568B2 (ja) * 2011-02-28 2016-10-05 ダウ コーニング コーポレーションＤｏｗ Ｃｏｒｎｉｎｇ Ｃｏｒｐｏｒａｔｉｏｎ ウェハ接着システム、及びその接着並びに剥離方法
US8551881B2 (en) * 2011-04-25 2013-10-08 Nanya Technology Corporation Method of bevel trimming three dimensional semiconductor device
JP2013008915A (ja) * 2011-06-27 2013-01-10 Toshiba Corp 基板加工方法及び基板加工装置
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
JP2013030537A (ja) * 2011-07-27 2013-02-07 Elpida Memory Inc 半導体装置の製造方法
JP5421967B2 (ja) * 2011-09-07 2014-02-19 東京エレクトロン株式会社 接合方法、プログラム、コンピュータ記憶媒体及び接合システム
US20130075892A1 (en) * 2011-09-27 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Three Dimensional Integrated Circuit Fabrication
WO2013048496A1 (en) 2011-09-30 2013-04-04 Intel Corporation Method for handling very thin device wafers
DE102012101237A1 (de) 2012-02-16 2013-08-22 Ev Group E. Thallner Gmbh Verfahren zum temporären Verbinden eines Produktsubstrats mit einem Trägersubstrat
US8697542B2 (en) * 2012-04-12 2014-04-15 The Research Foundation Of State University Of New York Method for thin die-to-wafer bonding
TWI468787B (zh) * 2012-04-25 2015-01-11 Mirle Automation Corp 暫時性貼合方法及其貼合設備
US9064770B2 (en) * 2012-07-17 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for minimizing edge peeling in the manufacturing of BSI chips
US9269623B2 (en) 2012-10-25 2016-02-23 Rohm And Haas Electronic Materials Llc Ephemeral bonding
KR102075635B1 (ko) 2013-01-03 2020-03-02 삼성전자주식회사 웨이퍼 지지 구조물, 웨이퍼 지지 구조물을 포함하는 반도체 패키지의 중간 구조물, 및 중간 구조물을 이용한 반도체 패키지의 제조 방법
US9368460B2 (en) * 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
JP6214182B2 (ja) * 2013-03-25 2017-10-18 東京応化工業株式会社 基板の処理方法
US9315696B2 (en) 2013-10-31 2016-04-19 Dow Global Technologies Llc Ephemeral bonding
CN103632926B (zh) * 2013-11-27 2016-04-13 中国电子科技集团公司第四十一研究所 一种用于超薄石英基片上电镀薄膜电路图形的方法
US9870946B2 (en) 2013-12-31 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and method of forming same
KR20150092675A (ko) * 2014-02-05 2015-08-13 삼성전자주식회사 반도체 소자의 제조 방법
US9355881B2 (en) 2014-02-18 2016-05-31 Infineon Technologies Ag Semiconductor device including a dielectric material
JP6423616B2 (ja) * 2014-05-22 2018-11-14 株式会社ディスコ ウェーハの加工方法
US9184104B1 (en) * 2014-05-28 2015-11-10 Stats Chippac, Ltd. Semiconductor device and method of forming adhesive layer over insulating layer for bonding carrier to mixed surfaces of semiconductor die and encapsulant
US9324601B1 (en) * 2014-11-07 2016-04-26 International Business Machines Corporation Low temperature adhesive resins for wafer bonding
US9644118B2 (en) 2015-03-03 2017-05-09 Dow Global Technologies Llc Method of releasably attaching a semiconductor substrate to a carrier
US10522383B2 (en) 2015-03-25 2019-12-31 International Business Machines Corporation Thermoplastic temporary adhesive for silicon handler with infra-red laser wafer de-bonding
JP6481050B2 (ja) * 2015-05-08 2019-03-13 富士フイルム株式会社 デバイス基板及び半導体デバイスの製造方法
KR20180090494A (ko) 2017-02-03 2018-08-13 삼성전자주식회사 기판 구조체 제조 방법
US10340251B2 (en) 2017-04-26 2019-07-02 Nxp Usa, Inc. Method for making an electronic component package
US10326044B2 (en) 2017-08-18 2019-06-18 Micron Technology, Inc. Method and apparatus for processing semiconductor device structures
KR102430496B1 (ko) 2017-09-29 2022-08-08 삼성전자주식회사 이미지 센싱 장치 및 그 제조 방법
US10586725B1 (en) * 2018-01-10 2020-03-10 Facebook Technologies, Llc Method for polymer-assisted chip transfer
US10559486B1 (en) * 2018-01-10 2020-02-11 Facebook Technologies, Llc Method for polymer-assisted chip transfer
US10388516B1 (en) * 2018-01-10 2019-08-20 Facebook Technologies, Llc Method for polymer-assisted chip transfer
US10910287B2 (en) * 2018-02-28 2021-02-02 Stmicroelectronics Pte Ltd Semiconductor package with protected sidewall and method of forming the same
WO2020159856A1 (en) * 2019-01-28 2020-08-06 Amerasia International Technology, Inc. Semiconductor wafer processing system and method
KR20210012302A (ko) * 2019-07-24 2021-02-03 삼성전자주식회사 이미지 센서 칩을 포함하는 반도체 패키지 및 이의 제조 방법
JP7189106B2 (ja) * 2019-09-13 2022-12-13 株式会社東芝 保持板および基板の研磨方法
CN111755377B (zh) * 2020-06-29 2022-02-11 西安微电子技术研究所 一种晶圆解键合方法
CN112959211B (zh) * 2021-02-22 2021-12-31 长江存储科技有限责任公司 晶圆处理装置和处理方法
JP2023038075A (ja) * 2021-09-06 2023-03-16 キオクシア株式会社 半導体製造装置および半導体装置の製造方法
CN115881541A (zh) * 2021-09-28 2023-03-31 聚力成半导体(上海)有限公司 半导体装置的制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020121693A1 (en) * 2000-12-11 2002-09-05 Milla Juan G. Stacked die package
US20020137255A1 (en) * 2001-03-23 2002-09-26 Hsing-Seng Wang One-step semiconductor stack packaging method
CN1885500A (zh) * 2005-06-24 2006-12-27 精工爱普生株式会社 半导体装置的制造方法
CN101611481A (zh) * 2007-01-09 2009-12-23 英飞凌科技股份有限公司 半导体封装

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7462551B2 (en) 2005-09-30 2008-12-09 Intel Corporation Adhesive system for supporting thin silicon wafer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020121693A1 (en) * 2000-12-11 2002-09-05 Milla Juan G. Stacked die package
US20020137255A1 (en) * 2001-03-23 2002-09-26 Hsing-Seng Wang One-step semiconductor stack packaging method
CN1885500A (zh) * 2005-06-24 2006-12-27 精工爱普生株式会社 半导体装置的制造方法
CN101611481A (zh) * 2007-01-09 2009-12-23 英飞凌科技股份有限公司 半导体封装

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021888B (zh) * 2011-09-23 2015-06-03 格罗方德半导体公司 用于制造包括高可靠性晶粒底填充的集成电路系统的方法
CN103021888A (zh) * 2011-09-23 2013-04-03 格罗方德半导体公司 用于制造包括高可靠性晶粒底填充的集成电路系统的方法
US9972521B2 (en) 2013-05-24 2018-05-15 Fuji Electric Co., Ltd. Method for manufacturing semiconductor device to facilitate peeling of a supporting substrate bonded to a semiconductor wafer
CN105190844A (zh) * 2013-05-24 2015-12-23 富士电机株式会社 半导体装置的制造方法
CN105190844B (zh) * 2013-05-24 2017-08-22 富士电机株式会社 半导体装置的制造方法
CN105659356A (zh) * 2013-08-01 2016-06-08 国际商业机器公司 使用中波长红外辐射烧蚀的晶片去接合
TWI628707B (zh) * 2013-11-20 2018-07-01 東京應化工業股份有限公司 處理方法
CN107912069A (zh) * 2015-05-04 2018-04-13 由普莱克斯有限公司 不具有裸片附接垫的引线载体结构和由此形成的封装
CN107403755A (zh) * 2016-05-19 2017-11-28 胡川 芯片制作方法
CN108242393A (zh) * 2016-12-23 2018-07-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN108242393B (zh) * 2016-12-23 2021-04-23 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN110178212A (zh) * 2016-12-28 2019-08-27 英帆萨斯邦德科技有限公司 堆栈基板的处理
CN110178212B (zh) * 2016-12-28 2024-01-09 艾德亚半导体接合科技有限公司 堆栈基板的处理
CN109390281A (zh) * 2017-08-11 2019-02-26 美光科技公司 半导体装置结构和其处理方法与系统
CN109390281B (zh) * 2017-08-11 2023-08-08 美光科技公司 半导体装置结构和其处理方法与系统

Also Published As

Publication number Publication date
TW201130022A (en) 2011-09-01
CN102163559B (zh) 2013-01-30
TWI446419B (zh) 2014-07-21
US7883991B1 (en) 2011-02-08

Similar Documents

Publication Publication Date Title
CN102163559B (zh) 堆叠装置的制造方法及装置晶片处理方法
US20230115122A1 (en) Method of bonding thin substrates
US8846499B2 (en) Composite carrier structure
KR101746269B1 (ko) 반도체 디바이스 및 그 제조방법
US9613857B2 (en) Electrostatic discharge protection structure and method
US20070045836A1 (en) Stacked chip package using warp preventing insulative material and manufacturing method thereof
TW201822330A (zh) 晶片封裝結構
JP5334411B2 (ja) 貼り合わせ基板および貼り合せ基板を用いた半導体装置の製造方法
CN107123605A (zh) 半导体封装件及其返工工艺
TWI494979B (zh) 半導體製程
JP2001015683A (ja) 極薄基板の転写方法及び該方法を用いた多層薄膜デバイスの製造方法
KR20150104467A (ko) 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US8173488B2 (en) Electronic device and method of manufacturing same
US8810012B2 (en) Chip package, method for forming the same, and package wafer
JP2008028325A (ja) 半導体装置の製造方法
US8642390B2 (en) Tape residue-free bump area after wafer back grinding
KR20100020939A (ko) 극박 적층 칩 패키징
US9576889B2 (en) Three-dimensional electronic packages utilizing unpatterned adhesive layer
JPWO2013179767A1 (ja) 撮像装置の製造方法および半導体装置の製造方法
TW201715231A (zh) 感測裝置及其製造方法
WO2020094096A1 (zh) 超薄来料封装方法
US10056294B2 (en) Techniques for adhesive control between a substrate and a die
US7846776B2 (en) Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods
TWI578452B (zh) 積體電路封裝及其製造方法
US8912653B2 (en) Plasma treatment on semiconductor wafers

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant