CN101066004B - 具有被导电材料填充的通孔的基板的制造方法 - Google Patents
具有被导电材料填充的通孔的基板的制造方法 Download PDFInfo
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Abstract
提供一种用于制造在填充于通孔内的导电材料中没有空隙部的具有被导电材料填充的通孔的基板的制造方法。在具有通孔的芯基板的一个面上形成基底导电层,并以该基底导电层为籽层通过电解镀敷使导电材料在通孔内从一个方向淀积、生长,从而不产生空隙部地将导电材料填充在通孔内,这样制造具有被导电材料填充的通孔的基板。
Description
技术领域
本发明涉及具有被导电材料填充的通孔的基板的制造方法,特别涉及能够形成用于载置半导体晶片的多层配线基板等高密度配线基板的具有被导电材料填充的通孔的基板的制造方法。
背景技术
近年来,在电子设备的高性能化、小型化、轻型化的进展中,追求半导体封装体的小型化、多引脚化、外部端子的微小间距化,从而对高密度配线基板的要求越来越高。因此,开始将LSI(大规模集成电路)直接安装在印刷电路配线基板上,或者将CSP(Chip Size Package)、BGA(BallGrid Array)安装在印刷电路配线基板上。于是,为了使印刷电路布线基板也能应对高密度化开始使用由积层法制作的多层配线基板,所述积层法为每一层都经由电气绝缘层地在芯基板上层叠多层配线和导通孔(ビア)。
在以往的一般积层多层配线基板中使用一种具有被导电材料填充的通孔的基板,其是在绝缘基板上通过钻孔设置通孔,并在该通孔内侧实施金属镀敷,在通孔内填充树脂或导电性糊料而形成的(日本特开平9-130050号公报)。该具有被导电材料填充的通孔的基板经由通孔而使正反面导通,在该具有被导电材料填充的通孔的基板上经由电气绝缘层层叠多层配线从而制作出多层配线基板。另外,最近开发出了一种堆叠构造的多层配线基板,其在填充了树脂的通孔上进行加盖镀敷(形成镀敷层使得覆盖住通孔的开口部分),在上述加盖镀敷部分的正上方配置导通孔,进而在该导通孔上再配置导通孔(日本特开2003-23251号公报)。
但是,以往的通孔的形成是由钻孔加工进行的,所以无法使通孔的开口直径比钻头直径更小,在使用微细钻头的钻孔加工中,钻头的破损频率较高。因此,存在通孔的微细化困难、配线设计的自由度受到限制的问题。
另外,在填充有树脂的通孔上进行了加盖镀敷的结构中,由于使用的绝缘基板的热收缩·热膨胀,填充在通孔内部的树脂也会伸缩,由此会有在形成于加盖镀敷部分上的导通孔上容易产生应力集中从而连接可靠性较低的问题。该问题可以通过使用在通孔内仅填充导电材料的具有被导电材料填充的通孔的基板来消除,但如果在填充于通孔内的导电材料中存在空隙部,则会有无法得到按照设计的电气特性的问题。
发明内容
本发明是鉴于上述的问题而完成的,其目的在于提供一种用于制造在填充在通孔内的导电材料中没有空隙部的具有被导电材料填充的通孔的基板的制造方法。
为达成这样的目的,本发明是在通孔内填充导电材料从而使正反面导通的具有被导电材料填充的通孔的基板的制造方法,其中,包括:在具有通孔的芯基板的一个面上形成基底导电层的工序;和以该基底导电层为籽层通过电解镀敷在所述通孔内填充导电材料的工序。
作为本发明的优选方案,通过利用了等离子体的干蚀刻法在芯基板上贯穿设置开口直径在10~100μm的范围内的通孔,从而形成所述具有通孔的芯基板。
作为本发明的优选方案,从芯基板的一个面开始,通过利用了等离子体的干蚀刻法贯穿设置开口直径在10~100μm的范围内的微细孔直到规定的深度,然后研磨芯基板的另一个面使所述微细孔露出从而成为通孔,由此形成所述具有通孔的芯基板。
作为本发明的优选方案,通过蒸镀法、溅镀法中的任意一种来形成所述基底导电层。
作为本发明的优选方案,将所述通孔形成为开口直径在10~70μm的范围内。
作为本发明的优选方案,所述芯基板为硅基板。
作为本发明的优选方案,所述导电材料为铜。
根据本发明,由于以形成在芯基板的一个面上的基底导电层为籽层,使导电材料在通孔内从一个方向淀积、生长,所以能够不产生空隙部地在通孔内形成致密的导电材料,从而能够得到呈现出按照设计的电气特性的具有被导电材料填充的通孔的基板。另外,在通过利用了等离子体的干蚀刻法形成通孔时能够形成开口直径较小的通孔,在这种情况下也能不产生空隙部地填充导电材料,所以能够得到以狭小的间距具有通孔的具有被导电材料填充的通孔的基板。并且,由于在通孔内没有配设树脂,所以能够得到连接可靠性较高的具有被导电材料填充的通孔的基板。
附图说明
图1是表示本发明的具有被导电材料填充的通孔的基板的制造方法的一个实施方式的工序图。
具体实施方式
下面,参照附图对本发明的实施方式进行说明。
图1是表示本发明的具有被导电材料填充的通孔的基板的制造方法的一个实施方式的工序图。
在本发明的具有被导电材料填充的通孔的基板的制造方法中,在芯基板12的一个面12a上形成具有规定的开口14a的掩模图形14,并以该掩模图形14为掩模通过利用了等离子体的干蚀刻法即ICP-RIE(InductiveCoupled Plasma-Reactive Ion Etching)而在芯基板12上以规定深度贯穿设置微细孔13’(图1(A))。
芯基板12可以使用例如硅、玻璃等。另外,在芯基板12的正面12a、反面12b上,也可以根据需要形成二氧化硅、氮化硅等电气绝缘膜。
另外,掩模图形14可以使用具有耐干蚀刻性的材料而形成,例如可以用使用了酚醛清漆树脂的正型抗蚀剂而形成。另外,也可以使用与芯基板12相比蚀刻选择比小(蚀刻速度小)的材料,例如相对于由硅构成的芯基板12使用氧化硅、氮化硅等来形成掩模图形14。
形成的微细孔13’的开口直径可以在10~100μm、优选为10~70μm的范围内适当设定。另外,微细孔13’的深度可以考虑所制作的具有被导电材料填充的通孔的基板的厚度(例如50~725μm)而设定,例如可以在70~745μm的范围内适当设定。这样,用利用了等离子体的干蚀刻法形成通孔用的微细孔13’,由此可以形成开口直径较小的通孔。
接下来,从芯基板12除去掩模图形14,对芯基板12的另一个面12b进行研磨,使微细孔13’露出从而形成通孔13(图1(B))。由此,得到具有通孔13的芯基板12。
另外,也可以根据需要在这样形成的通孔13的内壁面、正面上形成绝缘层、导电性物质扩散防止层。
作为绝缘层,在芯基板12为硅基板时,可以实施热氧化而形成氧化硅膜。另外,也可以对于硅和其他材质的芯基板12,通过等离子体CVD(Chemical Vapor Deposition(化学汽相淀积))形成氧化硅膜、氮化硅膜作为绝缘层。这样的绝缘层的厚度可以在例如500~4000nm的范围内适当设定。
另外,导电性物质扩散防止层可以设为由氮化钛、钛、铬等构成的薄膜。这样的导电性物质扩散防止层可以通过例如MO-CVD(Metal Organic-Chemical Vapor Deposition(有机金属化学汽相淀积))、溅镀法而形成,特别是在通孔13的开口直径为30μm以下时,优选通过MO-CVD形成。
上述那样的绝缘层、导电性物质扩散防止层可以例如从通孔13的内壁面侧开始按照导电性物质扩散防止层/绝缘层的顺序、绝缘层1/导电性物质扩散防止层/绝缘层2的顺序、绝缘层2/导电性物质扩散防止层/绝缘层2的顺序、绝缘层1/绝缘层2/导电性物质扩散防止层/绝缘层2的顺序形成。另外,上述的绝缘层1是通过上述的热氧化法、等离子体CVD形成的绝缘层,绝缘层2是通过上述的等离子体CVD形成的绝缘层。
接下来,在芯基板12的一个面12b上形成基底导电层15(图1(C))。该基底导电层15具有与通孔13相对应的开口部15a,可以通过蒸镀法、溅镀法等形成。这样的基底导电层15可以设为铜、镍、钛、铬、钨等的单层结构,或者组合它们中的2种以上(例如钛/铜、钛/镍)等的多层结构,基底导电层15的厚度可以设为例如10~1000nm左右。另外,在图示例中,将基底导电层15形成于在前工序中进行了研磨的芯基板12的面12b上,但也可以将基底导电层15形成在另一个面12a上。
接下来,以基底导电层15为籽层,通过电解镀敷在微细孔13内填充导电材料16(图1(D))。在该电解镀敷工序中,在基底导电层15上淀积导电材料16,并且在电场密度较高的开口部15a上集中淀积导电材料16从而将开口部15a封闭。然后,导电材料16从该封闭部位向通孔13的内部方向淀积、生长,通孔13内被导电材料16填充。这样,在本发明中,以基底导电层15为籽层而使导电材料16从一个方向淀积、生长从而填充在通孔13内,所以能够不产生空隙部地在通孔内形成致密的导电材料16。
接下来,将芯基板12的面12a上的多余的导电材料16和面12b上的多余的导电材料16、基底导电层15研磨除去,由此得到具有被导电材料填充的通孔的基板11(图1(E))。
另外,上述的实施方式仅是例示,本发明并不局限于上述的实施方式。例如,也可以通过利用了等离子体的干蚀刻法即ICP-RIE(InductiveCoupled Plasma-Reactive Ion Etching)在所希望的厚度的芯基板12上直接贯穿设置通孔13。
实施例
接下来,列举具体的实施例更详细地说明本发明。
[实施例1]
准备厚度625μm、直径150mm的硅基板作为芯基板,在该芯基板的一个面上涂布酚醛类的正型抗蚀剂材料(东京应化工业(株)制PMER-P-LA900PM),经由通孔形成用的光掩模曝光、显影。由此,形成下述的掩模图形:具有开口直径10μm、30μm、70μm、100μm四种圆形开口,并且开口直径10μm的开口的间距为20μm,开口直径30μm的开口的间距为60μm,开口直径70μm的开口的间距为150μm,开口直径100μm的开口的间距为200μm。
接下来,以该掩模图形作为掩模,在芯基板上通过ICP-RIE(InductiveCoupled Plasma-Reactive Ion Etching)进行干蚀刻,形成多个微细孔。该微细孔的深度约为250μm。
接下来,除去不需要的掩模图形,然后研磨芯基板的反面,使微细孔露出从而形成通孔。由此,得到具有通孔的基板(厚度200μm)。
接下来,在该芯基板的一个面上通过溅镀法形成包括由钛构成的厚度30nm的层和由铜构成的厚度200nm的层的层叠结构的基底导电层。
接下来,以基底导电层为籽层,使用组成如下的区域镀敷液(フイルドめつき液),进行5小时的电解镀敷(平均电流密度1A/dm2),由此从芯基板的反面开始实施铜镀敷,在通孔内填充铜。
(区域镀敷液的组成)
硫酸 ……50g/L
硫酸铜 ……200g/L
氯离子 ……50mg/L
添加剂(上村工业(株)制ESA21-A) ……2.5mL/L
添加剂(上村工业(株)制ESA21-B) ……10mL/L
接下来,研磨除去芯基板上的多余的铜覆盖膜、基底导电层,从而能够得到具有被导电材料填充的通孔的基板。
对于如上述那样制作的具有被导电材料填充的通孔的基板,通过光学显微镜观察通孔内的导电材料(铜)的填充状态,结果确认为没有间隙部的致密结构。
[实施例2]
将基底导电层的形成从溅镀法切换为蒸镀法,形成包括由钛构成的厚度30nm的层和由铜构成的厚度200nm的层的层叠结构的基底导电层,并且作为区域镀敷液使用组成如下的区域镀敷液,除此以外与实施例1相同,来制作具有被导电材料填充的通孔的基板。
(区域镀敷液的组成)
荏原ユ一ジライト(株)制CU-BRITE VFII A ……50mL/L
荏原ユ一ジライト(株)制CU-BRITE VFII B ……4mL/L
硫酸 ……50g/L
硫酸铜 ……200g/L
盐酸 ……40g/L
对于这样制作的具有被导电材料填充的通孔的基板,通过光学显微镜观察通孔内的导电材料(铜)的填充状态,结果确认为没有间隙部的致密结构。
[比较例]
首先,与实施例1同样,制作具有通孔的芯基板(厚度200μm)。
接下来,通过MO-CVD(Metal Organic-Chemical Vapor Deposition),在芯基板的两面和通孔内形成由铜构成的基底导电层(厚度200nm)。
接下来,以基底导电层为籽层,通过与实施例1同样的区域镀敷液以及镀敷条件进行电解镀敷,由此在芯基板的两面上实施铜镀敷,在通孔内填充铜。
接下来,研磨除去芯基板上的多余的铜覆盖膜、基底导电层,从而得到具有被导电材料填充的通孔的基板。
对于如上述那样制作的具有被导电材料填充的通孔的基板,通过光学显微镜观察通孔内的导电材料(铜)的填充状态,结果确认为在长度200μm的通孔中在最大约100μm的长度范围内分散分布有空隙部。
工业应用前景
在各种配线基板、多层配线基板、电子设备等的制造中十分有用。
Claims (7)
1.一种具有被导电材料填充的通孔的基板的制造方法,其在通孔内填充导电材料从而使正反面导通,其中,包括:
在具有通孔的芯基板的一个面上形成基底导电层的工序,该基底导电层具有与所述通孔对应的开口部;和
以该基底导电层为籽层,通过电解镀敷,在所述基底导电层上淀积导电材料,并在所述开口部淀积导电材料将该开口部封闭,从该封闭部位向所述通孔的内部方向淀积、生长导电材料,在所述通孔内填充导电材料的工序。
2.如权利要求1所述的具有被导电材料填充的通孔的基板的制造方法,其中,通过利用了等离子体的干蚀刻法在芯基板上贯穿设置开口直径在10~100μm的范围内的通孔,从而形成所述具有通孔的芯基板。
3.如权利要求1所述的具有被导电材料填充的通孔的基板的制造方法,其中,从芯基板的一个面开始,通过利用了等离子体的干蚀刻法贯穿设置开口直径在10~100μm的范围内的微细孔直到规定的深度,然后研磨芯基板的另一个面使所述微细孔露出从而成为通孔,由此形成所述具有通孔的芯基板。
4.如权利要求1所述的具有被导电材料填充的通孔的基板的制造方法,其中,通过蒸镀法、溅镀法中的任意一种来形成所述基底导电层。
5.如权利要求1所述的具有被导电材料填充的通孔的基板的制造方法,其中,将所述通孔形成为开口直径在10~70μm的范围内。
6.如权利要求1所述的具有被导电材料填充的通孔的基板的制造方法,其中,所述芯基板为硅基板。
7.如权利要求1所述的具有被导电材料填充的通孔的基板的制造方法,其中,所述导电材料为铜。
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JP特开2003-60343A 2003.02.28 |
JP特开2004-193295A 2004.07.08 |
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WO2006057175A1 (ja) | 2006-06-01 |
CN101066004A (zh) | 2007-10-31 |
US8196298B2 (en) | 2012-06-12 |
EP1830614A4 (en) | 2010-12-08 |
EP1830614B1 (en) | 2015-09-09 |
EP1830614A1 (en) | 2007-09-05 |
KR20070088643A (ko) | 2007-08-29 |
JP4564343B2 (ja) | 2010-10-20 |
JP2006147971A (ja) | 2006-06-08 |
US20080092378A1 (en) | 2008-04-24 |
US7918020B2 (en) | 2011-04-05 |
KR100934913B1 (ko) | 2010-01-06 |
US20110023298A1 (en) | 2011-02-03 |
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