CN106575623A - 用于低剖面基板的图案间图案 - Google Patents
用于低剖面基板的图案间图案 Download PDFInfo
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- CN106575623A CN106575623A CN201580019675.3A CN201580019675A CN106575623A CN 106575623 A CN106575623 A CN 106575623A CN 201580019675 A CN201580019675 A CN 201580019675A CN 106575623 A CN106575623 A CN 106575623A
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- 239000000758 substrate Substances 0.000 title claims abstract description 107
- 229910052751 metal Inorganic materials 0.000 claims abstract description 156
- 239000002184 metal Substances 0.000 claims abstract description 156
- 238000000034 method Methods 0.000 claims description 25
- 238000004806 packaging method and process Methods 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000005553 drilling Methods 0.000 claims 1
- 238000009713 electroplating Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 230000008569 process Effects 0.000 description 10
- 239000004020 conductor Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
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- 239000004065 semiconductor Substances 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
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- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
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- YTCQFLFGFXZUSN-BAQGIRSFSA-N microline Chemical compound OC12OC3(C)COC2(O)C(C(/Cl)=C/C)=CC(=O)C21C3C2 YTCQFLFGFXZUSN-BAQGIRSFSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
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- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
公开了包括形成在第一图案化金属层中间的第二图案化金属层的集成电路(IC)基板。形成在第一图案化金属层上的介电层将这两个金属层分隔开。非导电层形成在介电层和第二图案化金属层上。
Description
H·B·蔚,C-K·金,D·W·金,
J·S·李,K-P·黄,Y·K·宋
相关申请的交叉引用
本申请要求于2014年4月15日提交的美国非临时申请No.14/253,798的优先权,其全部内容通过援引纳入于此。
技术领域
本申请涉及集成电路器件中的基板,尤其涉及包括金属图案中间的金属图案的基板,以提供低剖面基板。
背景技术
为了制造集成电路(IC)器件,通常使用光刻。光刻使用光敏光致抗蚀材料和受控曝光在基板的表面上产生三维图案。一般而言,抗蚀剂被涂布在基板表面上作为聚合物溶液。随后烘培抗蚀剂,这会除去溶剂。接着,抗蚀剂暴露于受控光。光穿过限定期望图案的掩模。该图案被转移至抗蚀剂,并且抗蚀剂被用于将该图案转移至底层基板。以此方式,可以彼此叠加地构建层以形成期望的IC器件。
一个层级上的图案化导电材料通常通过电介质材料层与另一层级上的图案化导电材料电绝缘。图1解说了根据现有技术的具有第一图案化金属层104和第二图案化金属层108的IC基板100。第一图案化金属层104形成在基板102上。介电层106形成在第一图案化金属层104上方并且将第二图案化金属层108与第一图案化金属层104分隔开。第二图案化金属层108形成在电介质材料106上。这两个图案化金属层之间的空间110仅被电介质材料106占用,从而占据了空间并且向IC基板100添加了不想要的厚度。
图2A-2J解说了通常用于在基板上形成图案化金属层的方法。在图2A中,提供了基板200,其具有形成在基板200上的第一金属层202。在图2B中,光致抗蚀剂层204形成在第一金属层202的顶上,并且在图2C中,光致抗蚀剂层204被图案化以包括将第一金属层202的各部分暴露于后续蚀刻的各种开口。在图2D中,使用光致抗蚀剂层204来图案化第一金属层202。在图2E中,光致抗蚀剂层204被移除,从而留下第一图案化金属层202。在图2F中,介电层206形成在第一图案化金属层202上方。在图2G中,光致抗蚀剂层208形成在介电层206的顶上。在图2H中,光致抗蚀剂层208被图案化和蚀刻以暴露介电层206的各部分。在图2I中,第二金属210沉积在介电层206的暴露部分上,并且在图2I中,光致抗蚀剂层208被移除,从而留下第二图案化金属层210和第一图案化金属层202,其中介电层206将这两个金属层分隔开。
半导体IC设计、处理、和封装技术的进步已导致基板中的特征数目和密度的增大。尽管如此,便携式电子系统(诸如便携式计算机、蜂窝电话、PDA等)的尺寸持续缩减,而不管新特征和功能的添加。新特征和功能性(诸如数码相机和摄像机、全球定位系统、以及可移除存储卡)不断地被集成到现代便携式和/或高密度电子系统中。因此期望减小便携式电子系统内的组件厚度以提供尺寸缩减及附加空间来添加新组件。
因此,在本领域中需要薄的低剖面基板。
概述
为了提供具有减小的厚度和高度的IC基板,公开了包括形成在第一图案化金属层中间的第二图案化金属层的IC基板。换言之,第二图案化金属层的各部分位于第一图案化金属层的各部分当中。电介质层将第一图案化金属层与第二图案化金属层分隔开。非导电层形成在介电层和第二图案化金属层上。在示例性实施例中,这些金属层包括铜。在一个实施例中,IC基板包括封装基板,诸如有机基板。替换地,IC基板可包括半导体基板(管芯)。本公开的IC基板不仅具有减小的高度,而且还具有改善的布线密度、更高的机械稳定性、以及改善的电性能。
在各种实施例中,介电层比传统实现中更薄并且允许第二图案化金属层更加靠近第一图案化金属层。在一些实施例中,介电层的厚度是均匀的。在一示例性实施例中,介电层为约10μm厚。在另一实施例中,介电层遵循第一图案化金属层的形状。可使用真空涂敷来形成介电层。
附图简述
图1是根据现有技术的具有第一和第二图案化金属层的IC基板的横截面视图。
图2A-2J是根据现有技术的IC基板在各种制造阶段的横截面视图。
图3A是根据本公开的一实施例的具有图案间图案的IC基板的横截面视图。
图3B是根据本公开的一实施例的具有图案间图案的IC基板的横截面视图。
图4是根据本公开的一实施例的包括具有图案间图案的IC基板的集成电路封装。
图5A-5H是根据本公开的一实施例的用于制造具有图案间图案的IC基板的序列的横截面视图。
图6是根据本公开的一实施例的具有图案间图案的IC基板的制造方法的流程图。
图7解说了根据本公开的一实施例的纳入了具有图案间图案的IC基板的一些示例电子系统。
本公开的各实施例及其优势通过参考以下详细描述而被最好地理解。应当领会,在一个或多个附图中,相同的参考标记被用来标识相同的元件。
详细描述
为了满足本领域中对具有减小的厚度和高度的IC基板的需要,提供了包括形成在第一图案化金属层中间的第二图案化金属层的IC基板。介电层将第一图案化金属层与第二图案化金属层分隔开。介电层是用于将第一图案化金属层与第二图案化金属层分隔开且电绝缘的装置。非导电层形成在介电层和第二图案化金属层上。在一个实施例中,IC基板包括封装基板,诸如有机基板。替换地,IC基板可包括管芯基板。
概览
图3A示出了示例IC基板300,其包括基板302、第一图案化金属层304、介电层306、第二图案化金属层308、以及非导电层310。金属层304、308可包括铜、镍、或其他用于导电的合适金属(诸如银或金)。介电层306覆盖并遵循第一图案化金属层306的形状。介电层306通常包括氧化物(例如,二氧化硅)、或任何其他合适的材料,诸如磷硅玻璃(PSG)或硼磷硅玻璃(BPSG)。第二图案化金属层308形成在介电层306上,延伸超过第一图案化金属层304,并且基本上平行于第一图案化金属层304。第二图案化金属层308形成在第一图案化金属层304中间。非导电层310形成在第二图案化金属层308和介电层306上。在各种实施例中,非导电层310包括电介质材料、预浸材料(例如,环氧树脂)、有机材料、或其组合。
基板302可包括封装基板或管芯基板。基板302可包括各种各样的形式,诸如有机基板或半导体基板。可以容易地领会到,本公开独立于基板的类型。
当基板230包括封装基板时,基板302包括用于穿过基板302运送功率、接地、和信号的导电层(例如,第一和第二图案化金属层304、308)。在一实施例中,导电层由铜形成,但是也可以使用其他导电材料,诸如锡、铅、镍、金、钯、或其他材料。基板302中的非导电材料可由有机材料(诸如环氧树脂材料)形成。
当基板302包括管芯基板时,基板302可包括合适的半导体材料,诸如硅、锗、碳化硅、砷化镓、砷化铟、和磷化铟。基板302可包括各种其他特征,诸如p型掺杂区和/或n型掺杂区、隔离特征、栅极堆叠、层级间电介质(ILD)层、和导电特征(例如,第一和第二图案化金属层304、308)。
参考回到图3A,与传统实现形成对比,通常仅被电介质材料占据的空间现在被使用并且包括第二图案化金属层308。可使用此空间是因为介电层306涂敷在第一图案化金属层304上以遵循第一图案化金属层304的形状。在过去,介电层被毯覆沉积来覆盖第一图案化金属层以形成厚介电块,而不管第一图案化金属层的形状。
形成在第一图案化金属层304上方的介电层306比传统实现中更薄,并且允许第二图案化金属层308更加靠近第一图案化金属层304。因此,第二图案化金属层308可形成在第一图案化金属层304中间。在一示例性实施例中,介电层306为约10μm厚。更薄的介电层306以及彼此间隔更加靠近的金属层304、308一起提供具有减小的厚度/高度的IC基板。尽管使用了更薄的介电层306,但是介电层306仍可用作减少高速/关键信号路由的耦合和干扰的保护轨而不会增大基板面积。
由于金属层306、308可以更加靠近地形成在一起,因此实现了若干优点。第一,IC基板300具有改善的布线密度(例如,在区域中提供更多特征)。这种增大的密度向IC基板300提供更高的机械稳定性。第二,IC基板300具有改善的电性能。例如,基板300中的导线(例如,金属层306、308)存在减小的环路电感,因为这些导线更靠近在一起。当导线更靠近在一起时,电流行进的环路变得更小。较大的环路创建较强的磁场,并且导致比较小的环路更大的电感。在封装基板实施例中,由于更薄的封装厚度而存在减小的封装电感。而且,可在设计定向耦合器、滤波器和电感器时使用较佳的容限/控制和减小的耦合距离而不会增大基板面积。
在示例性实施例中,介电层306以均匀厚度涂敷在第一图案化金属层304上。例如,厚度T1基本上与厚度T2相同。在使用严格控制的介电工艺(诸如真空涂敷)的情况下,介电层306的厚度可被制作成非常均匀。此受控介电工艺允许形成厚线和细线金属图案两者。例如,如图3A所示,第二图案化金属层308包括具有较大宽度W1和较薄宽度W2的部分。在其他实施例中,第二图案化金属层308包括具有基本上相同宽度的部分。
图3B解说了具有构建有形成在第一图案化金属层304中间的第二图案化金属层308的基板302以提供具有减小的厚度或高度的低剖面基板的IC基板300。第一图案化金属层304通过介电层306与第二图案化金属层308分隔开。非导电层310形成在第二图案化金属层308上方。在各种实施例中,第一图案化金属层304通过通孔312耦合至第二图案化金属层308。
在一示例性实施例中,根据传统实现所制备的IC基板的厚度为约656微米。当IC基板根据本公开被制备成具有形成在第一图案化金属层中间的第二图案化金属层时,该基板的厚度被减小至约586微米。这是约70微米或约10.7%的厚度差。
封装和管芯基板实施例
图4解说了包括根据本公开的一个或多个实施例的基板的倒装芯片封装400。封装400包括管芯基板410(例如,集成电路管芯)和封装基板420(诸如有机封装基板)。管芯410藉由如倒装芯片封装领域中已知的焊料凸块412与封装基板420电(且机械)互连。替换地,凸块412可由铜柱或其他合适的互连来替代。更一般地,封装400包括用于诸如通过使用凸块412(例如,焊料凸块、或铜柱)将管芯410导电地互连至封装基板420的装置。封装基板420经由焊球422耦合至印刷电路板330。
在一个实施例中,管芯基板410包括根据本公开的具有形成在其他图案化金属层中间的图案化金属层的基板。在另一实施例中,封装基板420包括根据本公开的具有形成在其他图案化金属层中间的图案化金属层的基板。在又一实施例中,管芯基板410和封装基板420两者均包括根据本公开的具有形成在其他图案化金属层中间的图案化金属层的基板。
示例制造方法
图5A到图5H解说了用于形成IC基板(诸如图3A-3B的IC基板300)的制造步骤。
在图5A中,IC基板开始于在基板500上形成第一图案化金属层502。第一图案化金属层502和基板500涂敷有介电层504。介电层504遵循第一图案化金属层502的形状。在一示例性实施例中,使用真空涂敷来将介电层504沉积在第一图案化金属层502和基板500上。真空涂敷提供对膜厚度的精确控制以及均匀膜的沉积。在各种实施例中,使用真空涂敷来将较薄的介电膜沉积在第一图案化金属层502和基板500上。在一个实施例中,介电层504的厚度为约10μm。
在图5B中,金属晶种层506沉积在介电层504的顶上。金属晶种层506可包括任何合适的金属,诸如铜或钴。在一实施例中,通过物理气相沉积(PVD)或化学气相沉积(CVD)来沉积金属晶种层506。
图5C解说了在金属晶种层506上方沉积光致抗蚀剂层508。例如,光致抗蚀剂层508可使用旋涂式涂敷方法、CVD、等离子体增强化学气相沉积(PECVD)、低能量化学气相沉积(LECVD)、蒸镀、以及类似方法来沉积。
图5D解说了图案化光致抗蚀剂层508以形成暴露金属晶种层506的各部分的开口510。本领域中已知的任何合适的图案化方法可被用于图案化光致抗蚀剂层508。通常,图案化涉及辐射光致抗蚀剂层508的一部分以及显影。在曝光的一个示例中,光致抗蚀剂层508由辐射波束穿过具有预定义图案的掩模来选择性地曝光。在一个示例中,辐射波束包括紫外(UV)光。在曝光工艺之后,光致抗蚀剂层508通过热烘培工艺(称为曝光后烘培(PEB))来进一步处理。PEB可在光致抗蚀剂层508的曝光部分中引发一连串化学变换,其被变换成使光致抗蚀剂层508在显影剂中具有增大或减小的溶解度。此后,光致抗蚀剂层508被显影以使得曝光的抗蚀剂部分在显影工艺期间:(1)溶解并冲走或者(2)保留。
在图5E中,开口510填充有导电材料512且光致抗蚀剂层508被移除。根据一个实施例,使用常规电镀规程或电解沉积来沉积导电材料512。导电材料512可以是例如铜或镍。光致抗蚀剂层508可通过诸如湿法剥离或氧等离子灰化之类的工艺来移除。
在图5F中,蚀刻掉金属晶种层506的未被导电材料512覆盖的部分。导电材料512形成在第一图案化金属层502中间的第二图案化金属层512。第二图案化金属层512通过介电层504与第一图案化金属层502分隔开。此图案间图案特征提供具有减小的厚度或高度的基板。
在图5G中,非导电层(例如,介电层或预浸层)形成在介电层504和第二图案化金属层512上方。在图5H中,用于通孔的开口516形成在非导电层514和介电层504中。在一示例性实施例中,非导电层514和介电层504被蚀刻或激光钻孔以形成用于通孔的开口516。如可看出的,通孔可形成在第一图案化金属层502和第二图案化金属层两者上。
制造方法流程图
通用于本文中所讨论的各种实施例的制造过程可被概述为如图6的流程图中所示。第一步骤600包括在基板上形成第一图案化金属层。例如,此步骤在图5A中解说。第二步骤605包括在第一图案化金属层上形成介电层。该步骤的示例在图5A中示出。在各种实施例中,使用真空涂敷将介电层形成在第一图案化金属层上。使用真空涂敷所形成的介电层可具有均匀厚度。此过程包括在介电层上形成第二图案化金属层的步骤610。第二图案化金属层形成在第一图案化金属层之间。例如,此步骤在图5C-5F中解说。最后,此过程包括在介电层和第二图案化金属层上形成非导电层的步骤615。例如,此步骤在图5G中解说。
示例电子系统
包括如本文中所公开的IC基板的集成电路封装可被纳入到各种各样的电子系统中。例如,如图7所示,蜂窝电话700、膝上型设备705和平板PC 710都可包括纳入了根据本公开所构造的基板的集成电路封装。其他示例性电子系统(诸如音乐播放器、视频播放器、通信设备和个人计算机)也可以用根据本公开构建的集成电路封装来配置。
如本领域普通技术人员至此将领会的并取决于手头的具体应用,可以在本公开的设备的材料、装置、配置和使用方法上做出许多修改、替换和变动而不会脱离本公开的精神和范围。有鉴于此,本公开的范围不应当被限定于本文中所解说和描述的特定实施例(因为其仅是作为本公开的一些示例),而应当与所附权利要求及其功能等效方案完全相当。
Claims (30)
1.一种集成电路(IC)基板,包括:
形成在基板上的第一图案化金属层;
形成在所述第一图案化金属层上的介电层;
形成在所述介电层上并且在所述第一图案化金属层中间的第二图案化金属层;以及
形成在所述介电层和所述第二图案化金属层上的非导电层。
2.如权利要求1所述的IC基板,其特征在于,所述介电层遵循所述第一图案化金属层的形状。
3.如权利要求1所述的IC基板,其特征在于,所述介电层具有均匀的厚度。
4.如权利要求3所述的IC基板,其特征在于,所述介电层为约10μm厚。
5.如权利要求1所述的IC基板,其特征在于,所述介电层包括二氧化硅。
6.如权利要求1所述的IC基板,其特征在于,所述第一图案化金属层和第二图案化金属层包括铜。
7.如权利要求1所述的IC基板,其特征在于,所述第二图案化金属层基本上平行于所述第一图案化金属层。
8.如权利要求1所述的IC基板,其特征在于,所述第二图案化金属层包括具有不同宽度的部分。
9.如权利要求1所述的IC基板,其特征在于,所述非导电层包括介电材料、预浸材料、有机材料、或其组合。
10.如权利要求1所述的IC基板,其特征在于,所述IC基板包括封装基板。
11.如权利要求10所述的封装基板,其特征在于,所述封装基板被纳入到以下至少一者中:蜂窝电话、膝上型设备、平板设备、音乐播放器、通信设备、计算机、和视频播放器。
12.一种集成电路(IC)基板,包括:
形成在基板上的第一图案化金属层;
形成在所述第一图案化金属层中间的第二图案化金属层;
形成在所述第二图案化金属层上的非导电层;
形成在所述非导电层上的第三图案化金属层;以及
形成在所述第三图案化金属层中间的第四图案化金属层。
13.如权利要求12所述的IC基板,其特征在于,进一步包括形成在所述第一图案化金属层上的第一介电层和形成在所述第三图案化金属层上的第二介电层。
14.如权利要求13所述的IC基板,其特征在于,所述第一介电层遵循所述第一图案化金属层的形状且所述第二介电层遵循所述第三图案化金属层的形状。
15.如权利要求13所述的IC基板,其特征在于,所述第一介电层和所述第二介电层具有均匀的厚度。
16.如权利要求15所述的IC基板,其特征在于,所述第一介电层和所述第二介电层为约10μm厚。
17.如权利要求12所述的IC基板,其特征在于,所述第二图案化金属层基本上平行于所述第一图案化金属层且所述第四图案化金属层基本上平行于所述第三图案化金属层。
18.如权利要求12所述的IC基板,其特征在于,所述第二图案化金属层和所述第四金属层各自包括具有不同宽度的部分。
19.如权利要求12所述的IC基板,其特征在于,进一步包括将所述第二图案化金属层电连接至所述第三图案化金属层的多个通孔。
20.如权利要求19所述的IC基板,其特征在于,所述多个通孔延伸穿过所述非导电层。
21.一种方法,包括:
在基板上形成第一图案化金属层;
在所述第一图案化金属层中间形成第二图案化金属层;以及
在所述第二图案化金属层上形成非导电层。
22.如权利要求21所述的方法,其特征在于,进一步包括在所述第一图案化金属层上形成介电层。
23.如权利要求22所述的方法,其特征在于,形成所述介电层包括在所述第一图案化金属层上真空涂敷所述介电层。
24.如权利要求21所述的方法,其特征在于,形成所述第二图案化金属层包括光刻过程。
25.如权利要求21所述的方法,其特征在于,形成所述第二图案化金属层包括电镀过程。
26.如权利要求21所述的方法,其特征在于,进一步包括在所述非导电层中形成开口。
27.如权利要求26所述的方法,其特征在于,形成开口包括对所述非导电层进行激光钻孔。
28.一种设备,包括:
基板上的第一图案化金属层;
所述第一图案化金属层中间的第二图案化金属层;
用于将所述第一图案化金属层与所述第二图案化金属层分隔开的装置;以及
形成在所述装置和所述第二图案化金属层上的非导电层。
29.如权利要求28所述的设备,其特征在于,所述装置包括形成在所述第一图案化金属层上的介电层。
30.如权利要求29所述的设备,其特征在于,所述介电层遵循所述第一图案化金属层的形状。
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US14/253,798 US9269610B2 (en) | 2014-04-15 | 2014-04-15 | Pattern between pattern for low profile substrate |
US14/253,798 | 2014-04-15 | ||
PCT/US2015/025435 WO2015160671A1 (en) | 2014-04-15 | 2015-04-10 | Pattern between pattern for low profile substrate |
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US (1) | US9269610B2 (zh) |
EP (1) | EP3132469B1 (zh) |
JP (1) | JP2017517142A (zh) |
KR (1) | KR20160145572A (zh) |
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CN109346821A (zh) * | 2018-09-19 | 2019-02-15 | 中国科学院上海微系统与信息技术研究所 | 圆片级硅基集成小型化分形天线及其制备方法 |
US12044965B2 (en) * | 2020-02-12 | 2024-07-23 | Hutchinson Technology Incorporated | Method for forming components without adding tabs during etching |
US20220093505A1 (en) * | 2020-09-24 | 2022-03-24 | Intel Corporation | Via connections for staggered interconnect lines |
US20230395506A1 (en) * | 2022-06-06 | 2023-12-07 | Intel Corporation | Self-aligned staggered integrated circuit interconnect features |
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- 2015-04-10 JP JP2016562244A patent/JP2017517142A/ja active Pending
- 2015-04-10 KR KR1020167028148A patent/KR20160145572A/ko unknown
- 2015-04-10 BR BR112016023947A patent/BR112016023947A2/pt not_active IP Right Cessation
- 2015-04-10 WO PCT/US2015/025435 patent/WO2015160671A1/en active Application Filing
- 2015-04-10 EP EP15718725.3A patent/EP3132469B1/en not_active Not-in-force
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WO2015160671A1 (en) | 2015-10-22 |
WO2015160671A9 (en) | 2016-06-09 |
BR112016023947A2 (pt) | 2017-08-15 |
EP3132469B1 (en) | 2019-01-09 |
US20150294933A1 (en) | 2015-10-15 |
JP2017517142A (ja) | 2017-06-22 |
KR20160145572A (ko) | 2016-12-20 |
US9269610B2 (en) | 2016-02-23 |
EP3132469A1 (en) | 2017-02-22 |
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