GB2252668A - Interlayer contact structure - Google Patents
Interlayer contact structure Download PDFInfo
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- GB2252668A GB2252668A GB9108853A GB9108853A GB2252668A GB 2252668 A GB2252668 A GB 2252668A GB 9108853 A GB9108853 A GB 9108853A GB 9108853 A GB9108853 A GB 9108853A GB 2252668 A GB2252668 A GB 2252668A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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Abstract
Conductive or insulating pads (35a) are provided beneath a lower conductive layer (50) so that its separation from an upper conductive layer (55) may be reduced at points where an interlayer contact (100) is to be formed. Poor contact due to poor step coverage in forming the upper conductive layer where the via holes are excessively deep is thereby avoided. <IMAGE>
Description
22r.
1 INTERLAYER CONTACT STRUCTURE OF A SEMICONDUCTOR DEVICE AND THE FABRICATION METHOD THEREOF The present invention relates to a semiconductor device and the fabrication method therefor, and particularly to an interlayer contact structure of a semiconductor device and the fabrication method therefor, which facilitates contact between two conductive layers by forming a pad directly under the center of a via hole connecting a lower conductive layer to an upper conductive layer.
Along with the miniaturization of LSI, several physical limitation problems appear in relation to the contacts. Among them are: broken conductive layers caused by the increase in geometric step, an electromigration of the conductive material generated by the miniaturization, of the device and the high resistance of the conductive layers, and stress migration.
The multilevel interconnection technique is suggested to solve the problems due to the fineness of the conductive layer in order to manufacture highly reliable and highly integrated semiconductor devices. This technique comprises the steps of forming an interlayer insulating layer by coating an insulating material on a semiconductor substrate on which a lower conductive layer has been formed; forming a via hole by partially removing the interlayer insulating layer formed on the lower conductive layer; and connecting a conductive material to the lower conductive layer by filling the via hole with conductive material.
The multilevel interconnection technique as described 2 above uses wiring in two or three levels instead of the conventional conductive layers integrated in a single level. Thus, in contrast to a conventional wiring technique which reveals integration limitations due to resistance consumed power, a highly integrated conductive layer is possible and also the resistance of the conductive layer itself can be reduced, thereby improving the electrical characteristics of the device.
The reliability of multilevel interconnection is dependent on not, only the conductive layer but also the interlayer contact technique which electrically connects the conductive layer to another. A conventional interlayer contact method will be described with reference to FIG.1 of the accompanying drawings.
With reference to FIG.1, the conventional multilevel interconnection method is described from the standpoint of the surface of a semiconductor substrate 10 having a certain impurity doped region and being electrically insulated by an insulating layer 12 and a pattern 30 being formed, thereby forming a step on the surface of the semiconductor substrate and making it uneven. This will explain the problems generated by an uneven surface when a lower conductive layer is connected to an upper one.
A lower conductive layer 50 is formed by forming a first insulating layer 14 on the whole surface of the semiconductor substrate whose surface is uneven due to pattern 30, electrically insulating the pattern, and laminating and patterning a conductive material. Successively, a via hole for contact with an upper conductive layer is formed by opening a 3 section of a planarized interlayer insulating layer 18 which is formed on the f irst insulating layer on which a lower conductive layer has been formed. The upper conductive layer is formed by depositing a conductive material on the interlayer insulating layer in which the via hole has been formed, and patterning the conductive material. The interlayer contact is completed by connecting the lower conductive layer with the upper one.
The method for forming an interlayer contact structure for opening a via hole in a planarized interlayer insulating layer and connecting two conductive layers is advantageous in that the process for forming conductive layers does not result in an uneven surface because an evensurfaced planarized layer is provided since a planarized interlayer structure is first established and then the upper conductive layer is formed. However, the overall depth of the planarized interlayer insulating layer is unequal, because the surface state of the lower structure is not planarized.
Referring to FIG.1, the thickness of the interlayer insulating layer with respect to the lower conductive layer 50 has a difference at the thinnest region a and the thickest region c which is greater than or equal to the step of the lower structure. When the via hole for the interlayer contact is formed within region c of the thick interlayer insulating layer, the depth of the via hole becomes equal to c, thereby deteriorating the step coverage of the conductive material to be successively deposited. Also, the step coverage varies with the aspect ratio (thickness/width) of the via hole with a given coated material. It is generally considered as obvious to those skilled in the art 4 that step coverage deteriorates as the aspect ratio becomes larger.
When a metal material is deposited on a semiconductor substrate having several kinds of holes, if the step coverage of the metal material is poor or the depth of the hole to be created is deep, the metal material f orms a void in the hole or, as pictured in FIG. 1, thins the conductive layer at the junction of the lower conductive layer and the hole, thereby resulting in a poor contact which is highly resistive and subject to breaks.
It is an object of the present invention to provide an interlayer contact structure of a semiconductor device which solves the poor contact problem caused by a deep via hole in a conventional interlayer contact arrangement.
It is another object of the present invention to provide a fabrication method for forming the interlayer contact structure which is specifically adapted to the aforesaid interlayer contact.
It is further another object of the present invention to provide a method for forming a planarized conductive layer on an uneven surface of a semiconductor substrate.
According to one aspect of the present invention, in forming an interlayer contact through a via hole on a semiconductor substrate having a stepped surface, an interlayer contact structure of a semiconductor device comprises:
via hole formed in an interlayer insulating layer; lower conductive layer and an upper conductive layer connected through the via hole; and a pad formed directly under the via hole and beneath the lower conductive layer.
According to another aspect of the present invention, an interlayer contact method for a semiconductor device to form multilevel conductive layers on a semiconductor substrate having stepped surface, comprises the steps of:
forming a first insulating layer over the whole surface of the semiconductor substrate; forming a pad material on the first insulating layer; forming a pad directly under the location where the via hole will be formed, by a photolithography process; forming a second insulating layer over the whole surface of the first insulating layer on which a pad has been formed; depositing and patterning a conductive material on the second insulating layer so as to form a lower conductive layer; forming an interlayer insulating layer on the whole surface of the second insulating layer on which the lower conductive layer has been formed; forming a via hole in the interlayer insulating layer; and f orming an upper conductive layer connected to the lower conductive layer by filling the via hole.
According to a further aspect of the invention, there is provided a method for forming a planarized conductive layer on an uneven surf ace of a semiconductor substrate which comprises the steps of:
forming a first insulating layer over the whole surface of the semiconductor substrate; 6 forming a pad material on the first insulating layer; forming a pad between steps in a region where a conductive layer will be formed; forming a second insulating layer on the whole surf ace of the first insulating layer on which the pad has been formed; and depositing and patterning a conductive material on the second insulating layer, thereby forming a conductive layer.
Embodiments of the present invention will now be described, by way of example, with reference to the attached drawings, in which:
FIG. 1 is a sectional view showing a conventional interlayer contact structure for a semiconductor device; FIG. 2 shows an interlayer contact structure of a semiconductor device according to an embodiment of the present invention; FIGs. 3A to 3E are sectional views showing a fabrication method for the interlayer contact for a semiconductor device according to an embodiment of the present invention; FIGs. 4A and 4B are sectional views showing another fabrication method of the interlayer contact for a semiconductor device according to an embodiment of the present invention; FIG. BA is a plan view showing a further fabrication method of the interlayer contact f or a semiconductor device according to an embodiment of the present invention; FIGs. 5B and 5C are sectional views taken along lines AA1 and BBI respectively, showing an interlayer contact for a semiconductor device as shown in FIG. 5A; t 7 FIGs. 6A and 6B are a plan view and a sectional view respectively, showing an interlayer contact method for a semiconductor device of yet another embodiment according to the present invention; and FIGs. 7A and 7B are a plan view and a sectional view respectively, showing an interlayer contact method for a semiconductor device of another embodiment according to the present invention.
FIG. 2 is a cross-sectional view showing an interlayer contact structure according to an embodiment of the present invention. A pad 35a is formed directly under the center of a via hole 100 and beneath a lower conductive layer 50, and lessens the depth of a gully of the uneven surface created by a pattern 30, thereby making the interlayer contact easier to accomplish.
FIGs. 3A to 3E are views showing an interlayer contact method of a semiconductor device according to an embodiment of the present invention.
First, FIG. 3A shows a semiconductor substrate with an uneven surface by an arbitrary pattern 30. The pattern 30 is formed, for instance, as a gate electrode and a bit line in a DRAM during an intermediate step of a device manufacturing process, and provides an uneven surface to its upper structure. Generally, since the pattern is made of conductive material, the pattern is electrically insulated from the upper structure by coating a first insulating layer 14 over the whole surface of the substrate on which the pattern has been formed.
FIG. 3B shows a process for forming pads 35a on the insulating layer. The pads 35a are formed by depositing a pad 8 material 35 on the first insulating layer and forming a photoresist pattern 38 on the spots directly under the desired location of the via holes and removing the part of the pad material using the photoresist pattern 38 as a mask. The thickness of the interlayer insulating layer becomes thinner by the combined thickness of a pad and the second insulating layer formed on the pad by forming the pad in the thick part c of the interlayer insulating layer, whose thick part is due to the lower structure as shown in FIG. 1. Accordingly, this process prevents the poor contact of a deep via hole. in this case, the proportions of the photoresist pattern are approximately equal to or larger than that of the via hole.
The pads are not formed wherever via holes exist, but are formed if necessary and where the interlayer insulating layer becomes thick due to the unevenness of the lower structure and if necessary. The pad can also be formed by merely extending peripheral conductive layers without any extra masking process (refer to FIGs. 5A through 5C, and FIGs. 6A and 6B).
FIG. 3C shows a process for forming a lower conductive layer 50. The lower conductive layer is formed by coating a second insulating layer 16 over the whole surface of the semiconductor substrate on which the pads 35a have been formed, laminating a conductive material onto the second insulating layer 16, and then patterning the conductive material to the desired pattern. If the pads 35a are of a conductive material, the coated second insulating layer maintains the appropriate thickness to minimize the parasitic capacitance which may exist between the pad and the lower conductive layer. If the pads are of an 9 insulating material, a pad and the coated second insulating layer have the combined thickness required to compensate for the step of the lower structure.
FIG. 3D shows a process for forming an interlayer insulating layer 18 and via holes 100. An interlayer insulating layer 18 having a planarized surface is formed on the second insulating layer 16 on which the lower conductive layer 50 has been formed. The via holes 100 for interlayer connection are formed by removing the part of the interlayer insulating layer directly above the pads 35a.
At this point, the effect of compensating for the via hole depth when the pad is of an insulating material and therefore formed only for depth compensation, is different from that of the case when the pad is formed without any extra masking process, by the extension of a peripheral conductive layer or a floated conductive material. In the depth b-t3 of the via hole in the conventional method (in which the pads and the second insulating layer do not exist) becomes the distance b- (t, + t2 + t3) in the present invention, so that the compensating effect is tl + t2. Here, b is assumed to be unchanged in its size for this embodiment of the present invention and conventional technique. In the latter case, the depth b-(t,+ t3) of the via hole in the conventional method (which considers the second insulating layer since the peripheral conductive layer can exist on any part of the substrate, even if it is not an extended pad) becomes the distance b(tj + t2 + t3), so that the thickness t, is compensated. In this description, b is the distance from the surface of the interlayer insulating layer to the surface of the first insulating layer 14 formed on the lower surface of the pad and directly pertains to both FIGs. 1 and 3D, tj is the thickness of a pad, t2 is the thickness of the second insulating layer over the pads, and t. is the thickness of the lower conductive layer.
The pads 35a. not only have the effect of compensating for the depth of via hole as described above, but also planarizes the lower conductive layer by planarizing the surface of second insulating layer 16, thereby reducing its resistance. This planarization also prevents a notching phenomenon generated when the photolithography process is carried out to f orm the lower conductive layer. Generally, when a conductive material is deposited on a substrate having an uneven surface and a photoresist layer is then coated and exposed to form a conductive layer pattern, the unequal thickness of the photoresist layer generates distortion in the pattern of the photoresist layer by overexposure or underexposure. The unequal thickness is due to the photoresist layer being coated in a melted state and having a planarized surface regardless of the evenness or unevenness of the lower structure. Preventing the notching phenomenon makes it possible to form a fine pattern and a reliable conductive layer.
FIG. 3E shows a process for forming an upper conductive layer. The upper conductive layer is formed by depositing a conductive material on the whole surface of the interlayer insulating layer in which via holes have been formed, so as to fill the holes and successively etch to pattern the upper conductive layer. Thus, a multilevel conductive layer in which the lower conductive layer and the upper conductive layer are electrically connected is completed.
1 11 According to the interlayer contact structure of a semiconductor device of the present invention, the formation of the pad directly under the via hole sets the depth of the via hole formed in the interlayer insulating layer to be one which minimizes the parasitic capacitance. Thus, poor contacts between conductive layers due to broken conductive layers, the formation of voids, and migration and resulting from poor step coverage generated by a deep via hole, is prevented. The notching phenomenon generated during lower conductive layer formation is also prevented, achieving a highly reliable interlayer contact.
FIGs. 4A and 4B illustrate another manufacturing method of the interlayer contact structure of a semiconductor device according to an embodiment of the present invention, and show a process for forming a pad on a conductive layer 58. The pads 35a are made of an insulating material on the conductive layer and since the pads compensate for the depth of the via hole, interlayer contact through the via hole can be easily accomplished.
FIGs. 5A to 5C are a plan view and sectional views showing still another manufacturing method of the interlayer contact of a semiconductor device according to an embodiment of the present invention. Since a first conductive layer and a second conductive layer encompass the periphery of the via hole, the depth of the region where a via hole will be formed is deep in the planarizing process after the lower conductive layer process.
Referring to FIG. 5A, the portions defined with solid ines and running laterally is a mask pattern P1 for forming a 12 first conductive layer pattern. The portion having an extruded side in its central part and its neighbor, both defined with long broken lines and running longitudinally is a mask pattern P2 for forming a second conductive layer. The portion def ined with a short broken line and running laterally is a mask pattern P3 for forming a lower conductive layer. The portion def ined with a single-dashed line and running longitudinally is a mask pattern P4 for forming an upper conductive layer. The Portion def ined with solid lines forming a square with diagonally crossing lines therein, and overlapped by the mask patterns P2, P3 and P4 is a mask pattern P5 for forming a via hole.
FIG. 5B is a vertical sectional view taken along the line AA1 of FIG. 5A and shows an interlayer contact structure of a semiconductor device of an embodiment of the present invention, and FIG. 5C is a vertical sectional view taken along the line BBI of FIG. 5A. With reference to these drawings, since the pad is formed by extending the peripheral conductive layer passing the periphery of the via hole, i.e., the second conductive layer pattern P2, the depth of the via hole is reduced by the thickness of the second conductive layer or more, thereby improving the step coverage of the upper conductive layer by that much.
FIGs. 6A and 6B are a plan view and a sectional view showing yet another manufacturing method of an interlayer contact structure of a semiconductor device, according to an embodiment of the present invention, and show when a via hole is formed near the second conductive layer (or a first conductive layer). The identical reference designators used in FIGs. 6A and 6B match those used in FIGs. 5A through 5C and respectively denote the 13 corresponding parts.
In this case, since the via hole is formed by extending a conductive layer passing near the via hole, i.e., a second conductive pattern in the drawings, the depth of the via hole can be reduced after the planarization process.
FIGs. 7A to 7B show a plan view and a sectional view showing a further manufacturing method of the interlayer contact structure of a semiconductor device of an embodiment of the present invention, and describes when there is no pattern to create unevenness near the via hole.
Even if there is no pattern having a step around the periphery of the via hole, the formation of a pad 74 constituted by a pad material can reduce the depth of the via hole by the thickness of the pad, thereby improving a step coverage of the second conductive layer.
As described above, a pad is formed directly under the region where a via hole will be formed, by extending peripheral conductive layers or by being electrically floated, so that the peripheral patterns prevent the depth of the via hole formed on the planarized interlayer insulating layer from becoming too deep due to the peripheral patterns. Thus, the poor contact caused by poor step coverage of the second conductive layer generated by the conventional deep via hole is improved.
The present invention is not limited in the above described embodiments and modifications can be made by those skilled in the art without departing from the scope of the invention.
14
Claims (24)
1. An interlayer contact structure of a semiconductor device on a semiconductor substrate whose surface is uneven due to steps, comprising:
via hole in an interlayer insulating layer; lower conductive layer and an upper conductive layer connected to each other through said via hole; and a pad directly under said via hole and beneath said lower conductive layer.
2. An interlayer contact structure of a semiconductor device as claimed in claim 1, wherein the width of said pad is not less than that of said via hole.
3. An interlayer contact structure of a semiconductor device as claimed in claim 1 or 2, wherein said pad is isolated from peripheral layers.
4. An interlayer contact structure of a semiconductor device as claimed in claim 1 or 2, wherein said pad is connected to another conductive layer.
5. An interlayer contact structure of a semiconductor device as claimed in any preceding claim, wherein an insulating layer is interposed between said pad and said lower conductive layer.
is
6. An interlayer contact structure of a semiconductor device as claimed in any preceding claim, wherein said pad has a thickness which is capable of compensating for said surface steps.
7. An interlayer contact structure of a semiconductor device substantially as hereinbefore described with reference to FIGs. 2 to 3E of the accompanying drawings.
8. An interlayer contact structure of a semiconductor device substantially as herein described with reference to any of Figures 2, 4B, 5A, 5B, 5C, 6A, 6B, 7A and 7B.
A semiconductor device comprising an interlayer contact structure as claimed in any preceding claim.
10. A fabrication method for an interlayer contact structure of a semiconductor device, on a semiconductor substrate whose surface is uneven due to steps comprising: forming a first insulating layer on the whole surface of said semiconductor substrate; forming a pad material on said first insulating layer; forming a photoresist pattern on said pad material and f orming a pad directly under the location where a via hole is to be formed, by a photolithography process; forming a second insulating layer over the whole surface of said first insulating layer on which said pad has been formed; 16 depositing and patterning a conductive material on said second insulating layer so as to form a lower conductive layer; forming an interlayer insulating layer on the whole surface of said second insulating layer on which said lower conductive layer has been formed; forming said via hole in said interlayer insulating layer; and forming an upper conductive layer by filling said via hole so as to be connected to said lower conductive layer.
11. A fabrication method for an interlayer contact structure of a semiconductor device as claimed in claim 10, wherein said pad material is a conductive material.
12. A fabrication method for an interlayer contact structure of a semiconductor device as claimed in claim 10 or 11, wherein said pad is electrically floated.
13. A fabrication method for an interlayer contact structure of a semiconductor device as claimed in claim 10, wherein said pad material is an insulating material.
14. A fabrication method for an interlayer contact structure of a semiconductor device as claimed in claim 10 or 11, wherein said pad is formed by extending a conductive layer formed near said via hole.
15.
A fabrication method for an interlayer contact 1 17 structure of a semiconductor device as claimed in claim 14, wherein said conductive layer is a conductive line needed for the operation of the device.
16. A fabrication method for an interlayer contact structure of a semiconductor device as claimed in claim 10, wherein said pad is formed to be isolated from the peripheral conductive layers and not to be needed for the operation of the device. 1
17. A fabrication method for an interlayer contact structure of a semiconductor device as claimed in any of claims 10 to 16, wherein said interlayer insulating layer is planarized.
18. A fabrication method for an interlayer contact structure of a semiconductor device as claimed in any of claims to 17, wherein said via hole is formed on a portion where the depth of the interlayer insulating layer is too deep due to the peripheral patterns.
19. A fabrication method for an interlayer contact structure of a semiconductor device as claimed in any of claims to 18, wherein said via hole is formed in a portion of the interlayer insulating layer having a constant depth with respect to the surface of said semiconductor substrate.
20. A method for forming a conductive layer on semiconductor substrate whose surface is uneven due to steps, 18 comprising the steps of: coating a first insulating layer over the whole surface of said semiconductor substrate; forming a pad material on said first insulating layer; f orming a pad between steps in a region where the conductive layer is to be formed; f orming a second insulating layer on the whole surf ace of the f irst insulating layer on which said pad has been formed; and depositing and patterning a conductive material on said second insulating layer, thereby forming the conductive layer.
21. A fabricating method for an interlayer contact structure of a semiconductor device on a semiconductor substrate whose surface is uneven due to steps and whose uppermost layer is composed of conductive material, comprising: forming a pad material on the whole surface of said semiconductor substrate; forming a photoresist pattern on said pad material and carrying out a photolithography process so as to form a pad directly under the location where a via hole is to be formed; forming a second insulating layer over the whole surface of the first insulating layer on which said pad has been formed; depositing and patterning a conductive material on said second insulating layer, thereby forming a lower conductive layer; forming an interlayer insulating layer on the whole t 1 -Z 19 surf ace of said second insulating layer on which said lower conductive layer has been formed; forming said via hole; and forming an upper conductive layer by filling said via hole so as to contact said lower conductive layer.
22. A fabrication method for an interlayer contact structure of a semiconductor device as claimed in claim 20, wherein said pad material is an insulating material.
23. A fabrication method for an interlayer contact structure of a semiconductor device substantially as hereinbef ore described with reference to FIGs. 2 to 3E of the accompanying drawings.
24. A method of fabricating a semiconductor device comprising the method as claimed in any of claims 10 to 23.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910001977A KR920017227A (en) | 1991-02-05 | 1991-02-05 | Interlayer contact structure of semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9108853D0 GB9108853D0 (en) | 1991-06-12 |
| GB2252668A true GB2252668A (en) | 1992-08-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9108853A Withdrawn GB2252668A (en) | 1991-02-05 | 1991-04-25 | Interlayer contact structure |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH0613468A (en) |
| KR (1) | KR920017227A (en) |
| DE (1) | DE4113775A1 (en) |
| FR (1) | FR2672430A1 (en) |
| GB (1) | GB2252668A (en) |
| IT (1) | IT1248595B (en) |
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| DE4403604C2 (en) * | 1994-02-05 | 1998-02-19 | A B Elektronik Gmbh | Device for controlling the adjustment of a throttle valve determining the performance of an internal combustion engine |
| US5770518A (en) * | 1995-04-19 | 1998-06-23 | Advanced Micro Devices, Inc. | Semiconductor device and method of manufacturing without undercutting conductive lines |
| TW480636B (en) | 1996-12-04 | 2002-03-21 | Seiko Epson Corp | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
| TW571373B (en) | 1996-12-04 | 2004-01-11 | Seiko Epson Corp | Semiconductor device, circuit substrate, and electronic machine |
| KR20150021742A (en) | 2013-08-21 | 2015-03-03 | 에스케이하이닉스 주식회사 | Semiconductor device and method of manufacturing the same |
| KR102610485B1 (en) * | 2018-11-22 | 2023-12-05 | 엘지디스플레이 주식회사 | Electroluminescent display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0061939A2 (en) * | 1981-03-31 | 1982-10-06 | Fujitsu Limited | The provision of conductors in electronic devices |
| WO1987007979A1 (en) * | 1986-06-19 | 1987-12-30 | Lsi Logic Corporation | Planarized process for forming vias in silicon wafers |
| WO1990003046A1 (en) * | 1988-05-31 | 1990-03-22 | Unisys Corporation | Integrated circuit employing dummy conductors for planarity |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61193454A (en) * | 1985-02-20 | 1986-08-27 | Mitsubishi Electric Corp | Semiconductor device |
| DE3902693C2 (en) * | 1988-01-30 | 1995-11-30 | Toshiba Kawasaki Kk | Multi-level wiring for a semiconductor integrated circuit arrangement and method for producing multi-level wiring for semiconductor integrated circuit arrangements |
| JPH02222162A (en) * | 1989-02-22 | 1990-09-04 | Sharp Corp | Manufacture of semiconductor device |
| JPH04127452A (en) * | 1989-06-30 | 1992-04-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| JP3229973B2 (en) * | 1993-02-12 | 2001-11-19 | 株式会社リコー | Thermal recording material |
-
1991
- 1991-02-05 KR KR1019910001977A patent/KR920017227A/en not_active Application Discontinuation
- 1991-04-24 IT ITMI911148A patent/IT1248595B/en active IP Right Grant
- 1991-04-25 GB GB9108853A patent/GB2252668A/en not_active Withdrawn
- 1991-04-26 JP JP3124853A patent/JPH0613468A/en active Pending
- 1991-04-26 DE DE4113775A patent/DE4113775A1/en not_active Withdrawn
- 1991-05-03 FR FR9105457A patent/FR2672430A1/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0061939A2 (en) * | 1981-03-31 | 1982-10-06 | Fujitsu Limited | The provision of conductors in electronic devices |
| WO1987007979A1 (en) * | 1986-06-19 | 1987-12-30 | Lsi Logic Corporation | Planarized process for forming vias in silicon wafers |
| WO1990003046A1 (en) * | 1988-05-31 | 1990-03-22 | Unisys Corporation | Integrated circuit employing dummy conductors for planarity |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015160671A1 (en) * | 2014-04-15 | 2015-10-22 | Qualcomm Incorporated | Pattern between pattern for low profile substrate |
| US9269610B2 (en) | 2014-04-15 | 2016-02-23 | Qualcomm Incorporated | Pattern between pattern for low profile substrate |
| CN106575623A (en) * | 2014-04-15 | 2017-04-19 | 高通股份有限公司 | Pattern between pattern for low profile substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9108853D0 (en) | 1991-06-12 |
| KR920017227A (en) | 1992-09-26 |
| JPH0613468A (en) | 1994-01-21 |
| IT1248595B (en) | 1995-01-19 |
| ITMI911148A1 (en) | 1992-10-24 |
| ITMI911148A0 (en) | 1991-04-24 |
| DE4113775A1 (en) | 1992-08-13 |
| FR2672430A1 (en) | 1992-08-07 |
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| Date | Code | Title | Description |
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| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |