JPH02222162A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02222162A JPH02222162A JP4259289A JP4259289A JPH02222162A JP H02222162 A JPH02222162 A JP H02222162A JP 4259289 A JP4259289 A JP 4259289A JP 4259289 A JP4259289 A JP 4259289A JP H02222162 A JPH02222162 A JP H02222162A
- Authority
- JP
- Japan
- Prior art keywords
- layer wiring
- wiring
- lower layer
- film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 239000004020 conductor Substances 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は半導体装置の製造方法に関し、特に多層配線を
行う半導体装置の下層配線が凹状になることを防止でき
る半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can prevent lower wiring of a semiconductor device in which multilayer wiring is performed from becoming concave.
〈従来の技術〉
以下、図面を参照して多層配線を行う半導体装置の従来
の製造方法の一例を説明する。<Prior Art> An example of a conventional method for manufacturing a semiconductor device that performs multilayer wiring will be described below with reference to the drawings.
半導体装置に多層配線を行う場合、下層配線の下地は平
坦化されていることが望ましいが、完全に平坦化するに
はプロセス的に複雑になるので、現在では主にＢＰＳＧ
（ホウ素付加リンガラス）によるリフローが行われて
いる。この場合、下層配線の下地に制約がなければ、下
層配線が凹型に形成されることがある。When performing multilayer wiring in a semiconductor device, it is desirable that the base of the lower wiring be flattened, but the process is complicated to completely flatten it, so currently BPSG is mainly used.
(Boron-added phosphorus glass) is used for reflow. In this case, if there are no restrictions on the base of the lower layer wiring, the lower layer wiring may be formed in a concave shape.
第２図（ａ）において、Ｓｉ基板１とＳｉ基板１の表面
に形成したポリシリコン導電層２ａ、２ｂとの上にリフ
ローによってＢＰＳＧ３を形成した後、ポリシリコン導
電層２ａ、２ｂのほぼ上方に、下層配線４を形成し、次
に下層配線４とＢｐｓＧＨＩＪ３との上に５ｉｎ２膜５
を形成する。そして、ＳｉＯ□膜５に、下層配線４の表
面に達するヴィアホール６を設けたのち、このヴィアホ
ール６内とＳｉＯ□膜５の表面の一部に下層配線４に接
触する上層配線７を形成する。In FIG. 2(a), after BPSG 3 is formed by reflow on the Si substrate 1 and the polysilicon conductive layers 2a and 2b formed on the surface of the Si substrate 1, the BPSG 3 is formed almost above the polysilicon conductive layers 2a and 2b. , a lower layer wiring 4 is formed, and then a 5in2 film 5 is formed on the lower layer wiring 4 and BpsGHIJ3.
form. After forming a via hole 6 in the SiO□ film 5 that reaches the surface of the lower layer wiring 4, an upper layer wiring 7 that contacts the lower layer wiring 4 is formed inside the via hole 6 and in a part of the surface of the SiO□ film 5. do.
〈発明が解決しようとする課題〉
しかしながら、このように形成した下層配線４には、第
２図（ａ）に示すように、下方に曲がった凹部４ａが形
成されるので、この凹部４ａの上表面にヴィアホール６
を形成するためにホトリソグラフィを行ったとき、ヴィ
アホール６の下地が平坦でないので、ヴイアボール６の
形状が悪くなる。ヴィアホール６の形状が悪くなると、
ヴィアホール６内に形成された上層配線７と下層配線４
との良好な接触が得られない。<Problems to be Solved by the Invention> However, as shown in FIG. 2(a), the lower layer wiring 4 formed in this manner has a downwardly curved recess 4a, so that the upper part of the recess 4a is Via hole 6 on the surface
When photolithography is performed to form the via hole 6, the shape of the via ball 6 becomes poor because the base of the via hole 6 is not flat. If the shape of via hole 6 deteriorates,
Upper layer wiring 7 and lower layer wiring 4 formed in via hole 6
Good contact cannot be obtained.
そこで、下層配線４を形成後、第２図（ｂ）に示すよう
に、５ＯＧ（Ｓｐｉｎ Ｏｎ Ｇｌａｓｓ ）塗布法に
よって、適宜の材質の塗布剤８を塗布して下層配線４の
」二部が平坦になるようにし、この後、ヴィアホール６
が形成される部分に堆積した全ての塗布剤と、下層配線
４と共に形成された酸化膜５ａの一部とをエツチングで
除去して、四部４ａ上に形成されるヴイアボール６の抵
抗が塗布剤８によって増大するのを防止する。この塗布
剤を除去する際に、しばしばエツチングが過大になり過
ぎて、下層配線４が薄くなり過ぎたり、或いは、エツチ
ングによって形成された表面の平坦度が却って悪くなる
という問題点があった。Therefore, after forming the lower layer wiring 4, as shown in FIG. 2(b), a coating agent 8 made of an appropriate material is applied using the 5OG (Spin On Glass) coating method to flatten the second part of the lower layer wiring 4. After this, Via Hall 6
By etching all the coating material deposited on the part where the oxide layer 4 is formed and a part of the oxide film 5a formed together with the lower layer wiring 4, the resistance of the via ball 6 formed on the fourth part 4a is reduced by the coating material 8. Prevent the increase due to When this coating agent is removed, there is a problem that the etching is often excessive, resulting in the lower layer wiring 4 becoming too thin, or the flatness of the surface formed by etching becoming worse.
本発明は上記事情に鑑みて創案されたものであって、下
層配線に凹部を生じることがなく、従ってＳＯＣ塗布法
によって下層配線の」二部絶縁膜を平坦にすることを必
要とゼす、それ故に良好な形状のヴイアボールを形成す
ることができる半導体装置の製造方法を提供することを
目的としている。The present invention has been devised in view of the above-mentioned circumstances, and eliminates the need to form recesses in the lower wiring, and therefore requires the SOC coating method to flatten the two-part insulating film of the lower wiring. Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a via ball with a good shape.
く課題を解決するだめの手段〉
上記問題点を解決するために、本発明の半導体装置の製
造方法は、下層配線と上層配線とこれら両配線を接続す
るためのヴィアホールとを有する半導体装置の製造方法
において、下層配線を平坦化するため、下層配線下にあ
らかじめダミーパターンを形成する。Means for Solving the Problems In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention provides a method for manufacturing a semiconductor device having a lower layer wiring, an upper layer wiring, and a via hole for connecting both wirings. In the manufacturing method, a dummy pattern is formed in advance under the lower layer wiring in order to planarize the lower layer wiring.
〈作用〉
ダミーパターンを形成した後、このダミーパターンの」
一方に絶縁膜を介して下層配線を形成しているため下層
配線に四部が生じず、下層配線上の絶縁膜に良好な形状
のヴイアポールを形成することができる。<Operation> After forming the dummy pattern,
Since the lower layer wiring is formed on one side with an insulating film interposed therebetween, a four-part portion does not occur in the lower layer wiring, and a well-shaped via pole can be formed in the insulating film on the lower layer wiring.
〈実施例〉
以下、図面を参照して本発明の一実施例を説明する。第
１図は本発明の一実施例を説明するための半導体の断面
説明図であって、この半導体はＭＯ３型トランジスタと
多層配線とを有する半導体を例にとっている。<Example> Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory cross-sectional view of a semiconductor for explaining one embodiment of the present invention, and this semiconductor is taken as an example of a semiconductor having an MO3 type transistor and multilayer wiring.
ウェーハ１００に形成したＮ型層１１の表面に、ＬＯＣ
ＯＳ酸化膜２４とゲート絶縁膜２５とを形成した後、ゲ
ート絶縁膜２５上にゲート電極２１を形成する。次に、
Ｎ型層１１の表面の一部にＰ゛型層ソース２２ａとドレ
イン２３ａ とを形成した後、ソース２２ａおよびドレ
イン２３ａにそれぞれ接触するソース電極２２およびド
レイン電極２３を形成する。またＬＯＣＯ５酸化膜２４
上には導電層１２ａ 、１２ｂおよび導電層１２ａ 、
１２ｂと同時にダミーパターン１２ｃを形成する。LOC on the surface of the N-type layer 11 formed on the wafer 100.
After forming the OS oxide film 24 and the gate insulating film 25, the gate electrode 21 is formed on the gate insulating film 25. next,
After forming a P'-type layer source 22a and drain 23a on a part of the surface of the N-type layer 11, a source electrode 22 and a drain electrode 23 are formed in contact with the source 22a and drain 23a, respectively. Also, the LOCO5 oxide film 24
On top are conductive layers 12a, 12b and conductive layers 12a,
A dummy pattern 12c is formed simultaneously with the pattern 12b.
ダミーパターン１２ｃは導電層１２ａ 、１２ｂと電気
的に接続しても良いが、特に電気的な機能をもつもので
はなく、単に下層配線１４に凹部が発生することを防止
するために設けられる。なお、ゲート電極２１、導電層
１２ａ 、１２ｂおよびダミーパターン１２Ｃはポリシ
リコンで構成されている。Although the dummy pattern 12c may be electrically connected to the conductive layers 12a and 12b, it has no particular electrical function and is provided simply to prevent the formation of a recess in the lower wiring 14. Note that the gate electrode 21, the conductive layers 12a and 12b, and the dummy pattern 12C are made of polysilicon.
次いで、ウェーハ１００の表面にＢＰＳＧ膜１３膜形３
した後、グー（・電極２１上方のＢＰＳＧ膜１３膜形３
タクト窓１３ａを形成し、このコンタクト窓１３ａ内と
、ＢＰＳＧ膜１３膜面３表面−パターン１２ｃの上方と
に、下層配線１４を形成する。次いで、ウェーハ１００
の表面に５ｉ０２膜１５を形成し、ダミーパターン１２
ｃの上方の５ｉｎ２膜５にヴィアホール１６を形成した
後、ヴィアホール１６内とヴィアホール１６に接する５
ｉ０２膜５の表面に、下層配線１４に接触する上層配線
１７を形成する。Next, a BPSG film 13 film type 3 is formed on the surface of the wafer 100.
After that, the BPSG film 13 above the electrode 21
A tact window 13a is formed, and a lower wiring 14 is formed within this contact window 13a and above the surface of the film surface 3 of the BPSG film 13 and the pattern 12c. Next, the wafer 100
A 5i02 film 15 is formed on the surface of the dummy pattern 12.
After forming a via hole 16 in the 5in2 film 5 above c,
An upper layer wiring 17 is formed on the surface of the i02 film 5 in contact with the lower layer wiring 14.
上記のように、下層配線１４の下方にはダミーパターン
１２ｃが形成されているので、下層配線１４は平坦か、
或いは上層配線１７側に若干凸状に形成され、下層配線
１４には、第２図（ａ）にて説明した四部４ａが生しる
ことばない。従って、このような下層配線１４上に形成
されたヴィアホール１６は良好な形状とすることができ
る。As mentioned above, since the dummy pattern 12c is formed below the lower layer wiring 14, the lower layer wiring 14 may be flat or flat.
Alternatively, it is formed in a slightly convex shape on the upper layer wiring 17 side, and the lower layer wiring 14 does not have the four portions 4a described in FIG. 2(a). Therefore, the via hole 16 formed on such a lower layer wiring 14 can have a good shape.
なお、上記実施例では、ダミーパターンが導電性である
場合を説明したが、導電性にこだわるものではなく、適
宜の方法で形成した絶縁性のダミーパターンを設けた場
合であっても本実施例と同等の効果を得ることができる
。更にダミーパターンの形成は上層配線１７上にも配線
層を形成する場合にも適用でき、この時は上層配線を平
坦にするため上層配線下にダミーパターンを形成すれば
よい。In addition, in the above example, the case where the dummy pattern is conductive is explained, but the conductivity is not a concern, and even if an insulating dummy pattern formed by an appropriate method is provided, this example can be applied. The same effect can be obtained. Furthermore, the formation of the dummy pattern can also be applied to the case where a wiring layer is formed on the upper layer wiring 17, and in this case, the dummy pattern may be formed under the upper layer wiring in order to flatten the upper layer wiring.
〈発明の効果〉
以上説明したように本発明の半導体装置の製造方法は、
下層配線と上層配線とこれら両扉線を接続するだめのヴ
ィアホールとを有する半導体装置の製造方法において、
前記下層配線を平坦化するためのダミーパターンをあら
かじめ形成している。<Effects of the Invention> As explained above, the method for manufacturing a semiconductor device of the present invention has the following effects:
In a method of manufacturing a semiconductor device having a lower layer wiring, an upper layer wiring, and a via hole for connecting these double door wires,
A dummy pattern for planarizing the lower layer wiring is formed in advance.
従って、本発明の半導体装置の製造方法によれば、下層
配線に四部を生じることがなく、従ってＳＯＧ塗布法に
よって下層配線の上部絶縁膜を平坦にすることを必要と
せず、それ故に良好な形状のヴィアホールを形成するこ
とができる。Therefore, according to the method of manufacturing a semiconductor device of the present invention, there is no formation of four parts in the lower layer wiring, and therefore, it is not necessary to flatten the upper insulating film of the lower layer wiring by the SOG coating method, and therefore a good shape can be obtained. via holes can be formed.
第１図は本発明の一実施例を説明するための半導体の断
面説明図である。第２図は半導体装置の従来の製造方法
を説明するだめの半導体装置の断面説明図であって、第
２図（ａ）は上層配線が形成された状態を、第２図（ｂ
）は下層配線を形成後、ＳＯＧによる塗布を行った状態
をそれぞれ示す。
１２ｃ ・・・ダミーパターン、１４・・・下層配線
、１６・・・ヴイアボール、１７・・・上層配線。
特許出願人 シャープ株式会社FIG. 1 is an explanatory cross-sectional view of a semiconductor for explaining one embodiment of the present invention. FIG. 2 is a cross-sectional explanatory view of a semiconductor device for explaining a conventional manufacturing method of a semiconductor device, and FIG. 2(a) shows a state in which upper layer wiring is formed, and FIG.
) shows the state in which SOG coating was performed after forming the lower layer wiring. 12c... Dummy pattern, 14... Lower layer wiring, 16... Via ball, 17... Upper layer wiring. Patent applicant Sharp Corporation
Claims (1)
めのヴィアホールとを有する半導体装置の製造方法にお
いて、前記下層配線を平坦化するためのダミーパターン
をあらかじめ形成しておくことを特徴とする半導体装置
の製造方法。(1) A method for manufacturing a semiconductor device having a lower layer wiring, an upper layer wiring, and a via hole for connecting both wirings, characterized in that a dummy pattern for flattening the lower layer wiring is formed in advance. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4259289A JPH02222162A (en) | 1989-02-22 | 1989-02-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4259289A JPH02222162A (en) | 1989-02-22 | 1989-02-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02222162A true JPH02222162A (en) | 1990-09-04 |
Family
ID=12640336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4259289A Pending JPH02222162A (en) | 1989-02-22 | 1989-02-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02222162A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4113775A1 (en) * | 1991-02-05 | 1992-08-13 | Samsung Electronics Co Ltd | INTERLAY CONTACT STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR THEIR PRODUCTION |
| WO1997047035A1 (en) * | 1996-06-05 | 1997-12-11 | Advanced Micro Devices, Inc. | Mask generation technique for producing an integrated circuit with optimal interconnect layout for achieving global planarization |
| JP2001053143A (en) * | 1999-08-09 | 2001-02-23 | Matsushita Electric Ind Co Ltd | Semiconductor device manufacturing method and the semiconductor device |
| JP2013069845A (en) * | 2011-09-22 | 2013-04-18 | Lapis Semiconductor Co Ltd | Semiconductor device and manufacturing method of the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59222944A (en) * | 1983-06-01 | 1984-12-14 | Hitachi Ltd | Multilayer interconnection method |
| JPH01108748A (en) * | 1987-10-21 | 1989-04-26 | Nec Corp | Semiconductor device having multilayer interconnection structure |
-
1989
- 1989-02-22 JP JP4259289A patent/JPH02222162A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59222944A (en) * | 1983-06-01 | 1984-12-14 | Hitachi Ltd | Multilayer interconnection method |
| JPH01108748A (en) * | 1987-10-21 | 1989-04-26 | Nec Corp | Semiconductor device having multilayer interconnection structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4113775A1 (en) * | 1991-02-05 | 1992-08-13 | Samsung Electronics Co Ltd | INTERLAY CONTACT STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR THEIR PRODUCTION |
| WO1997047035A1 (en) * | 1996-06-05 | 1997-12-11 | Advanced Micro Devices, Inc. | Mask generation technique for producing an integrated circuit with optimal interconnect layout for achieving global planarization |
| JP2001053143A (en) * | 1999-08-09 | 2001-02-23 | Matsushita Electric Ind Co Ltd | Semiconductor device manufacturing method and the semiconductor device |
| JP2013069845A (en) * | 2011-09-22 | 2013-04-18 | Lapis Semiconductor Co Ltd | Semiconductor device and manufacturing method of the same |
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