JP3716958B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a plug for connecting stacked wiring layers.
[0002]
[Prior art]
In a semiconductor device, various elements formed on a main surface of a semiconductor substrate such as single crystal silicon are connected by a wiring layer formed on an upper layer through an interlayer insulating film to constitute a predetermined circuit. The number of elements formed in a semiconductor device increases due to the progress of microfabrication technology, and by configuring a more complicated circuit, the number of wirings required to connect the elements and configure a circuit also increases. As the wiring layer, a multi-layer wiring in which a plurality of wiring layers are laminated via an interlayer insulating film is used.
[0003]
The stacked wiring layers or various elements formed on the wiring substrate and the main surface of the semiconductor substrate are connected to each other by plugs formed in through holes provided in the interlayer insulating film.
[0004]
In such a multilayer wiring structure, patterning processing of the wiring layer becomes difficult as the miniaturization progresses. Further, regarding the formation of the insulating film after processing the wiring layer, the insulating film is given priority when filling the fine gap. Since the quality of the film deteriorates or the planarization of the insulating film becomes complicated, a trench for the wiring layer is provided in the insulating film, and the multilayer is formed by a buried damascene method in which the groove is filled with metal. The wiring layer structure has attracted attention.
[0005]
In addition, copper is attracting attention as a wiring material for reducing the resistance of the wiring. However, when copper is used as the wiring material, it is difficult to etch, and a barrier film that prevents diffusion of copper into silicon oxide. However, the formation of wiring by the damascene method is suitable as a method for solving these problems. For example, damascene wiring formation is described in pages 248 to 251 of “ULSI Process Technology” published by Baifukan, or pages 212 to 217 of the December 1997 issue of Nikkei Microdevices.
[0006]
[Problems to be solved by the invention]
In multilayer wiring, when connecting wiring layers that are not adjacent to each other vertically, an intermediate wiring layer for connection is provided in the wiring layer located in the middle, and the upper and lower plugs are connected via this intermediate wiring layer. And connected.
[0007]
The connection state of such wiring layers will be described with reference to FIG. 1 or FIG. In the figure, (a) is a plan view, and a cross section along the line aa is shown in (b). For example, in the case of three wiring layers 1, 2, and 3, a plug 4 connected to the wiring layer 1 and a plug connected to the wiring layer 3 in order to connect the lower wiring layer 1 and the upper wiring layer 3. 5 is connected to the intermediate wiring layer 2. Each of the plugs 4 and 5 has been conventionally formed so as not to overlap in the vertical direction by changing the planar position. However, since it is necessary to increase the wiring density, in recent years, as shown in FIG. 3, there is a demand for a wiring structure using through-holes in which the respective plugs 4 and 5 are formed in the same position on the plane in the vertical direction. ing. In such a case, the intermediate wiring layer 3 is required to have the same size as the plugs 4 and 5 in order to increase the wiring density.
[0008]
In addition, when connecting plugs of adjacent layers to each other, in recent years, stacked vias that directly connect plugs have been used. However, in the damascene method, an interlayer insulating film is formed prior to forming a wiring layer. Normally, the plug is connected through the intermediate wiring layer.
[0009]
As a result of such miniaturization, the plug shape is formed into a substantially circular cylindrical shape in the case of a square pattern plug of 0.4 μm × 0.4 μm due to a decrease in the resolution margin of photolithography. The Rukoto.
[0010]
Further, in order to miniaturize the intermediate wiring layer connected to such a plug, a wiring layer having a relatively large wiring layer thickness relative to the wiring layer width, that is, a high aspect ratio is required. In the intermediate wiring layer having a square pattern of 0.4 μm × 0.4 μm (wiring width × wiring length), the cross-sectional shape is also substantially square.
[0011]
However, in the intermediate wiring layer having such a pattern, when copper is used as the wiring material, the step coverage with respect to the groove portion having a high aspect ratio is not sufficient by sputtering, and the reflow embedding technique of the copper film is insufficient.
[0012]
For this reason, there is a problem that the filling of copper, which is a metal material, is not sufficiently performed and disconnection occurs, resulting in poor conduction of the intermediate wiring layer, or voids resulting in high resistance. When the resistance is partially increased in this way, there is a risk of disconnection over time due to heat generated when current flows. As a method for solving these problems, copper film formation by CVD with good step coverage can be considered, but it has not yet reached the practical stage. Further, there is a problem that it is difficult to completely embed a square pattern wiring having a high aspect ratio even by CVD or plating.
[0013]
In addition, when an unacceptable portion in which a through hole for plug formation is displaced from the intermediate wiring layer due to an error in mask alignment at the time of etching, etc., a crevasse-like shape is formed on the side surface of the intermediate wiring layer by overetching of the insulating film. There may be gaps. In such a gap, when performing degassing treatment to remove moisture contained in the silicon oxide film or residual hydrogen, it is difficult to release moisture. Therefore, CVD formation of a conductor such as tungsten by moisture remaining in this portion is difficult. A film failure occurs, and this causes a plug conduction failure such as an increase in resistance or disconnection.
[0014]
An object of the present invention is to provide a technique capable of preventing disconnection or high resistance due to insufficient embedding in an intermediate wiring layer.
[0015]
Another object of the present invention is a technique capable of preventing a plug conduction failure due to a film formation failure of a conductor such as tungsten due to moisture remaining in a crevasse-like gap generated in an insulating film in an extraordinary portion. Is to provide.
The above and other problems and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
[0016]
[Means for solving problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
At least three or more damascene wiring layers stacked via an interlayer insulating film, a first damascene wiring formed in an upper damascene wiring layer, and through the interlayer insulating film and connected to the first wiring A first damascene plug, a second damascene wiring formed in a lower damascene wiring layer, and a second plug penetrating the interlayer insulating film and connected to the second wiring, The first plug and the second plug are formed in the same position on the plane and stacked in the vertical direction and connected via a third damascene wiring formed in an intermediate damascene wiring layer, The planar shape of the third damascene wiring is a rectangle, the length of the short side is equal to the wiring width of the other damascene wiring formed in the intermediate damascene wiring layer, and the length of the long side is the wiring. Larger than the width, the third damascene wiring is The aspect ratio of made is to have grooves, towards the long side direction of the cross section is smaller than the short side cross section.
[0017]
According to the above-described means, it is possible to prevent disconnection or high resistance due to insufficient embedding by widening the intermediate wiring layer.
[0018]
In addition, the widened portion can avoid occurrence of an extraordinary portion and can prevent a poor plug conduction due to a poor film formation of the conductor.
[0019]
Embodiments of the present invention will be described below.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 4 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention.
[0021]
In the semiconductor device of the present embodiment, the main surface of the semiconductor substrate 11 is separated into each element formation region by an element isolation insulating film 12 such as SGI (Shallow Groove Isolation), and the element formation region or the element isolation insulating film 12 is formed. Various elements such as a bipolar transistor 13, an FET 14, and a diffused resistor 15 are formed.
[0022]
The side surface of the gate electrode of the FET 14 is covered with sidewalls, and the salicide process in which the electrode of the bipolar transistor 13, the source region, the drain region, and the gate electrode of the FET 14 are silicided by self-alignment by reacting the upper surface with a refractory metal such as titanium. Has been made.
[0023]
Each element formed on the main surface of the semiconductor substrate 11 is covered with a silicon nitride film 16 for SAC (Self Align Contact), mainly composed of silicon oxide such as a PSG film for gettering with phosphorus, and polished by CMP technology. Then, it is covered with an interlayer insulating film 17 in which the element step is flattened. The connection region of each element or the like is connected to one end of a plug 18 that penetrates the interlayer insulating film 17, and the other end of the plug 18 is connected to the first wiring layer 19 stacked via the interlayer insulating film 17. ing.
[0024]
The plug 18 is constituted by a barrier film on which titanium, titanium nitride, or the like is deposited by sputtering, a tungsten film by CVD, or the like, and the first wiring layer 19 is formed of tungsten because it is mainly used for local wiring. It is connected to the second wiring layer 22 by a plug 21 penetrating the interlayer insulating film 20.
[0025]
The second wiring layer 22 is a copper wiring by the damascene method, and the formation of the wiring layer by the damascene method will be described with reference to FIG. First, after forming the plug 21 penetrating the interlayer insulating film 20a, the interlayer insulating film 20b is further deposited, and then a resist mask 23 having a pattern excluding the wiring formation region is formed, and then dry etching using the resist mask 23 is performed. A trench reaching the plug 21 is formed in the wiring formation region, and then a barrier film 22a and a copper film 22b on which titanium nitride is deposited are sequentially deposited by sputtering, heat treatment is performed, the copper film 22b is reflowed, and then by CMP. Excess wiring material is polished and removed to form a wiring layer 22 in the groove.
[0026]
Similarly, the third interlayer insulating film 24, plug 25, wiring layer 26, fourth interlayer insulating film 27, plug 28, wiring layer 29, fifth interlayer insulating film 30, plug 31, wiring layer An interlayer insulating film 33, a plug 34, a wiring layer 35, and a seventh interlayer insulating film 36, a plug 37, and a wiring layer 38 are formed. In the sixth and seventh wiring layers 35 and 38, the resistance may be lowered by increasing the wiring cross-sectional area, and the wiring layers 35 and 38 may be formed by sputtering using aluminum.
[0027]
Next, the connection state of the wiring layers according to the present embodiment will be described using the wiring layers 26, 29, and 32 as an example. 6, FIG. 7, and FIG. 8 are diagrams showing their connection state. In FIG. 6, (a) is a plan view, and (b) represents a cross section along the line aa.
[0028]
First, in the example shown in FIG. 6, in order to connect the lower wiring layer 26 and the upper wiring layer 32, the plug 28 connected to the wiring layer 26 and the plug 31 connected to the wiring layer 32 are connected to the intermediate wiring layer 29. Connected by. Each of the plugs 28 and 31 has a wiring structure with through-holes formed in the same position on the plane and stacked in the vertical direction, and the intermediate wiring layer 29 is substantially oversized with respect to the plugs 28 and 31. Widened in a square shape.
[0029]
Further, in the example shown in FIG. 7, each plug 28, 31 has a wiring structure with through-through holes formed in the same position on the plane and stacked in the vertical direction, and the intermediate wiring layer 29 has the plug 28, 31 is widened in one direction of the wiring length direction. In the example shown in FIG. 8, each plug 28, 31 has a wiring structure with through-holes formed in the same position on the plane and stacked vertically, and the intermediate wiring layer 29 is connected to the plugs 28, 31. On the other hand, it is widened in two directions in the wiring length direction.
[0030]
By such widening of the intermediate wiring layer 29, it is possible to prevent disconnection or high resistance of the intermediate wiring layer 29 due to insufficient embedding of the copper film. Further, the widened portion avoids the occurrence of an extraordinary portion in which the through hole is displaced from the intermediate wiring layer 29 due to an etching mask alignment error or the like when forming the through hole for forming the plug 31. Therefore, it is possible to prevent the conduction failure of the plug 31 due to the film formation failure.
[0031]
In the above-described example, the intermediate wiring layer 29 is widened in the wiring length direction. Similarly, the intermediate wiring layer 29 is widened in the wiring width direction or in both the wiring length direction and the wiring width direction. It may be done in the direction.
[0032]
Note that such widening is performed within the range of the opposing length limitation considering the parasitic capacitance between the wiring layers in the same layer or the processing limit of the wiring layer, etc. This opposing length limitation is the use of the wiring layer or the length of the wiring layer, etc. Can be set for each.
[0033]
Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.
[0034]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, there is an effect that the conductive film is sufficiently filled into the fine pattern by widening the intermediate wiring layer.
(2) According to the present invention, the effect (1) has an effect of preventing disconnection due to poor filling.
(3) According to the present invention, the effect (1) has an effect of preventing generation of voids due to poor filling.
(4) According to the present invention, due to the effects (2) and (3), there is an effect that a poor conduction of the intermediate wiring layer can be prevented.
(5) According to the present invention, by widening the intermediate wiring layer, it is possible to prevent the occurrence of an extraordinary portion due to a mask alignment error or the like.
(6) According to the present invention, the effect (5) has an effect of preventing the formation of a crevasse-like gap on the side surface of the intermediate wiring layer.
(7) According to the present invention, due to the effect (6), there is an effect that it is possible to prevent a CVD film formation defect of a conductor such as tungsten due to residual moisture or the like.
(8) According to the present invention, due to the effect (7), it is possible to prevent occurrence of defective plug conduction.
[Brief description of the drawings]
1A and 1B are a plan view and a cross-sectional view showing a connection state of wiring layers of a conventional semiconductor device.
2A and 2B are a plan view and a cross-sectional view showing a connection state of wiring layers of a conventional semiconductor device.
3A and 3B are a plan view and a cross-sectional view showing a connection state of wiring layers of a conventional semiconductor device.
FIG. 4 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a longitudinal sectional view showing wiring layer formation by a damascene method.
6A and 6B are a plan view and a cross-sectional view showing a connection state of wiring layers in a semiconductor device of the present invention.
7A and 7B are a plan view and a cross-sectional view showing a connection state of a wiring layer of a semiconductor device of the present invention.
8A and 8B are a plan view and a cross-sectional view showing a connection state of a wiring layer of a semiconductor device of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 2, 3 ... Wiring layer, 4, 5 ... Plug, 11 ... Semiconductor substrate, 12 ... Inter-element isolation insulating film, 13 ... Bipolar transistor, 14 ... FET, 15 ... Diffusion resistance, 16 ... Silicon nitride film, 17, 2024, 27, 30, 33, 36 ... interlayer insulating film, 18, 21, 25, 28, 31, 34, 37 ... plug, 19, 22, 26, 29, 32, 35, 38 ... wiring layer, 23 ... resist mask.

Claims (4)

At least three or more damascene wiring layers stacked via an interlayer insulating film ;
A first damascene wiring formed in an upper damascene wiring layer;
A first plug passing through the interlayer insulating film and connected to the first wiring;
A second damascene wiring formed in a lower damascene wiring layer;
A second plug penetrating the interlayer insulating film and connected to the second wiring;
The first plug and the second plug are formed in the same position on the plane and stacked in the vertical direction and connected via a third damascene wiring formed in an intermediate damascene wiring layer,
The planar shape of the third damascene wiring is a rectangle, the length of the short side is equal to the wiring width of the other damascene wiring formed in the intermediate damascene wiring layer, and the length of the long side is the wiring. Larger than the width,
The aspect ratio of the groove in which the third damascene wiring is formed is such that the cross section in the long side direction is smaller than the cross section in the short side direction . The semiconductor device according to claim 1, wherein the first plug and the second plug are connected to the end of the rectangle . The semiconductor device according to claim 1, wherein the first plug and the second plug are connected to a central portion of the rectangle . Said third damascene wiring, one of claims 1 to 3, characterized in that it is formed at the other damascene adjacent formed in the middle of the Damascene wiring line and the opposing length within limits The semiconductor device according to one item.

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