CN100440473C - 半导体集成电路器件的制造方法 - Google Patents
半导体集成电路器件的制造方法 Download PDFInfo
- Publication number
- CN100440473C CN100440473C CNB2004100970381A CN200410097038A CN100440473C CN 100440473 C CN100440473 C CN 100440473C CN B2004100970381 A CNB2004100970381 A CN B2004100970381A CN 200410097038 A CN200410097038 A CN 200410097038A CN 100440473 C CN100440473 C CN 100440473C
- Authority
- CN
- China
- Prior art keywords
- test
- semiconductor device
- test board
- thermostat
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 229
- 238000000034 method Methods 0.000 title claims description 50
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000012360 testing method Methods 0.000 claims abstract description 608
- 238000001816 cooling Methods 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims description 8
- 238000007789 sealing Methods 0.000 claims description 4
- 230000015654 memory Effects 0.000 abstract description 119
- 238000012545 processing Methods 0.000 abstract description 27
- 230000032683 aging Effects 0.000 description 82
- 238000010923 batch production Methods 0.000 description 21
- 230000006870 function Effects 0.000 description 20
- 238000010586 diagram Methods 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 13
- 239000000758 substrate Substances 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 8
- 230000006641 stabilisation Effects 0.000 description 8
- 238000011105 stabilization Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000003860 storage Methods 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 102100025677 Alkaline phosphatase, germ cell type Human genes 0.000 description 1
- 235000017060 Arachis glabrata Nutrition 0.000 description 1
- 241001553178 Arachis glabrata Species 0.000 description 1
- 235000010777 Arachis hypogaea Nutrition 0.000 description 1
- 235000018262 Arachis monticola Nutrition 0.000 description 1
- 101000574440 Homo sapiens Alkaline phosphatase, germ cell type Proteins 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000002431 foraging effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 210000003141 lower extremity Anatomy 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000020232 peanut Nutrition 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000000153 supplemental effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2868—Complete testing stations; systems; procedures; software aspects
- G01R31/287—Procedures; Software aspects
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56016—Apparatus features
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5602—Interface to device under test
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
Claims (9)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP425616/2003 | 2003-12-22 | ||
JP2003425616A JP2005181222A (ja) | 2003-12-22 | 2003-12-22 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1638079A CN1638079A (zh) | 2005-07-13 |
CN100440473C true CN100440473C (zh) | 2008-12-03 |
Family
ID=34736236
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100970381A Expired - Fee Related CN100440473C (zh) | 2003-12-22 | 2004-12-21 | 半导体集成电路器件的制造方法 |
Country Status (4)
Country | Link |
---|---|
US (3) | US7306957B2 (zh) |
JP (1) | JP2005181222A (zh) |
CN (1) | CN100440473C (zh) |
TW (1) | TW200529337A (zh) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4445299B2 (ja) * | 2004-03-18 | 2010-04-07 | 富士通株式会社 | 不揮発性メモリ評価方法 |
US7301242B2 (en) | 2004-11-04 | 2007-11-27 | Tabula, Inc. | Programmable system in package |
US8201124B1 (en) | 2005-03-15 | 2012-06-12 | Tabula, Inc. | System in package and method of creating system in package |
US7139630B1 (en) * | 2005-04-28 | 2006-11-21 | International Business Machines Corporation | Allocating manufactured devices according to customer specifications |
US20070279079A1 (en) * | 2006-05-31 | 2007-12-06 | Jianxiang Chang | Multiple chip package test program and programming architecture |
US8232176B2 (en) * | 2006-06-22 | 2012-07-31 | Applied Materials, Inc. | Dielectric deposition and etch back processes for bottom up gapfill |
US7901955B2 (en) * | 2007-06-25 | 2011-03-08 | Spansion Llc | Method of constructing a stacked-die semiconductor structure |
TWI365524B (en) * | 2007-10-04 | 2012-06-01 | Unimicron Technology Corp | Stackable semiconductor device and fabrication method thereof |
JP5061860B2 (ja) * | 2007-11-19 | 2012-10-31 | 横河電機株式会社 | 実装回路及び半導体試験装置 |
KR101384358B1 (ko) | 2008-03-18 | 2014-04-21 | 삼성전자주식회사 | 반도체 모듈 핸들링 시스템 |
WO2009147722A1 (ja) * | 2008-06-02 | 2009-12-10 | 株式会社アドバンテスト | 試験用ウエハ、試験システム、および、半導体ウエハ |
US20100123477A1 (en) * | 2008-11-20 | 2010-05-20 | Shih-Wei Sun | Programmable array module |
CN101873679B (zh) * | 2009-04-23 | 2016-07-06 | 瑞昱半导体股份有限公司 | 具有省电功能的网络系统的装置及相关方法 |
CN101901633A (zh) * | 2009-05-27 | 2010-12-01 | 深圳芯邦科技股份有限公司 | 一种移动存储设备生产方案 |
KR20110099556A (ko) * | 2010-03-02 | 2011-09-08 | 삼성전자주식회사 | 반도체 패키지 테스트장치 |
KR101734364B1 (ko) * | 2010-12-13 | 2017-05-12 | 삼성전자 주식회사 | 반도체 장치 동시 연속 테스트 방법 및 테스트 장비 |
KR20120069404A (ko) | 2010-12-20 | 2012-06-28 | 삼성전자주식회사 | 테스터 및 이를 포함하는 테스트 시스템 |
US9224659B2 (en) | 2013-03-14 | 2015-12-29 | Microchip Technology Incorporated | Method and apparatus for semiconductor testing at low temperature |
CN104239177A (zh) * | 2013-06-19 | 2014-12-24 | 鸿富锦精密工业(深圳)有限公司 | 串行接口信号测试治具 |
CN105891703B (zh) * | 2014-12-22 | 2020-06-30 | 恩智浦美国有限公司 | 用于集成电路的非常低电压和偏置的扫描测试的测试电路 |
CN106887255A (zh) * | 2015-12-15 | 2017-06-23 | 西安富成防务科技有限公司 | 一种双口ram测试设备的处理板结构 |
CN108535556B (zh) * | 2017-03-02 | 2021-01-22 | 台达电子工业股份有限公司 | 复合式产品测试系统及其测试方法 |
KR102471500B1 (ko) * | 2018-03-12 | 2022-11-28 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이를 포함하는 테스트 시스템 |
US11169203B1 (en) * | 2018-09-26 | 2021-11-09 | Teradyne, Inc. | Determining a configuration of a test system |
CN111370054B (zh) * | 2018-12-26 | 2024-07-05 | 华为技术有限公司 | 一种存储卡的测试系统 |
CN114424331A (zh) * | 2019-11-15 | 2022-04-29 | 铠侠股份有限公司 | 存储器设备以及控制方法 |
KR102467416B1 (ko) * | 2020-12-24 | 2022-11-16 | 주식회사 엑시콘 | 이종의 피검사 디바이스를 테스트하는 테스트 시스템 |
WO2023032121A1 (ja) * | 2021-09-02 | 2023-03-09 | キオクシア株式会社 | ストレージシステム |
CN116068380B (zh) * | 2023-03-01 | 2023-07-07 | 上海聚跃检测技术有限公司 | 一种芯片封装测试方法及装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0783996A (ja) * | 1993-06-30 | 1995-03-31 | Ando Electric Co Ltd | 加熱ブロックを熱媒体とするバーンインチェンバ |
JPH10239388A (ja) * | 1997-02-28 | 1998-09-11 | Ando Electric Co Ltd | 挿抜装置 |
JPH1123651A (ja) * | 1997-06-30 | 1999-01-29 | Ando Electric Co Ltd | バーンイン試験装置 |
US6225798B1 (en) * | 1997-04-16 | 2001-05-01 | Advantest Corporation | Semiconductor device tester |
US20020073370A1 (en) * | 1998-01-21 | 2002-06-13 | Salman Akram | Testing system for evaluating integrated circuits, a testing system, and a method for testing an integrated circuit |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03206639A (ja) * | 1990-01-08 | 1991-09-10 | Mitsubishi Electric Corp | 半導体検査ハンドリング装置 |
JPH0555328A (ja) | 1991-08-28 | 1993-03-05 | Nippon Steel Corp | 半導体デバイスの信頼性評価試験装置 |
JPH06283657A (ja) | 1993-03-30 | 1994-10-07 | Hitachi Ltd | 半導体装置の製造方法および半導体装置組立モジュールならびに半導体装置用試験装置 |
JP3547471B2 (ja) * | 1994-03-09 | 2004-07-28 | 富士通株式会社 | 誘電体膜の気相成長方法 |
JPH0864921A (ja) * | 1994-05-12 | 1996-03-08 | Texas Instr Inc <Ti> | 表面実装形集積回路構造体 |
BE1008808A3 (nl) * | 1994-10-19 | 1996-08-06 | Imec Inter Uni Micro Electr | Inrichting en werkwijze voor het evalueren van de thermische weerstand van een halfgeleider-component. |
JP2876106B2 (ja) * | 1995-01-31 | 1999-03-31 | タバイエスペック株式会社 | バーンイン用複合体及び複合体使用バーンイン装置 |
US5899987A (en) * | 1995-10-03 | 1999-05-04 | Memco Software Ltd. | Apparatus for and method of providing user exits on an operating system platform |
US5903269A (en) * | 1995-10-10 | 1999-05-11 | Anysoft Ltd. | Apparatus for and method of acquiring processing and routing data contained in a GUI window |
US5990907A (en) * | 1995-12-15 | 1999-11-23 | Colletti; John C. | Automatic font management within an operating system environment |
US6097200A (en) * | 1996-10-07 | 2000-08-01 | Aetrium Incorporated | Modular, semiconductor reliability test system |
US6314470B1 (en) * | 1997-07-25 | 2001-11-06 | Hewlett Packard Company | System and method for asynchronously accessing a graphics system for graphics application evaluation and control |
JPH11248786A (ja) * | 1998-02-26 | 1999-09-17 | Ando Electric Co Ltd | バーンイン試験システム |
US6304881B1 (en) * | 1998-03-03 | 2001-10-16 | Pumatech, Inc. | Remote data access and synchronization |
JP2000040390A (ja) | 1998-07-23 | 2000-02-08 | Ono Sokki Co Ltd | バーンイン装置 |
US6463583B1 (en) * | 1999-04-08 | 2002-10-08 | Novadigm, Inc. | Dynamic injection of execution logic into main dynamic link library function of the original kernel of a windowed operating system |
IL132915A (en) * | 1999-11-14 | 2004-05-12 | Networks Assoc Tech Inc | Method for secure function execution by calling address validation |
TW518733B (en) * | 2000-04-08 | 2003-01-21 | Advanced Semiconductor Eng | Attaching method of heat sink for chip package |
JP4570208B2 (ja) * | 2000-06-13 | 2010-10-27 | 株式会社アドバンテスト | 試験済み電子部品の分類制御方法 |
US20030221313A1 (en) * | 2001-01-26 | 2003-12-04 | Gann Keith D. | Method for making stacked integrated circuits (ICs) using prepackaged parts |
JP2002280414A (ja) * | 2001-03-22 | 2002-09-27 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2003057292A (ja) | 2001-08-17 | 2003-02-26 | Ando Electric Co Ltd | 半導体集積回路試験装置及び試験用ボード並びに半導体集積回路試験方法 |
JP3901570B2 (ja) * | 2002-04-23 | 2007-04-04 | スパンション エルエルシー | 電子冷却素子を利用した半導体装置の低温試験装置 |
US6707142B2 (en) * | 2002-04-24 | 2004-03-16 | Barun Electronics Co., Ltd. | Package stacked semiconductor device having pin linking means |
KR100843737B1 (ko) * | 2002-05-10 | 2008-07-04 | 페어차일드코리아반도체 주식회사 | 솔더 조인트의 신뢰성이 개선된 반도체 패키지 |
JP2005140572A (ja) * | 2003-11-05 | 2005-06-02 | Hitachi High-Tech Electronics Engineering Co Ltd | 半導体装置の試験装置および試験方法 |
-
2003
- 2003-12-22 JP JP2003425616A patent/JP2005181222A/ja active Pending
-
2004
- 2004-11-04 TW TW093133685A patent/TW200529337A/zh not_active IP Right Cessation
- 2004-12-16 US US11/012,225 patent/US7306957B2/en not_active Expired - Fee Related
- 2004-12-21 CN CNB2004100970381A patent/CN100440473C/zh not_active Expired - Fee Related
-
2007
- 2007-11-07 US US11/936,358 patent/US7422914B2/en not_active Expired - Fee Related
-
2008
- 2008-08-01 US US12/184,563 patent/US20080293167A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0783996A (ja) * | 1993-06-30 | 1995-03-31 | Ando Electric Co Ltd | 加熱ブロックを熱媒体とするバーンインチェンバ |
JPH10239388A (ja) * | 1997-02-28 | 1998-09-11 | Ando Electric Co Ltd | 挿抜装置 |
US6225798B1 (en) * | 1997-04-16 | 2001-05-01 | Advantest Corporation | Semiconductor device tester |
JPH1123651A (ja) * | 1997-06-30 | 1999-01-29 | Ando Electric Co Ltd | バーンイン試験装置 |
US20020073370A1 (en) * | 1998-01-21 | 2002-06-13 | Salman Akram | Testing system for evaluating integrated circuits, a testing system, and a method for testing an integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
TW200529337A (en) | 2005-09-01 |
CN1638079A (zh) | 2005-07-13 |
US20080070330A1 (en) | 2008-03-20 |
US7422914B2 (en) | 2008-09-09 |
US20080293167A1 (en) | 2008-11-27 |
JP2005181222A (ja) | 2005-07-07 |
US7306957B2 (en) | 2007-12-11 |
TWI371068B (zh) | 2012-08-21 |
US20050153465A1 (en) | 2005-07-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100440473C (zh) | 半导体集成电路器件的制造方法 | |
US7659738B2 (en) | Test sockets having peltier elements, test equipment including the same and methods of testing semiconductor packages using the same | |
TWI320958B (en) | Testing of a semiconductor device | |
KR101411565B1 (ko) | 싱귤레이션된 다이를 테스트하는 장치 및 방법 | |
KR100524632B1 (ko) | 테스트-번인 장치, 그 테스트-번인 장치를 이용한 인라인시스템 및 그 시스템을 이용한 테스트 방법 | |
US6871307B2 (en) | Efficient test structure for non-volatile memory and other semiconductor integrated circuits | |
US7394268B2 (en) | Carrier for test, burn-in, and first level packaging | |
JPH0922929A (ja) | Bgaパッケージ半導体素子及びその検査方法 | |
US7906982B1 (en) | Interface apparatus and methods of testing integrated circuits using the same | |
US20080237592A1 (en) | Semiconductor device and its test method | |
US20150198658A1 (en) | Method and equipment for testing semiconductor apparatuses simultaneously and continuously | |
JP2003197697A (ja) | 半導体装置の製造方法 | |
US6777924B2 (en) | Method and magazine device for testing semiconductor devices | |
KR100687687B1 (ko) | 멀티칩 모듈 패키징 방법 | |
CN111435145A (zh) | 一种针对智能卡芯片的测试系统 | |
JP2012247435A (ja) | 半導体装置のテスト方法 | |
JP5167312B2 (ja) | 半導体装置のテスト方法 | |
KR0141453B1 (ko) | 노운 굳 다이의 제조장치와 제조방법 | |
JP2011211113A (ja) | 半導体装置の製造方法 | |
JPH09152449A (ja) | 露出された共通パッドを有するマルチチップパッケージ | |
JP2007127660A (ja) | 半導体装置の製造方法 | |
TW562929B (en) | Wafer level board/card assembly method and equipment thereof | |
CN110164503A (zh) | 一种半导体组件测试夹具、测试系统及测试方法 | |
JP2001281293A (ja) | バーンイン装置 | |
KR19980021183A (ko) | 노운 굿 다이의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: RENESAS ELECTRONICS Free format text: FORMER OWNER: RENESAS TECHNOLOGY CORP. Effective date: 20100919 |
|
C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: TOKYO, JAPAN TO: KANAGAWA PREFECTURE, JAPAN |
|
TR01 | Transfer of patent right |
Effective date of registration: 20100919 Address after: Kanagawa Patentee after: Renesas Electronics Corporation Address before: Tokyo, Japan, Japan Patentee before: Renesas Technology Corp. |
|
CP02 | Change in the address of a patent holder | ||
CP02 | Change in the address of a patent holder |
Address after: Tokyo, Japan, Japan Patentee after: Renesas Electronics Corporation Address before: Kanagawa Patentee before: Renesas Electronics Corporation |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081203 Termination date: 20201221 |
|
CF01 | Termination of patent right due to non-payment of annual fee |