JP2005181222A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- G01—MEASURING; TESTING
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- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2868—Complete testing stations; systems; procedures; software aspects
- G01R31/287—Procedures; Software aspects
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56016—Apparatus features
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5602—Interface to device under test
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
【解決手段】テストバーンイン装置において、24枚のテストボードは順次時間差を持って処理されることになり、各々のテストボードは1枚単位で循環する。この場合、半導体装置を詰め終わったテストボードからテストスタート、テスト終了したテストボードから半導体装置を払い出すという枚葉処理のシーケンスによってメモリテストが実行される。
【選択図】 図12
Description
1.以下の工程を含む半導体装置の製造方法:
(a)複数の半導体装置が搭載された複数のテストボードがテスト装置の収納槽内に収容されて前記複数の半導体装置のテストが行われている状態で、テストが終了した1枚の前記テストボードを取り出す工程;
(b)取り出された前記テストボードから、前記複数の半導体装置をはずす工程;
(c)前記半導体装置をはずした前記テストボードに、テストする複数の半導体装置を搭載する工程;
(d)前記複数の半導体装置が搭載された前記テストボードを前記収納槽に収容し、前記導入したテストボードをテストする工程。
2 マザーボード
3 スロット
4 テストボード
4a ボードエッジコネクタ
4b 測定用ソケット
4c 周辺回路
5 バックボード(テスト制御部)
5a CPUモジュール
5b FPGA
6 電源ボード(電源部)
7 固定DC電源
8 ハブ
9 制御端末(テストコントローラ)
10 ハンドラ(テストシステム)
11 ボードラック
12 エレベータ
13 ローダ/アンローダ
14 エレベータ
15 バッファトレイ
16 ローダトレイ
17 良品トレイ
18 不良トレイ
19 未検トレイ
20 半導体装置
20a CPU
20b SDRAM
20c フラッシュメモリ
21 プリント配線基板
22〜25 半導体チップ
26,27 半導体チップ
28 プリント配線基板
29 接続用電極
30 バンプ
31 ボンディングワイヤ
32 はんだバンプ
33 封止樹脂
34,35 ダイパッド
36,37 半導体チップ
38 インナリード
39 ボンディングワイヤ
40 封止樹脂
41 アウタリード
42 LANインタフェース
43 SDRAM
44 フラッシュメモリ
45 CPU
46 CFスロット
47 バスインタフェース
48 ドライバ
49 バッファ
50 電源コントロール部
51〜54 電源生成部
AB アドレスバス
DB データバス
Claims (12)
- 以下の工程を含む半導体装置の製造方法:
(a)複数の半導体装置が搭載された複数のテストボードが恒温槽に導入されてテストが行われている状態で、テストが終了した1枚の前記テストボードを取り出す工程;
(b)取り出された前記テストボードから、前記複数の半導体装置をはずす工程;
(c)前記半導体装置をはずした前記テストボードに、テストする複数の半導体装置を搭載する工程;
(d)前記複数の半導体装置が搭載された前記テストボードを前記恒温槽に導入し、前記導入したテストボードをテストする工程。 - 請求項1記載の半導体装置の製造方法において、
前記複数のテストボードが前記恒温槽に導入されて前記複数の半導体装置のテストが行われている状態で、新たにテストされる複数の半導体装置を前記テストボードに搭載する工程と、
テストが終了した前記テストボードが前記恒温槽から取り出された際に、前記新たにテストされる半導体装置が搭載されたテストボードを前記恒温槽に導入し、テストする工程とを含む半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記恒温槽は、第1のスロットと第2のスロットとの温度が異なる半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
第1の温度が設定された前記恒温槽において前記テストボードに搭載された半導体装置のテストを行う工程と、
前記第1の温度によるテストが終了した後、第2の温度が設定された前記恒温槽において前記テストボードに搭載された半導体装置のテストを行う工程とを含む半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
前記恒温槽を第1の温度に設定し、前記半導体装置をテストする工程と、
前記第1の温度によるテストが終了すると、前記恒温槽を第2の温度に設定し、前記半導体装置をテストする工程とを含む半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法において、
第1の温度による前記半導体装置のテストと第2の温度による前記半導体装置をテストとを異なる恒温槽により行う半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
ハンドラにより、前記テストボードに半導体装置を搭載する工程と、
前記半導体装置を搭載したテストボードを1枚毎に前記検査装置の恒温槽に前記ハンドラにより供給する工程と、
テストの終了後に、テスト結果に基づいて冷却された前記半導体装置を前記ハンドラにより分類、収納する工程とを含む半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記ハンドラによって前記テストボードに搭載される半導体装置は、第1のテストボードと第2のテストボードで種類が異なる半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記半導体装置は、ロジックや半導体メモリなどの複数の半導体チップを1つのパッケージに収納したSiP製品よりなる半導体装置の製造方法。 - 以下の工程を含む半導体装置の製造方法:
ロジック回路装置またはCPU、およびメモリ回路装置を含む複数の半導体チップを1つのパッケージに収納した複数の半導体装置を複数のテストボードに搭載する工程;
前記複数のテストボードを恒温槽に収容した状態で、前記複数の半導体装置の各メモリ回路装置に対してメモリテストを行う工程。 - 以下の工程を含む半導体装置の製造方法:
(a)複数の半導体装置が搭載された複数のテストボードが恒温槽に導入されてテストが行われている状態で、テストが終了した1枚の前記テストボードを取り出す工程;
(b)取り出された前記テストボードから、前記複数の半導体装置をはずす工程;
(c)前記半導体装置をはずした前記テストボードに、テストする複数の半導体装置を搭載する工程;
(d)前記複数の半導体装置が搭載された前記テストボードを前記恒温槽に導入し、前記導入したテストボードをテストする工程とを有し、
前記恒温槽は、第1のスロットと第2のスロットとの温度が異なる半導体装置の製造方法。 - 以下の工程を含む半導体装置の製造方法:
(a)複数の半導体装置が搭載された複数のテストボードが恒温槽に導入されてテストが行われている状態で、テストが終了した1枚の前記テストボードをハンドラにより取り出す工程;
(b)前記ハンドラによって取り出された前記テストボードから、前記複数の半導体装置をはずす工程;
(c)テスト結果に基づいて冷却された前記半導体装置を前記ハンドラにより分類、収納する工程;
(d)前記半導体装置をはずした前記テストボードに、前記ハンドラがテストする複数の半導体装置を搭載する工程;
(e)前記複数の半導体装置が搭載された前記テストボードを前記ハンドラが前記恒温槽に導入し、前記導入したテストボードをテストする工程とを有し、
前記恒温槽は、第1のスロットと第2のスロットとの温度が異なる半導体装置の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003425616A JP2005181222A (ja) | 2003-12-22 | 2003-12-22 | 半導体装置の製造方法 |
TW093133685A TW200529337A (en) | 2003-12-22 | 2004-11-04 | Fabrication method of semiconductor device |
US11/012,225 US7306957B2 (en) | 2003-12-22 | 2004-12-16 | Fabrication method of semiconductor integrated circuit device |
CNB2004100970381A CN100440473C (zh) | 2003-12-22 | 2004-12-21 | 半导体集成电路器件的制造方法 |
US11/936,358 US7422914B2 (en) | 2003-12-22 | 2007-11-07 | Fabrication method of semiconductor integrated circuit device |
US12/184,563 US20080293167A1 (en) | 2003-12-22 | 2008-08-01 | Fabrication method of semiconductor integrated circuit device |
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JP2003425616A JP2005181222A (ja) | 2003-12-22 | 2003-12-22 | 半導体装置の製造方法 |
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JP2006329282A Division JP2007127660A (ja) | 2006-12-06 | 2006-12-06 | 半導体装置の製造方法 |
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JP2005181222A true JP2005181222A (ja) | 2005-07-07 |
JP2005181222A5 JP2005181222A5 (ja) | 2007-02-01 |
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US (3) | US7306957B2 (ja) |
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CN (1) | CN100440473C (ja) |
TW (1) | TW200529337A (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009122073A (ja) * | 2007-11-19 | 2009-06-04 | Yokogawa Electric Corp | 実装回路及び半導体試験装置 |
KR101384358B1 (ko) | 2008-03-18 | 2014-04-21 | 삼성전자주식회사 | 반도체 모듈 핸들링 시스템 |
US9557366B2 (en) | 2010-12-20 | 2017-01-31 | Samsung Electronics Co., Ltd. | Tester to simultaneously test different types of semiconductor devices and test system including the same |
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JPWO2021095251A1 (ja) * | 2019-11-15 | 2021-05-20 | ||
WO2021095251A1 (ja) * | 2019-11-15 | 2021-05-20 | キオクシア株式会社 | ストレージデバイスおよび制御方法 |
JP7293389B2 (ja) | 2019-11-15 | 2023-06-19 | キオクシア株式会社 | ストレージデバイスおよび制御方法 |
KR20220091848A (ko) * | 2020-12-24 | 2022-07-01 | 주식회사 엑시콘 | 이종의 피검사 디바이스를 테스트하는 테스트 시스템 |
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Also Published As
Publication number | Publication date |
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US7422914B2 (en) | 2008-09-09 |
US20050153465A1 (en) | 2005-07-14 |
US7306957B2 (en) | 2007-12-11 |
US20080293167A1 (en) | 2008-11-27 |
US20080070330A1 (en) | 2008-03-20 |
TWI371068B (ja) | 2012-08-21 |
CN100440473C (zh) | 2008-12-03 |
TW200529337A (en) | 2005-09-01 |
CN1638079A (zh) | 2005-07-13 |
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