CN100336180C - 干蚀刻方法 - Google Patents

干蚀刻方法 Download PDF

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Publication number
CN100336180C
CN100336180C CNB028124936A CN02812493A CN100336180C CN 100336180 C CN100336180 C CN 100336180C CN B028124936 A CNB028124936 A CN B028124936A CN 02812493 A CN02812493 A CN 02812493A CN 100336180 C CN100336180 C CN 100336180C
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CN
China
Prior art keywords
etching
groove
gas
electric power
dry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB028124936A
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English (en)
Chinese (zh)
Other versions
CN1518759A (zh
Inventor
饭嶋悦夫
高明辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
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Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001189579A external-priority patent/JP4854874B2/ja
Priority claimed from JP2002012206A external-priority patent/JP4516713B2/ja
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of CN1518759A publication Critical patent/CN1518759A/zh
Application granted granted Critical
Publication of CN100336180C publication Critical patent/CN100336180C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
CNB028124936A 2001-06-22 2002-06-07 干蚀刻方法 Expired - Fee Related CN100336180C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP189579/2001 2001-06-22
JP2001189579A JP4854874B2 (ja) 2001-06-22 2001-06-22 ドライエッチング方法
JP12206/2002 2002-01-21
JP2002012206A JP4516713B2 (ja) 2002-01-21 2002-01-21 エッチング方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CNB2006100826286A Division CN100403494C (zh) 2001-06-22 2002-06-07 干蚀刻方法

Publications (2)

Publication Number Publication Date
CN1518759A CN1518759A (zh) 2004-08-04
CN100336180C true CN100336180C (zh) 2007-09-05

Family

ID=26617413

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028124936A Expired - Fee Related CN100336180C (zh) 2001-06-22 2002-06-07 干蚀刻方法

Country Status (5)

Country Link
US (2) US7183217B2 (enExample)
KR (2) KR100702723B1 (enExample)
CN (1) CN100336180C (enExample)
TW (1) TWI364789B (enExample)
WO (1) WO2003001577A1 (enExample)

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JP2007184356A (ja) * 2006-01-05 2007-07-19 Oki Electric Ind Co Ltd エッチング方法
US20070218681A1 (en) * 2006-03-16 2007-09-20 Tokyo Electron Limited Plasma etching method and computer-readable storage medium
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WO2009012122A1 (en) * 2007-07-13 2009-01-22 Marvell World Trade Ltd. Method for shallow trench isolation
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CN102456610B (zh) * 2010-10-20 2013-11-06 中国科学院微电子研究所 控制背孔剖面形状的方法
CN104217985A (zh) * 2013-05-31 2014-12-17 中芯国际集成电路制造(上海)有限公司 半导体器件和浅沟槽的制作方法
US20150371889A1 (en) * 2014-06-20 2015-12-24 Applied Materials, Inc. Methods for shallow trench isolation formation in a silicon germanium layer
KR200488004Y1 (ko) 2014-07-28 2018-12-03 오종만 피자 고정구에 착탈되는 캐릭터
CN106298636B (zh) * 2015-05-22 2019-05-14 中芯国际集成电路制造(上海)有限公司 一种超低k介质材料刻蚀深度的控制方法
KR20170023654A (ko) * 2015-08-24 2017-03-06 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
US9966312B2 (en) 2015-08-25 2018-05-08 Tokyo Electron Limited Method for etching a silicon-containing substrate
US9793164B2 (en) * 2015-11-12 2017-10-17 Qualcomm Incorporated Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices
JP6556046B2 (ja) * 2015-12-17 2019-08-07 東京エレクトロン株式会社 プラズマ処理方法およびプラズマ処理装置
JP6643950B2 (ja) * 2016-05-23 2020-02-12 東京エレクトロン株式会社 プラズマ処理方法
JP6524562B2 (ja) * 2017-02-23 2019-06-05 パナソニックＩｐマネジメント株式会社 素子チップおよびその製造方法
US11877434B2 (en) * 2020-07-09 2024-01-16 Micron Technology, Inc. Microelectronic devices having features with a fin portion of different sidewall slope than a lower portion, and related methods and electronic systems

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JPH0214548A (ja) * 1988-07-01 1990-01-18 Hitachi Ltd 半導体装置およびその製造方法
US5880004A (en) * 1997-06-10 1999-03-09 Winbond Electronics Corp. Trench isolation process
CN1218279A (zh) * 1997-11-13 1999-06-02 日本电气株式会社 从氧化硅膜选择蚀刻氮化硅膜的方法
JP2000294626A (ja) * 1999-04-07 2000-10-20 Sony Corp 半導体装置の製造方法

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US4855017A (en) * 1985-05-03 1989-08-08 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
US4729815A (en) * 1986-07-21 1988-03-08 Motorola, Inc. Multiple step trench etching process
US5258332A (en) * 1987-08-28 1993-11-02 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices including rounding of corner portions by etching
US5316616A (en) * 1988-02-09 1994-05-31 Fujitsu Limited Dry etching with hydrogen bromide or bromine
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US6225187B1 (en) * 1999-02-12 2001-05-01 Nanya Technology Corporation Method for STI-top rounding control
DE19910886B4 (de) * 1999-03-11 2008-08-14 Infineon Technologies Ag Verfahren zur Herstellung einer flachen Grabenisolation für elektrisch aktive Bauelemente
US6432832B1 (en) * 1999-06-30 2002-08-13 Lam Research Corporation Method of improving the profile angle between narrow and wide features
US6235643B1 (en) * 1999-08-10 2001-05-22 Applied Materials, Inc. Method for etching a trench having rounded top and bottom corners in a silicon substrate
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Publication number Priority date Publication date Assignee Title
JPS57131374A (en) * 1981-02-09 1982-08-14 Nippon Telegr & Teleph Corp <Ntt> Plasma etching device
JPH0214548A (ja) * 1988-07-01 1990-01-18 Hitachi Ltd 半導体装置およびその製造方法
US5880004A (en) * 1997-06-10 1999-03-09 Winbond Electronics Corp. Trench isolation process
CN1218279A (zh) * 1997-11-13 1999-06-02 日本电气株式会社 从氧化硅膜选择蚀刻氮化硅膜的方法
JP2000294626A (ja) * 1999-04-07 2000-10-20 Sony Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US7531460B2 (en) 2009-05-12
US20060172546A1 (en) 2006-08-03
CN1518759A (zh) 2004-08-04
KR100702723B1 (ko) 2007-04-03
KR20040021613A (ko) 2004-03-10
US20040171254A1 (en) 2004-09-02
WO2003001577A1 (fr) 2003-01-03
TWI364789B (enExample) 2012-05-21
KR20060028660A (ko) 2006-03-30
KR100595065B1 (ko) 2006-06-30
US7183217B2 (en) 2007-02-27

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