TWI364789B - - Google Patents

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Publication number
TWI364789B
TWI364789B TW091112669A TW91112669A TWI364789B TW I364789 B TWI364789 B TW I364789B TW 091112669 A TW091112669 A TW 091112669A TW 91112669 A TW91112669 A TW 91112669A TW I364789 B TWI364789 B TW I364789B
Authority
TW
Taiwan
Prior art keywords
groove
gas
dry etching
plasma treatment
etching method
Prior art date
Application number
TW091112669A
Other languages
English (en)
Chinese (zh)
Inventor
Akiteru Koh
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001189579A external-priority patent/JP4854874B2/ja
Priority claimed from JP2002012206A external-priority patent/JP4516713B2/ja
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Application granted granted Critical
Publication of TWI364789B publication Critical patent/TWI364789B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
TW091112669A 2001-06-22 2002-06-11 TWI364789B (enExample)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001189579A JP4854874B2 (ja) 2001-06-22 2001-06-22 ドライエッチング方法
JP2002012206A JP4516713B2 (ja) 2002-01-21 2002-01-21 エッチング方法

Publications (1)

Publication Number Publication Date
TWI364789B true TWI364789B (enExample) 2012-05-21

Family

ID=26617413

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091112669A TWI364789B (enExample) 2001-06-22 2002-06-11

Country Status (5)

Country Link
US (2) US7183217B2 (enExample)
KR (2) KR100702723B1 (enExample)
CN (1) CN100336180C (enExample)
TW (1) TWI364789B (enExample)
WO (1) WO2003001577A1 (enExample)

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US7531461B2 (en) * 2005-09-14 2009-05-12 Tokyo Electron Limited Process and system for etching doped silicon using SF6-based chemistry
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CN104217985A (zh) * 2013-05-31 2014-12-17 中芯国际集成电路制造(上海)有限公司 半导体器件和浅沟槽的制作方法
US20150371889A1 (en) * 2014-06-20 2015-12-24 Applied Materials, Inc. Methods for shallow trench isolation formation in a silicon germanium layer
KR200488004Y1 (ko) 2014-07-28 2018-12-03 오종만 피자 고정구에 착탈되는 캐릭터
CN106298636B (zh) * 2015-05-22 2019-05-14 中芯国际集成电路制造(上海)有限公司 一种超低k介质材料刻蚀深度的控制方法
KR20170023654A (ko) * 2015-08-24 2017-03-06 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
US9966312B2 (en) 2015-08-25 2018-05-08 Tokyo Electron Limited Method for etching a silicon-containing substrate
US9793164B2 (en) * 2015-11-12 2017-10-17 Qualcomm Incorporated Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices
JP6556046B2 (ja) * 2015-12-17 2019-08-07 東京エレクトロン株式会社 プラズマ処理方法およびプラズマ処理装置
JP6643950B2 (ja) * 2016-05-23 2020-02-12 東京エレクトロン株式会社 プラズマ処理方法
JP6524562B2 (ja) * 2017-02-23 2019-06-05 パナソニックＩｐマネジメント株式会社 素子チップおよびその製造方法
US11877434B2 (en) * 2020-07-09 2024-01-16 Micron Technology, Inc. Microelectronic devices having features with a fin portion of different sidewall slope than a lower portion, and related methods and electronic systems

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JPS5812347B2 (ja) 1981-02-09 1983-03-08 日本電信電話株式会社 プラズマエッチング装置
US4855017A (en) * 1985-05-03 1989-08-08 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
US4729815A (en) * 1986-07-21 1988-03-08 Motorola, Inc. Multiple step trench etching process
US5258332A (en) * 1987-08-28 1993-11-02 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices including rounding of corner portions by etching
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TW328162B (en) 1997-07-07 1998-03-11 Winbond Electronics Corp The method for rounding the top corner in shallow trench isolation process
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US6008131A (en) * 1997-12-22 1999-12-28 Taiwan Semiconductor Manufacturing Company Ltd. Bottom rounding in shallow trench etching using a highly isotropic etching step
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Also Published As

Publication number Publication date
CN100336180C (zh) 2007-09-05
US7531460B2 (en) 2009-05-12
US20060172546A1 (en) 2006-08-03
CN1518759A (zh) 2004-08-04
KR100702723B1 (ko) 2007-04-03
KR20040021613A (ko) 2004-03-10
US20040171254A1 (en) 2004-09-02
WO2003001577A1 (fr) 2003-01-03
KR20060028660A (ko) 2006-03-30
KR100595065B1 (ko) 2006-06-30
US7183217B2 (en) 2007-02-27

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees