CA2014285A1 - Procede de fabrication de structures fines; les structures ainsi obtenues - Google Patents

Procede de fabrication de structures fines; les structures ainsi obtenues

Info

Publication number
CA2014285A1
CA2014285A1 CA2014285A CA2014285A CA2014285A1 CA 2014285 A1 CA2014285 A1 CA 2014285A1 CA 2014285 A CA2014285 A CA 2014285A CA 2014285 A CA2014285 A CA 2014285A CA 2014285 A1 CA2014285 A1 CA 2014285A1
Authority
CA
Canada
Prior art keywords
fabrication
irradiation
removal
regions
inventive process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2014285A
Other languages
English (en)
Other versions
CA2014285C (fr
Inventor
Lloyd R. Harriott
Morton B. Panish
Henryk Temkin
Yuh-Lin Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2014285A1 publication Critical patent/CA2014285A1/fr
Application granted granted Critical
Publication of CA2014285C publication Critical patent/CA2014285C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02387Group 13/15 materials
    • H01L21/02392Phosphides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02387Group 13/15 materials
    • H01L21/02395Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02461Phosphides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02463Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • H01L21/02507Alternating layers, e.g. superlattice
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/02543Phosphides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/02546Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • H01L21/30612Etching of AIIIBV compounds
    • H01L21/30621Vapour phase etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/026Deposition thru hole in mask
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/111Narrow masking
CA002014285A 1989-04-10 1990-04-10 Procede de fabrication de structures fines; les structures ainsi obtenues Expired - Fee Related CA2014285C (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US33562689A 1989-04-10 1989-04-10
US335,626 1989-04-10
US07/444,579 US5106764A (en) 1989-04-10 1989-11-30 Device fabrication
US444,579 1989-11-30

Publications (2)

Publication Number Publication Date
CA2014285A1 true CA2014285A1 (fr) 1990-10-10
CA2014285C CA2014285C (fr) 1994-06-07

Family

ID=26989806

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002014285A Expired - Fee Related CA2014285C (fr) 1989-04-10 1990-04-10 Procede de fabrication de structures fines; les structures ainsi obtenues

Country Status (6)

Country Link
US (1) US5106764A (fr)
EP (1) EP0400791B9 (fr)
JP (1) JPH0722142B2 (fr)
KR (1) KR940007443B1 (fr)
CA (1) CA2014285C (fr)
DE (1) DE69033879T2 (fr)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0909985A1 (fr) * 1990-09-26 1999-04-21 Canon Kabushiki Kaisha Méthode de traitement et appareillage photolithographique
US5288657A (en) * 1990-11-01 1994-02-22 At&T Bell Laboratories Device fabrication
JPH0555545A (ja) * 1991-08-27 1993-03-05 Matsushita Electric Ind Co Ltd 量子素子の製造方法
JP2757642B2 (ja) * 1991-12-20 1998-05-25 日本電気株式会社 ドライエッチング方法
US5275687A (en) * 1992-11-20 1994-01-04 At&T Bell Laboratories Process for removing surface contaminants from III-V semiconductors
US5346581A (en) * 1993-04-01 1994-09-13 At&T Bell Laboratories Method of making a compound semiconductor device
US5403753A (en) * 1993-07-15 1995-04-04 Texas Instruments Incorporated Method of forming implant indicators for implant verification
US5580419A (en) * 1994-03-23 1996-12-03 Trw Inc. Process of making semiconductor device using focused ion beam for resistless in situ etching, deposition, and nucleation
US5427648A (en) * 1994-08-15 1995-06-27 The United States Of America As Represented By The Secretary Of The Army Method of forming porous silicon
JP4014676B2 (ja) * 1996-08-13 2007-11-28 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置およびその作製方法
SE511314C2 (sv) * 1997-02-07 1999-09-06 Ericsson Telefon Ab L M Framställning av heterobipolär transistor och laserdiod på samma substrat
US20060051508A1 (en) * 2000-12-28 2006-03-09 Ilan Gavish Focused ion beam deposition
US6638580B2 (en) * 2000-12-29 2003-10-28 Intel Corporation Apparatus and a method for forming an alloy layer over a substrate using an ion beam
US6492261B2 (en) 2000-12-30 2002-12-10 Intel Corporation Focused ion beam metal deposition
US6528427B2 (en) * 2001-03-30 2003-03-04 Lam Research Corporation Methods for reducing contamination of semiconductor substrates
DE10163346A1 (de) * 2001-12-21 2003-07-10 Infineon Technologies Ag Resistloses Lithographieverfahren zur Herstellung feiner Strukturen
EP2144117A1 (fr) * 2008-07-11 2010-01-13 The Provost, Fellows and Scholars of the College of the Holy and Undivided Trinity of Queen Elizabeth near Dublin Procédé et système de fabrication de motifs sur une surface
US8547526B2 (en) * 2009-04-07 2013-10-01 Micron Technology, Inc. Photolithography systems and associated methods of selective die exposure
US8828873B2 (en) * 2010-07-26 2014-09-09 Hamamatsu Photonics K.K. Method for manufacturing semiconductor device
WO2014025683A2 (fr) 2012-08-06 2014-02-13 Skorpios Technologies, Inc. Procédé et système d'intégration monolithique de circuits de surveillance et de commande de signaux rf
US9337933B2 (en) * 2012-10-19 2016-05-10 Skorpios Technologies, Inc. Integrated optical network unit

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5375854A (en) * 1976-12-17 1978-07-05 Nippon Telegr & Teleph Corp <Ntt> Production fo semiconductor device
JPS5567138A (en) * 1978-11-16 1980-05-21 Jeol Ltd Method of exposure to electron beam
US4377437A (en) * 1981-05-22 1983-03-22 Bell Telephone Laboratories, Incorporated Device lithography by selective ion implantation
US4405710A (en) * 1981-06-22 1983-09-20 Cornell Research Foundation, Inc. Ion beam exposure of (g-Gex -Se1-x) inorganic resists
JPS60128622A (ja) * 1983-12-16 1985-07-09 Hitachi Ltd エツチング法
JPS62281349A (ja) * 1986-05-29 1987-12-07 Seiko Instr & Electronics Ltd 金属パタ−ン膜の形成方法及びその装置
JPS62284939A (ja) * 1986-05-31 1987-12-10 Suzuki Motor Co Ltd 内燃機関の始動制御装置
JPS63116443A (ja) * 1986-11-05 1988-05-20 Seiko Instr & Electronics Ltd Fibテスタ
US4853341A (en) * 1987-03-25 1989-08-01 Mitsubishi Denki Kabushiki Kaisha Process for forming electrodes for semiconductor devices using focused ion beams
JP2531690B2 (ja) * 1987-08-03 1996-09-04 株式会社日立製作所 配線薄膜パタ―ンの形成方法及びその装置
US4897361A (en) * 1987-12-14 1990-01-30 American Telephone & Telegraph Company, At&T Bell Laboratories Patterning method in the manufacture of miniaturized devices
GB8806800D0 (en) * 1988-03-22 1988-04-20 British Telecomm Etching methods

Also Published As

Publication number Publication date
KR940007443B1 (ko) 1994-08-18
EP0400791B1 (fr) 2001-12-19
KR900017111A (ko) 1990-11-15
EP0400791A3 (fr) 1991-01-02
CA2014285C (fr) 1994-06-07
EP0400791A2 (fr) 1990-12-05
JPH02295115A (ja) 1990-12-06
DE69033879T2 (de) 2002-08-22
DE69033879D1 (de) 2002-01-31
JPH0722142B2 (ja) 1995-03-08
EP0400791B9 (fr) 2002-11-27
US5106764A (en) 1992-04-21

Similar Documents

Publication Publication Date Title
CA2014285A1 (fr) Procede de fabrication de structures fines; les structures ainsi obtenues
US5405734A (en) Method for correcting a patterned film using an ion beam
EP0418423B1 (fr) Procédé d&#39;attaque anisotrope de silicium
ES465428A1 (es) Procedimiento para el ataque quimico de precision de un ma- terial fotosensible.
EP0358350A3 (fr) Formation d&#39;un motif determiné sur une couche d&#39;un dispositif semi-conducteur
US4362598A (en) Method of patterning a thick resist layer of polymeric plastic
ATE250323T1 (de) Verfahren zur herstellung von leiterplatten mit groben leiterstrukturen und mindestens einem bereich mit feinen leiterstrukturen
US4612274A (en) Electron beam/optical hybrid lithographic resist process in acoustic wave devices
EP0385480A3 (fr) Plaque d&#39;impression à réseau d&#39;ouvertures pour un masque d&#39;ombre et méthode de fabrication de celui-ci
JPS57204033A (en) Formation of fine pattern
JPS57193031A (en) Manufacture of mask substrate for exposing x-ray
JPS57198632A (en) Fine pattern formation
JPS57202735A (en) Manufacture of integrated circuit device
JPS6060725A (ja) パタ−ン形成方法
JPS55140229A (en) Method for formation of fine pattern
JPS57137472A (en) Etching method for polycrystalline silicon
JPS5539646A (en) Ion taper etching
JPS5935319B2 (ja) 金属板、半導体等に精巧なパタ−ンを食刻する方法
JPS6473087A (en) Formation of metallic pattern
JPS6442132A (en) Formation of pattern
JPS6412547A (en) Formation of multilayer interconnection
KR950001407A (ko) 반도체 소자의 레지스트 패턴 형성방법
JPS5636134A (en) Forming method for pattern of semiconductor substrate
JPS56167329A (en) Piling joint setting mark to be used in fine processing exposure technology
SU902072A1 (ru) Способ изготовлени интегральных схем на цилиндрических магнитных доменах

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed