BRPI0911090A2 - design estrutural de arranjo de células de bit de memória magnetoresistiva de acesso aleatório (mram) - Google Patents
design estrutural de arranjo de células de bit de memória magnetoresistiva de acesso aleatório (mram)Info
- Publication number
- BRPI0911090A2 BRPI0911090A2 BRPI0911090A BRPI0911090A BRPI0911090A2 BR PI0911090 A2 BRPI0911090 A2 BR PI0911090A2 BR PI0911090 A BRPI0911090 A BR PI0911090A BR PI0911090 A BRPI0911090 A BR PI0911090A BR PI0911090 A2 BRPI0911090 A2 BR PI0911090A2
- Authority
- BR
- Brazil
- Prior art keywords
- mram
- random access
- cell array
- structural design
- memory bit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/82—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of the magnetic field applied to the device
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/933—Spintronics or quantum computing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/098,017 US8159870B2 (en) | 2008-04-04 | 2008-04-04 | Array structural design of magnetoresistive random access memory (MRAM) bit cells |
| PCT/US2009/037935 WO2009123874A1 (en) | 2008-04-04 | 2009-03-23 | Array structural design of magnetoresistive random access memory (mram) bit cells |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| BRPI0911090A2 true BRPI0911090A2 (pt) | 2018-03-20 |
| BRPI0911090B1 BRPI0911090B1 (pt) | 2019-12-10 |
Family
ID=40940420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BRPI0911090 BRPI0911090B1 (pt) | 2008-04-04 | 2009-03-23 | design estrutural de arranjo de células de bit de memória magnetoresistiva de acesso aleatório (mram) |
Country Status (12)
| Country | Link |
|---|---|
| US (2) | US8159870B2 (pt) |
| EP (1) | EP2269192B1 (pt) |
| JP (1) | JP5575745B2 (pt) |
| KR (1) | KR101227675B1 (pt) |
| CN (2) | CN103956180B (pt) |
| BR (1) | BRPI0911090B1 (pt) |
| CA (1) | CA2719700C (pt) |
| ES (1) | ES2401142T3 (pt) |
| MX (1) | MX2010010909A (pt) |
| RU (1) | RU2464654C2 (pt) |
| TW (1) | TWI409814B (pt) |
| WO (1) | WO2009123874A1 (pt) |
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| JP5088465B2 (ja) * | 2006-07-12 | 2012-12-05 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 不揮発性半導体メモリ |
| US8159870B2 (en) | 2008-04-04 | 2012-04-17 | Qualcomm Incorporated | Array structural design of magnetoresistive random access memory (MRAM) bit cells |
| US8704319B2 (en) * | 2010-12-31 | 2014-04-22 | Samsung Electronics Co., Ltd. | Method and system for providing magnetic layers having insertion layers for use in spin transfer torque memories |
| US8710602B2 (en) * | 2011-12-20 | 2014-04-29 | Samsung Electronics Co., Ltd. | Method and system for providing magnetic junctions having improved characteristics |
| KR101929983B1 (ko) * | 2012-07-18 | 2018-12-17 | 삼성전자주식회사 | 저항성 메모리 셀을 갖는 반도체 메모리 장치 및 그 테스트 방법 |
| KR20160022809A (ko) * | 2013-06-21 | 2016-03-02 | 인텔 코포레이션 | Mtj 스핀 홀 mram 비트-셀 및 어레이 |
| KR102074943B1 (ko) | 2013-08-30 | 2020-02-07 | 삼성전자 주식회사 | 자기 메모리 소자 |
| KR102098244B1 (ko) | 2014-02-04 | 2020-04-07 | 삼성전자 주식회사 | 자기 메모리 소자 |
| KR20170058916A (ko) * | 2014-09-25 | 2017-05-29 | 인텔 코포레이션 | 변형 보조형 스핀 토크 스위칭 스핀 전달 토크 메모리 |
| US20160254318A1 (en) * | 2015-02-27 | 2016-09-01 | Qualcomm Incorporated | MAGNETIC RANDOM ACCESS MEMORY (MRAM) BIT CELLS EMPLOYING SOURCE LINES (SLs) AND/OR BIT LINES (BLs) DISPOSED IN MULTIPLE, STACKED METAL LAYERS TO REDUCE MRAM BIT CELL RESISTANCE |
| US9721634B2 (en) | 2015-04-27 | 2017-08-01 | Qualcomm Incorporated | Decoupling of source line layout from access transistor contact placement in a magnetic tunnel junction (MTJ) memory bit cell to facilitate reduced contact resistance |
| US10043852B2 (en) * | 2015-08-11 | 2018-08-07 | Toshiba Memory Corporation | Magnetoresistive memory device and manufacturing method of the same |
| WO2017052561A1 (en) * | 2015-09-24 | 2017-03-30 | Intel Corporation | Memory with high overlay tolerance |
| WO2017052622A1 (en) * | 2015-09-25 | 2017-03-30 | Intel Corporation | Spin hall effect mram with thin-film selector |
| WO2017052635A1 (en) | 2015-09-25 | 2017-03-30 | Intel Corporation | Psttm device with bottom electrode interface material |
| US10326075B2 (en) | 2015-09-25 | 2019-06-18 | Intel Corporation | PSTTM device with multi-layered filter stack |
| WO2017052586A1 (en) * | 2015-09-25 | 2017-03-30 | Intel Corporation | High density memory array with self-aligned via |
| EP3353825A4 (en) | 2015-09-25 | 2019-05-22 | INTEL Corporation | PSTTM DEVICE WITH FREE MAGNETIC LAYERS COUPLED BY A METAL LAYER HAVING HIGH TEMPERATURE STABILITY |
| KR20170064052A (ko) | 2015-11-30 | 2017-06-09 | 에스케이하이닉스 주식회사 | 스위칭 소자 및 반도체 메모리를 포함하는 전자 장치 |
| US9715916B1 (en) | 2016-03-24 | 2017-07-25 | Intel Corporation | Supply-switched dual cell memory bitcell |
| KR102379706B1 (ko) | 2017-10-25 | 2022-03-28 | 삼성전자주식회사 | 가변 저항 메모리 소자 |
| KR20190122421A (ko) * | 2018-04-20 | 2019-10-30 | 삼성전자주식회사 | 반도체 소자 |
| US11151296B2 (en) * | 2018-05-18 | 2021-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell array circuit |
| US11502188B2 (en) | 2018-06-14 | 2022-11-15 | Intel Corporation | Apparatus and method for boosting signal in magnetoelectric spin orbit logic |
| US11476412B2 (en) | 2018-06-19 | 2022-10-18 | Intel Corporation | Perpendicular exchange bias with antiferromagnet for spin orbit coupling based memory |
| US11616192B2 (en) | 2018-06-29 | 2023-03-28 | Intel Corporation | Magnetic memory devices with a transition metal dopant at an interface of free magnetic layers and methods of fabrication |
| US11444237B2 (en) | 2018-06-29 | 2022-09-13 | Intel Corporation | Spin orbit torque (SOT) memory devices and methods of fabrication |
| JP2020035976A (ja) * | 2018-08-31 | 2020-03-05 | キオクシア株式会社 | 磁気記憶装置 |
| US11594673B2 (en) | 2019-03-27 | 2023-02-28 | Intel Corporation | Two terminal spin orbit memory devices and methods of fabrication |
| US11557629B2 (en) | 2019-03-27 | 2023-01-17 | Intel Corporation | Spin orbit memory devices with reduced magnetic moment and methods of fabrication |
| US11244983B2 (en) | 2019-06-25 | 2022-02-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | MRAM memory cell layout for minimizing bitcell area |
| CN112837723A (zh) * | 2019-11-22 | 2021-05-25 | 上海磁宇信息科技有限公司 | 错层式金属位线走线的磁性随机存储器存储阵列 |
| CN113782077A (zh) * | 2020-06-09 | 2021-12-10 | 上海磁宇信息科技有限公司 | 磁性随机存储器 |
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| JP3527230B2 (ja) * | 2001-06-19 | 2004-05-17 | 松下電器産業株式会社 | 磁気メモリの駆動方法 |
| DE60205569T2 (de) * | 2001-12-21 | 2006-05-18 | Kabushiki Kaisha Toshiba | MRAM mit gestapelten Speicherzellen |
| JP3887272B2 (ja) * | 2001-12-21 | 2007-02-28 | 株式会社東芝 | 磁気ランダムアクセスメモリの読み出し方法 |
| RU2310928C2 (ru) | 2004-10-27 | 2007-11-20 | Самсунг Электроникс Ко., Лтд. | Усовершенствованное многоразрядное магнитное запоминающее устройство с произвольной выборкой и способы его функционирования и производства |
| KR100590563B1 (ko) * | 2004-10-27 | 2006-06-19 | 삼성전자주식회사 | 멀티 비트 자기 메모리 소자와 그 동작 및 제조 방법 |
| JP2007081161A (ja) * | 2005-09-14 | 2007-03-29 | Fujitsu Ltd | 磁気抵抗素子メモリとその製造方法 |
| JP4799218B2 (ja) | 2006-03-03 | 2011-10-26 | 株式会社東芝 | スピン注入書き込み型磁気記憶装置 |
| DE602006013948D1 (de) * | 2006-05-04 | 2010-06-10 | Hitachi Ltd | Magnetspeichervorrichtung |
| US7345912B2 (en) * | 2006-06-01 | 2008-03-18 | Grandis, Inc. | Method and system for providing a magnetic memory structure utilizing spin transfer |
| US7742329B2 (en) * | 2007-03-06 | 2010-06-22 | Qualcomm Incorporated | Word line transistor strength control for read and write in spin transfer torque magnetoresistive random access memory |
| US8004880B2 (en) * | 2007-03-06 | 2011-08-23 | Qualcomm Incorporated | Read disturb reduction circuit for spin transfer torque magnetoresistive random access memory |
| US8159870B2 (en) | 2008-04-04 | 2012-04-17 | Qualcomm Incorporated | Array structural design of magnetoresistive random access memory (MRAM) bit cells |
-
2008
- 2008-04-04 US US12/098,017 patent/US8159870B2/en active Active
-
2009
- 2009-03-23 WO PCT/US2009/037935 patent/WO2009123874A1/en active Application Filing
- 2009-03-23 CN CN201410208924.0A patent/CN103956180B/zh active Active
- 2009-03-23 EP EP09727965A patent/EP2269192B1/en active Active
- 2009-03-23 CN CN200980116359.2A patent/CN102017004B/zh active Active
- 2009-03-23 BR BRPI0911090 patent/BRPI0911090B1/pt active IP Right Grant
- 2009-03-23 KR KR1020107024808A patent/KR101227675B1/ko active IP Right Grant
- 2009-03-23 CA CA2719700A patent/CA2719700C/en active Active
- 2009-03-23 JP JP2011503030A patent/JP5575745B2/ja active Active
- 2009-03-23 MX MX2010010909A patent/MX2010010909A/es active IP Right Grant
- 2009-03-23 ES ES09727965T patent/ES2401142T3/es active Active
- 2009-03-23 RU RU2010145133/08A patent/RU2464654C2/ru active
- 2009-03-25 TW TW098109797A patent/TWI409814B/zh active
-
2012
- 2012-04-17 US US13/448,652 patent/US8625341B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN102017004A (zh) | 2011-04-13 |
| BRPI0911090B1 (pt) | 2019-12-10 |
| US8625341B2 (en) | 2014-01-07 |
| CN103956180B (zh) | 2017-09-12 |
| KR20100125478A (ko) | 2010-11-30 |
| CN102017004B (zh) | 2014-06-25 |
| CA2719700A1 (en) | 2009-10-08 |
| JP5575745B2 (ja) | 2014-08-20 |
| US8159870B2 (en) | 2012-04-17 |
| CA2719700C (en) | 2014-01-28 |
| EP2269192A1 (en) | 2011-01-05 |
| MX2010010909A (es) | 2010-11-04 |
| JP2011519476A (ja) | 2011-07-07 |
| ES2401142T3 (es) | 2013-04-17 |
| RU2010145133A (ru) | 2012-05-20 |
| KR101227675B1 (ko) | 2013-01-29 |
| US20090251949A1 (en) | 2009-10-08 |
| RU2464654C2 (ru) | 2012-10-20 |
| EP2269192B1 (en) | 2013-02-13 |
| WO2009123874A1 (en) | 2009-10-08 |
| US20130100732A1 (en) | 2013-04-25 |
| TW201003652A (en) | 2010-01-16 |
| TWI409814B (zh) | 2013-09-21 |
| CN103956180A (zh) | 2014-07-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| B06F | Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette] | ||
| B06T | Formal requirements before examination [chapter 6.20 patent gazette] | ||
| B15K | Others concerning applications: alteration of classification |
Free format text: A CLASSIFICACAO ANTERIOR ERA: G11C 11/16 Ipc: G11C 11/16 (1968.09), G11C 5/06 (1968.09), H01L 29 |
|
| B09A | Decision: intention to grant [chapter 9.1 patent gazette] | ||
| B16A | Patent or certificate of addition of invention granted [chapter 16.1 patent gazette] |
Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 10/12/2019, OBSERVADAS AS CONDICOES LEGAIS. (CO) 10 (DEZ) ANOS CONTADOS A PARTIR DE 10/12/2019, OBSERVADAS AS CONDICOES LEGAIS |