ATE181790T1 - Basiszelle für bicmos-gatterfeld - Google Patents

Basiszelle für bicmos-gatterfeld

Info

Publication number
ATE181790T1
ATE181790T1 AT91910089T AT91910089T ATE181790T1 AT E181790 T1 ATE181790 T1 AT E181790T1 AT 91910089 T AT91910089 T AT 91910089T AT 91910089 T AT91910089 T AT 91910089T AT E181790 T1 ATE181790 T1 AT E181790T1
Authority
AT
Austria
Prior art keywords
cell
channel
transistor
small
gate field
Prior art date
Application number
AT91910089T
Other languages
English (en)
Inventor
Gamal Abbas El
Original Assignee
Synopsys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synopsys Inc filed Critical Synopsys Inc
Application granted granted Critical
Publication of ATE181790T1 publication Critical patent/ATE181790T1/de

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • H01L27/11896Masterslice integrated circuits using combined field effect/bipolar technology
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • H03K19/1735Controllable logic circuits by wiring, e.g. uncommitted logic arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Luminescent Compositions (AREA)
  • Silicon Polymers (AREA)
  • Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)
  • Semiconductor Integrated Circuits (AREA)
AT91910089T 1990-05-15 1991-05-08 Basiszelle für bicmos-gatterfeld ATE181790T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/524,183 US5055716A (en) 1990-05-15 1990-05-15 Basic cell for bicmos gate array

Publications (1)

Publication Number Publication Date
ATE181790T1 true ATE181790T1 (de) 1999-07-15

Family

ID=24088114

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91910089T ATE181790T1 (de) 1990-05-15 1991-05-08 Basiszelle für bicmos-gatterfeld

Country Status (8)

Country Link
US (2) US5055716A (de)
EP (1) EP0528956B1 (de)
JP (1) JPH06501813A (de)
KR (1) KR100217210B1 (de)
AT (1) ATE181790T1 (de)
AU (1) AU7899191A (de)
DE (1) DE69131399T2 (de)
WO (1) WO1991018447A1 (de)

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JP3030991B2 (ja) * 1991-11-14 2000-04-10 日本電気株式会社 半導体集積回路
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US6324592B1 (en) 1997-02-25 2001-11-27 Keystone Aerospace Apparatus and method for a mobile computer architecture and input/output management system
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JP3152642B2 (ja) 1998-01-29 2001-04-03 三洋電機株式会社 半導体集積回路装置
JP2009177200A (ja) * 1998-05-01 2009-08-06 Sony Corp 半導体記憶装置
JP4501164B2 (ja) * 1998-05-01 2010-07-14 ソニー株式会社 半導体記憶装置
US6974978B1 (en) 1999-03-04 2005-12-13 Intel Corporation Gate array architecture
US6480032B1 (en) 1999-03-04 2002-11-12 Intel Corporation Gate array architecture
US6331733B1 (en) 1999-08-10 2001-12-18 Easic Corporation Semiconductor device
US6245634B1 (en) 1999-10-28 2001-06-12 Easic Corporation Method for design and manufacture of semiconductors
US6236229B1 (en) 1999-05-13 2001-05-22 Easic Corporation Integrated circuits which employ look up tables to provide highly efficient logic cells and logic functionalities
JP3647323B2 (ja) * 1999-07-30 2005-05-11 富士通株式会社 半導体集積回路
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US7299459B1 (en) 2000-01-19 2007-11-20 Sabio Labs, Inc. Parser for signomial and geometric programs
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US6756811B2 (en) 2000-03-10 2004-06-29 Easic Corporation Customizable and programmable cell array
US6617621B1 (en) 2000-06-06 2003-09-09 Virage Logic Corporation Gate array architecture using elevated metal levels for customization
US7065727B2 (en) * 2001-04-25 2006-06-20 Barcelona Design, Inc. Optimal simultaneous design and floorplanning of integrated circuit
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US20030191611A1 (en) * 2002-04-05 2003-10-09 Hershenson Maria Del Mar Behavioral circuit modeling for geometric programming
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US6909330B2 (en) * 2002-04-07 2005-06-21 Barcelona Design, Inc. Automatic phase lock loop design using geometric programming
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US6988258B2 (en) * 2002-12-09 2006-01-17 Altera Corporation Mask-programmable logic device with building block architecture
US6816401B2 (en) * 2003-04-03 2004-11-09 Ami Semiconductor, Inc. Static random access memory (SRAM) without precharge circuitry
US6870398B2 (en) * 2003-04-24 2005-03-22 Ami Semiconductor, Inc. Distributed memory and logic circuits
US7095063B2 (en) * 2003-05-07 2006-08-22 International Business Machines Corporation Multiple supply gate array backfill structure
US7081772B1 (en) * 2004-06-04 2006-07-25 Altera Corporation Optimizing logic in non-reprogrammable logic devices
JP2006041354A (ja) * 2004-07-29 2006-02-09 Renesas Technology Corp 半導体装置及びその製造方法
JP5372578B2 (ja) * 2009-04-09 2013-12-18 ルネサスエレクトロニクス株式会社 半導体装置
US8533641B2 (en) 2011-10-07 2013-09-10 Baysand Inc. Gate array architecture with multiple programmable regions

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Also Published As

Publication number Publication date
JPH06501813A (ja) 1994-02-24
AU7899191A (en) 1991-12-10
EP0528956A1 (de) 1993-03-03
DE69131399T2 (de) 1999-12-16
EP0528956A4 (de) 1994-01-05
US5341041A (en) 1994-08-23
DE69131399D1 (de) 1999-08-05
US5055716B1 (de) 1992-12-15
KR100217210B1 (ko) 1999-09-01
US5055716A (en) 1991-10-08
EP0528956B1 (de) 1999-06-30
WO1991018447A1 (en) 1991-11-28

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties