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A PMOS ROM address line decoding structure comprises: two sets of decoding area located on two sides of memory region, that forms several PMOS transistors with array structure, and implanting ion to conduct transistor in specific position to compose address decoding circuit, and implanting P-type code into PMOS channel area to avoid junction breakdown leakage; on internal and external position of each decoding area individually forming grounding transistor and power transistor corresponding to each word line position in memory region, in which the gate of each ground transistor and power transistor is connected to one enable signal; by potential change of enable signal making each word line represent low potential state on non-operating, and on performing read operation, through decoding area sending one high potential signal to selected word line to prevent leakage definitely.
TW84100817A1995-01-281995-01-28PMOS ROM address line decoding structure
TW280946B
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