JPS57148363A - Gate array - Google Patents

Gate array

Info

Publication number
JPS57148363A
JPS57148363A JP56033807A JP3380781A JPS57148363A JP S57148363 A JPS57148363 A JP S57148363A JP 56033807 A JP56033807 A JP 56033807A JP 3380781 A JP3380781 A JP 3380781A JP S57148363 A JPS57148363 A JP S57148363A
Authority
JP
Japan
Prior art keywords
mos transistors
gate
fan out
sized
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56033807A
Other languages
Japanese (ja)
Inventor
Tsuneo Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56033807A priority Critical patent/JPS57148363A/en
Publication of JPS57148363A publication Critical patent/JPS57148363A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To allow to increase no gate retardation time even when the number of fan out is increased for the subject gate array by a method wherein the gate array is constituted of a plurality of C-MOS transistors of reference size and a plurality of C-MOS transistors of the size multiplied by the natural numbers which are aligned on the same Si substrate. CONSTITUTION:A plurality of reference sized C-MOS transistors 11, a plurality of double-sized C-MOS transistors 12, and a plurality of threefold-sized C-MOS transistors 13 are provided on the Si substrate 10, and the substrate 10 for one chip component as above is formed by connecting it to all directions. At this point, the double-size above-mentioned means the area ratio of the transistors. Then, in order to form the inverter gate of the fan out number 2, inverter gates 14 and 15 are arranged, and they are connected in the final masking process using a metal 16. Accordingly, even when the transistors of large charging output are combined and the fan out number is increased, the gate retardation time remains unchanged when compared with that of the fan out number 1.
JP56033807A 1981-03-11 1981-03-11 Gate array Pending JPS57148363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56033807A JPS57148363A (en) 1981-03-11 1981-03-11 Gate array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56033807A JPS57148363A (en) 1981-03-11 1981-03-11 Gate array

Publications (1)

Publication Number Publication Date
JPS57148363A true JPS57148363A (en) 1982-09-13

Family

ID=12396744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56033807A Pending JPS57148363A (en) 1981-03-11 1981-03-11 Gate array

Country Status (1)

Country Link
JP (1) JPS57148363A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594139A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Logical large-scale integrated circuit
JPS6065546A (en) * 1983-09-20 1985-04-15 Fujitsu Ltd Gate array type integrated circuit
EP0147998A2 (en) * 1983-12-23 1985-07-10 Fujitsu Limited Semiconductor IC output circuitry
EP0150423A2 (en) * 1983-12-17 1985-08-07 Kabushiki Kaisha Toshiba C-MOS basic cells arrangement
US4611236A (en) * 1983-07-09 1986-09-09 Fujitsu Limited Masterslice semiconductor device
JPS6424443A (en) * 1987-07-21 1989-01-26 Nec Corp Gate array
US5289021A (en) * 1990-05-15 1994-02-22 Siarc Basic cell architecture for mask programmable gate array with 3 or more size transistors
US5341041A (en) * 1990-05-15 1994-08-23 Siarc Basic cell for BiCMOS gate array

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594139A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Logical large-scale integrated circuit
JPH0479143B2 (en) * 1982-06-30 1992-12-15 Fujitsu Ltd
US4611236A (en) * 1983-07-09 1986-09-09 Fujitsu Limited Masterslice semiconductor device
JPS6065546A (en) * 1983-09-20 1985-04-15 Fujitsu Ltd Gate array type integrated circuit
JPH0479145B2 (en) * 1983-09-20 1992-12-15 Fujitsu Ltd
EP0150423A2 (en) * 1983-12-17 1985-08-07 Kabushiki Kaisha Toshiba C-MOS basic cells arrangement
EP0147998A2 (en) * 1983-12-23 1985-07-10 Fujitsu Limited Semiconductor IC output circuitry
JPS60136238A (en) * 1983-12-23 1985-07-19 Fujitsu Ltd Gate array lsi device
JPS6424443A (en) * 1987-07-21 1989-01-26 Nec Corp Gate array
US5289021A (en) * 1990-05-15 1994-02-22 Siarc Basic cell architecture for mask programmable gate array with 3 or more size transistors
US5341041A (en) * 1990-05-15 1994-08-23 Siarc Basic cell for BiCMOS gate array

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