WO2022009618A1 - 抵抗変化型不揮発性記憶装置およびその書き込み方法 - Google Patents

抵抗変化型不揮発性記憶装置およびその書き込み方法 Download PDF

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Publication number
WO2022009618A1
WO2022009618A1 PCT/JP2021/022553 JP2021022553W WO2022009618A1 WO 2022009618 A1 WO2022009618 A1 WO 2022009618A1 JP 2021022553 W JP2021022553 W JP 2021022553W WO 2022009618 A1 WO2022009618 A1 WO 2022009618A1
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Prior art keywords
resistance
current
period
constant current
volatile storage
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English (en)
French (fr)
Japanese (ja)
Inventor
賢 河合
幸治 片山
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Nuvoton Technology Corp Japan
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Nuvoton Technology Corp Japan
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Priority to JP2022534981A priority Critical patent/JP7708759B2/ja
Priority to CN202180043696.4A priority patent/CN115917651B/zh
Publication of WO2022009618A1 publication Critical patent/WO2022009618A1/ja
Priority to US18/057,067 priority patent/US12190950B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0078—Write using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0083—Write to perform initialising, forming process, electro forming or conditioning
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the present disclosure relates to a resistance-changing non-volatile storage device including a memory cell composed of a resistance-changing non-volatile storage element whose resistance value changes reversibly based on an electric signal, and a writing method thereof.
  • the resistance change type non-volatile storage element has a property that the resistance value is reversibly changed by an electric signal or the like, and further, an element capable of non-volatilely storing data corresponding to this resistance value.
  • Examples of the resistance change type non-volatile storage device include ReRAM based on the change in the electric resistance value due to the oxidation-reduction reaction, MRAM based on the change in the magnetoresistance, and PCRAM based on the change in the electric resistance value due to the phase change.
  • resistance-changing non-volatile storage devices can control the resistance value and stabilize the operation by controlling the amount of current flowing through the resistance-changing non-volatile storage element and the applied voltage value in the rewriting operation. It has been known.
  • Such a resistance-changing non-volatile storage device is disclosed in, for example, Patent Document 1.
  • the write current for changing the resistance-changing element from the high-resistance state to the low-resistance state is increased. If it is reduced, there is a problem that the initial operation window cannot be sufficiently secured.
  • the operation window refers to the difference between the read current obtained in the high resistance state and the read current obtained in the low resistance state. If this difference is large enough, stable read operation is guaranteed. On the contrary, the smaller the difference, the greater the possibility that a read error will occur. Further, the operation window tends to be deteriorated by a high cycling operation, that is, a rewriting operation many times (for example, 100,000 times).
  • the initial operation window refers to an operation window at the time of the initial rewriting operation immediately after manufacturing (for example, about several tens or several hundred times from the first time).
  • an object of the present disclosure is to provide a resistance change type non-volatile storage device capable of expanding the initial operation window and suppressing deterioration of the operation window due to a large number of rewriting operations, and a writing method thereof.
  • the resistance-changing non-volatile storage device includes a resistance-changing element capable of reversibly changing between a high-resistance state and a low-resistance state, and for changing the high-resistance state to the low-resistance state.
  • a current supply circuit for energizing the resistance changing element with a low resistance current is provided, and the low resistance current has a downward stepped current waveform.
  • the initial operation window can be expanded, and deterioration of the operation window due to a large number of rewrite operations can be suppressed.
  • FIG. 1A is a diagram showing a configuration example of a main part of the resistance change type non-volatile storage device according to the embodiment.
  • FIG. 1B is a diagram showing an example of a current waveform of a low resistance current.
  • FIG. 2A is a diagram showing a more detailed configuration example of the main part of the resistance change type non-volatile storage device according to the embodiment.
  • FIG. 2B is a timing chart illustrating the operation of the constant current control circuit in the embodiment.
  • FIG. 3 is an explanatory diagram showing a circuit symbol and a cross section of the resistance change type non-volatile memory element according to the embodiment.
  • FIG. 4 is a diagram showing a processing flow for an experiment including a large number of rewriting processes.
  • FIG. 5 is a normal expected value plot diagram showing the cell current distribution of the 1T1R memory cell as the experimental result of the comparative example.
  • FIG. 6 is a normal expected value plot diagram showing the cell current distribution of the 1T1R memory cell in FIG. 2A in the embodiment.
  • FIG. 7 is a block diagram showing a configuration example of the resistance change type non-volatile storage device according to the embodiment.
  • FIG. 8 is a diagram showing an example of a writing circuit of the resistance change type non-volatile storage device according to the embodiment.
  • FIG. 9 is a diagram showing an example of a column selection circuit of the resistance change type non-volatile storage device according to the embodiment.
  • FIG. 10 is a row selection circuit diagram of the resistance change type non-volatile storage device according to the embodiment.
  • FIG. 11 is a timing chart of the resistance change type non-volatile storage device according to the embodiment.
  • FIG. 12 is a bias diagram of a memory cell of the resistance change type non-volatile storage device according to the embodiment.
  • FIG. 13 is a diagram showing a configuration of a resistance change type non-volatile storage device as a comparative example.
  • FIG. 14 is an explanatory diagram showing the rewriting characteristics described in Non-Patent Document 1.
  • FIG. 15 is a diagram showing driving conditions of the resistance change type non-volatile storage device according to the embodiment.
  • FIG. 16 is a diagram showing a modified example of the main part of the resistance change type non-volatile storage device according to the embodiment.
  • FIG. 17 is a diagram showing a modified example of the current waveform of the low resistance current in the embodiment.
  • FIG. 18 is a diagram showing another modification of the current waveform of the low resistance current in the modification of the embodiment.
  • Patent Document 1 in a storage device including a 1T1R memory cell in which a resistance change type non-volatile storage element and a transistor are connected, a drive circuit (pass transistor) suitable for parallel driving of low resistance operation and high resistance operation is driven.
  • the method is shown.
  • the resistance-changing non-volatile storage element is composed of an insulator film such as SiN, SiO2, Gd2O3, and a conductor film such as a metal film containing a metal element such as Cu, Ag, Zr, and Al, an alloy film, and a metal compound film. Has been done.
  • the resistance change type non-volatile memory element can be set to a desired low resistance value according to the driving current value. Further, by limiting the driving current so that an excessive current does not flow to the resistance change type non-volatile memory element, deterioration of the resistance change type non-volatile memory element can be suppressed.
  • ReRAM resistance-changing non-volatile storage devices
  • flash memory which is the mainstream of conventional non-volatile storage devices.
  • the number of rewrites of the flash memory which used to be about 100,000 times, has decreased to about several thousand times with the progress of miniaturization and large capacity, but it is said that it has high rewrite performance in this respect as well.
  • ReRAM is expected as a non-volatile storage device to replace the flash memory.
  • an excessive current is applied by a method of setting the resistance-changing non-volatile storage element to a desired resistance value or a rewriting operation of the resistance-changing non-volatile storage element.
  • the destruction and deterioration of the resistance-changing non-volatile memory element are suppressed.
  • the issue of achieving both the number of rewrites has not been disclosed and has not been overcome.
  • an object of the present disclosure is to provide a resistance change type non-volatile storage device capable of expanding the initial operation window and suppressing deterioration of the operation window due to a large number of rewriting operations, and a writing method thereof.
  • the resistance change type non-volatile storage device includes a resistance change element capable of reversibly changing between a high resistance state and a low resistance state, and the high resistance state to the above.
  • a current supply circuit for energizing the resistance changing element with a low resistance current for changing to a low resistance state is provided, and the low resistance current has a current waveform of the low resistance current on the time axis.
  • the current supply circuit 24 has one period and a second period following the first period, and the current supply circuit 24 applies the first current to the resistance changing element in the first period and is smaller than the first current in the second period.
  • a current is applied to the resistance changing element, the first current at the end of the first period is not zero, and the second current at the start of the second period is not zero.
  • the initial operation window can be enlarged, and deterioration of the operation window due to a large number of rewrite operations can be suppressed.
  • FIG. 1A is a diagram showing a configuration example of a main part of the resistance change type non-volatile storage device 2 according to the embodiment.
  • the figure shows a circuit related to a low resistance writing operation that changes a resistance change type non-volatile memory element from a high resistance state to a low resistance state as the main configuration of the present disclosure. Further, in the figure, the circuit related to the high resistance writing operation, which is not the main part of the present disclosure, is omitted.
  • the resistance change type non-volatile storage device 2 shown in the figure includes a memory cell 3, an LR BL selection switch 13, an LR SL selection switch 14, and a current waveform control circuit 24.
  • the memory cell 3 has a resistance change type non-volatile storage element RSE and a memory cell transistor 1 connected in series.
  • the memory cell 3 in the figure is shown as a representative of one memory cell in a memory array composed of a plurality of memory cells 3 arranged in a matrix.
  • the resistance-changing non-volatile storage element RSE may be simply referred to as a resistance-changing element RSE below.
  • the resistance changing element RSE is an element that can reversibly change between a high resistance state and a low resistance state, and as a readable and writable storage element by making the high resistance state and the low resistance state correspond to digital binary values. Function. One end of the resistance change type non-volatile storage element RSE is connected to the source S of the memory cell transistor 1, and the other end is connected to the bit line BL.
  • the memory cell transistor 1 has a drain D, a source S, and a gate G.
  • the drain D is connected to the source line SL.
  • the gate G is connected to the memory cell gate terminal MG.
  • the source S is connected to one end of the resistance changing element RSE.
  • the drain and source of the transistor may be on either side of the gate, but in the present specification, the side connected to the resistance change type non-volatile storage element RSE is defined as the source S.
  • the voltage VwL shown in the figure is applied to the memory cell gate MG during the period of the low resistance writing operation. As a result, the memory cell transistor 1 is turned on.
  • Both the LR BL selection switch 13 and the LR SL selection switch 14 are turned on during the low resistance write operation.
  • the current waveform control circuit 24 is a current supply circuit, and energizes the resistance changing element with a low resistance current LRIcell for changing from a high resistance state to a low resistance state.
  • the low resistance current LRIcell has a downward stepped current waveform.
  • the current waveform control circuit 24 drives the low resistance current LRIcell to reduce the constant current in the low resistance write operation in two steps by making the current waveform a downward step.
  • This drive is called a constant current two-step reduction drive. According to this drive, deterioration of the initial window can be suppressed in the writing operation of changing from the high resistance state to the low resistance state, and the deterioration of the operation window during high cycling (for example, when rewriting 100,000 times) is suppressed. can do. For example, even when miniaturized, a highly reliable and stable rewriting operation can be realized over a long period of time.
  • FIG. 1B is a diagram showing an example of a current waveform of a low resistance current.
  • the downstep current waveform has a first period and a second period following the first period.
  • the current supply circuit that is, the current waveform control circuit 24 energizes the resistance changing element RSE with the first constant current in the first period, and energizes the resistance changing element RSE with the second constant current smaller than the first constant current in the second period. ..
  • the current supply circuit that is, the current waveform control circuit 24 includes the LR conversion current limiting element 26 as the first constant current source and the LR conversion current limiting element 27 as the second constant current source.
  • the current waveform control circuit 24 generates the first constant current by superimposing the constant current from the first constant current source and the constant current from the second constant current source in the first period. Further, the current waveform control circuit 24 generates a constant current from either the first constant current source or the second constant current source as the second constant current in the second period.
  • the current supply circuit that is, the current waveform control circuit 24 has a first switch (that is, a constant current control switch 31) connected in series with the first constant current source and a second switch connected in series with the second constant current source. Includes a switch (ie, constant current control switch 32).
  • the current waveform control circuit 24 energizes the resistance changing element RSE with the first constant current by making both the first switch and the second switch conductive in the first period. Further, the current waveform control circuit 24 energizes the resistance changing element RSE with the second constant current by making one of the first switch and the second switch in the non-conducting state and the other in the conducting state in the second period. do.
  • the resistance changing element RSE is energized with a current value higher than that in the second period in the first period. Since the resistance changing element is energized with a current value lower than that of the first period in the second period, window deterioration during high cycling can be suppressed. Further, the operation of the first switch and the second switch can easily generate a downward stepped current waveform.
  • the first period is shorter than the second period.
  • the first period may be 10% or less of the second period.
  • the operation window is enlarged in the first period when the relatively high first constant current is energized, and the deterioration of the operation window due to the high cycling operation is suppressed in the second period when the relatively low second constant current is energized. can do.
  • the operation window can be sufficiently expanded. More specifically, the first period may be 5 n seconds or less, and the second period may be 50 n seconds or more. By doing so, the writing operation to the low resistance state can be performed at high speed.
  • the second constant current may be 60% or less of the first constant current. By doing so, it is possible to reduce the power consumption of the writing operation to the low resistance state. More specifically, the first constant current may be 125 ⁇ A or more, and the second constant current may be 75 ⁇ A or less. By doing so, it is possible to reduce the power consumption of the writing operation to the low resistance state.
  • FIG. 2A is a diagram showing a detailed configuration example of the resistance change type non-volatile storage device 2 according to the embodiment.
  • FIG. 2A the circuit related to the high resistance write operation omitted in FIG. 1A is also specified, and a specific example of the current waveform control circuit 24 and its peripheral circuits is shown.
  • the resistance change type non-volatile storage device 2 shown in FIG. 2A includes a memory cell 3, a bit line drive circuit 22b, and a source line drive circuit 23.
  • the bit line drive circuit 22b includes an LR BL selection switch 13 and an HR BL selection switch 16 and is connected to the memory cell 3 via the bit line BL.
  • the LR BL selection switch 13 is a switch that connects the ground and the bit line BL, and is turned on during the low resistance operation.
  • the HR conversion BL selection switch 16 is a switch that connects the HR conversion power supply terminal 17 and the bit line BL, and is turned on during the high resistance operation. That is, the HR BL selection switch 16 is a switch for supplying the memory cell 3 with a high resistance current pulse for increasing the resistance of the memory cell 3.
  • a voltage VdH for generating a pulse voltage for increasing resistance is applied to the power supply terminal 17 for HR conversion.
  • the source line drive circuit 23 includes an LR power supply terminal 11, an LR SL selection switch 14, an HR SL selection switch 18, a current waveform control circuit 24, and a write pulse width control terminal 33.
  • the source line drive circuit 23 is a circuit that energizes the resistance changing element RSE with a low resistance current.
  • the low resistance current has a downward stepped current waveform instead of a single rectangular pulse waveform.
  • a voltage VdL for generating a pulse current for lowering the resistance is applied to the power supply terminal 11 for LR.
  • the LR SL selection switch 14 connects the source line SL and the current supply terminal of the current waveform control circuit 24, and is turned on during the period of low resistance operation.
  • the current supply terminal of the current waveform control circuit 24 refers to a connection point between the constant current control switch 31 and the constant current control switch 32.
  • the HR SL selection switch 18 is a switch that connects the ground and the source line SL, and is turned on during the period of high resistance operation.
  • the current waveform control circuit 24 shows a more specific circuit example of the current supply circuit, that is, the current waveform control circuit 24 shown in FIG. 1A.
  • the current waveform control circuit 24 of FIG. 2A includes a constant current control circuit 25, an LR current limiting element 26, and an LR current limiting element 27.
  • the current waveform control circuit 24 is composed of a constant current control circuit 25 and LR current limiting elements 26 and 27 including a polyclonal transistor.
  • the constant current control circuit 25 is composed of a delay circuit 28 having a first delay time (for example, 5 ns), a NAND circuit 29, an inverter 30, and constant current control switches 31 and 32 including a polyclonal transistor.
  • the write pulse width control terminal 33 is connected to the input of the delay circuit 28, the input terminal of the inverter 30, and the gate terminal of the constant current control switch 32.
  • One input terminal of the NAND circuit 29 is connected to the output terminal of the delay circuit 28.
  • the other input terminal of the NAND circuit 29 is connected to the output of the inverter 30.
  • the output terminal of the NAND circuit 29 is connected to the gate terminal of the constant current control switch 31.
  • the source terminals of the LR current limiting elements 26 and 27 are both connected to the LR power supply terminal 11, and the drain terminals are connected to the source terminals of the constant current control switches 31 and 32, respectively.
  • the drain terminals of the current control switches 31 and 32 are both connected to the LR SL selection switch 14.
  • the LR current limiting element 26 is composed of a polyclonal transistor, and a clamp voltage Vc1 ( ⁇ VdL) is given to the gate terminal thereof. Further, the LR current limiting element 27 is composed of a polyclonal transistor, and a clamp voltage Vc2 ( ⁇ VdL) is given to the gate terminal thereof. Therefore, the LR current limiting elements 26 and 27 become substantially constant current sources due to the current saturation region characteristics of the LR current limiting elements 26 and 27, and the constant currents Set1 (for example, 100 ⁇ A) and Set2 (for example, for example), respectively. The current can be limited to 75 ⁇ A).
  • the transistor size and its gate voltage are set so that the output currents of the LR current limiting elements 26 and 27 can be limited to the constant currents Set1 and Set2.
  • the write pulse width control terminal 33 is a terminal for inputting a voltage Vi that specifies the timing of the low resistance current for low resistance and the pulse width (that is, the LR write pulse width).
  • the constant current control switch 31 is the LR current limiting element 26, that is, the first switch connected in series with the first current source, and is turned on for the first period according to the pulse voltage Vc.
  • the constant current control switch 32 is a second switch connected in series with the LR current limiting element 27, that is, the second current source, and is turned on for the second period according to the pulse voltage Vi.
  • the circuit including the delay circuit 28, the NAND circuit 29, and the inverter 30 is a control circuit that controls the continuity and non-conduction of the first switch, that is, the constant current control switch 31.
  • this circuit is a circuit for generating a negative logic pulse voltage Vc obtained by differentiating the head of the negative logic pulse voltage Vi input from the write pulse width control terminal 33.
  • the pulse width of the negative logic pulse voltage Vc determines the first period in which the constant current control switch 31 is turned on. Further, the pulse width of the pulse voltage Vi of the negative logic determines the second period in which the constant current control switch 32 is turned on.
  • the LR BL selection switch 13 and the LR SL selection switch 14 are controlled on for a predetermined period, and the HR BL selection switch 16 and the HR SL selection switch 18 are controlled off.
  • a negative logic voltage pulse Vi having a pulse width for a predetermined period for example, 100 ns
  • the output voltage Va of the delay circuit 28 becomes the voltage pulse Vi as shown in FIG. 2B.
  • the voltage pulse is delayed by 5 ns.
  • the output voltage Vb of the inverter 30 is a voltage pulse in which the voltage pulse Vi is logically inverted.
  • the output voltage Vc of the NAND circuit 29 is the result of NAND calculation between the output voltage Va and the output voltage Vb, and the pulse width is a negative logic voltage pulse having a first delay time (for example, 5 ns).
  • the constant current control switches 31 and 32 are both activated for 5 ns and turned on, and the LR write current is generated by both the LR current limiting elements 26 and 27. , Is limited to the sum of the constant current Issue1 (100 ⁇ A) and the constant current Issue2 (75 ⁇ A) (eg, 175 ⁇ A).
  • the constant current control switch 32 keeps on, and the constant current control switch 31 turns off. After that, during the remaining 95 ns period (t2 to t3), only the constant current control switch 31 is turned off, and the LR write current is reduced to the constant current Issue2 (75 ⁇ A) by the LR current limiting element 27.
  • the LR write current is flowed from the source line SL side to the bit line BL side while controlling the current reduction in two stages.
  • the current waveform control circuit 24 energizes the resistance changing element RSE with the low resistance current having the downward stepped current waveform shown in FIG. 2B as the low resistance operation.
  • the LR BL selection switch 13 and the LR SL selection switch 14 are turned off, the HR BL selection switch 16 and the HR SL selection switch 18 are turned on for a predetermined period, and the bit lined BL is used. A current is passed in the direction of the source line SL.
  • FIG. 3 is an explanatory diagram showing a circuit symbol and a cross-sectional structure of the resistance change type non-volatile memory element RSE in the embodiment.
  • the terminal on the side connected to the source S of the memory cell transistor 1 is connected to the terminal A and the bit line BL.
  • the terminal is the terminal B.
  • the resistance-changing non-volatile memory element 3000a shown in FIG. 3B shows the structure of the resistance-changing non-volatile storage element RSE after manufacturing and before forming.
  • the resistance change type non-volatile memory element 3000a includes a first electrode 81 (lower electrode) corresponding to the terminal A side, a second electrode 84 (upper electrode) corresponding to the terminal B side, and an oxygen-deficient transition metal oxide. It is provided with a resistance changing layer 85 composed of.
  • the resistance change layer 85 is a first transition metal oxide layer 82 composed of an oxygen-deficient transition metal oxide and a transition metal oxide having a smaller oxygen deficiency than the first transition metal oxide layer 82. It is configured by laminating the configured second transition metal oxide layer 83.
  • the resistance change type non-volatile memory element RSE shown in FIG. 3 (c) shows the structure after forming.
  • a minute filament 86 serving as a conductive path is formed in the local region of the second transition metal oxide layer 83.
  • a redox reaction occurs in the minute filament 86, and the resistance value changes to cause a resistance change phenomenon.
  • the resistance change operation described in the present disclosure is due to the structure of the resistance change type non-volatile storage element RSE after this forming.
  • the same kind of transition metal is used for the first transition metal oxide layer 82 and the second transition metal oxide layer 83, and the oxygen-deficient type is used as the first transition metal oxide layer 82.
  • the first tantalum oxide layer (hereinafter referred to as the first Ta oxide layer) and the second tantalum oxide layer (hereinafter referred to as the second Ta oxide layer) as the second transition metal oxide layer 83.
  • the film thickness of the second Ta oxide layer is preferably 1 nm or more and 10 nm or less.
  • the first electrode 81 is configured by laminating titanium nitride (TiN) and tantalum nitride (TaN), and the second electrode 84 contains a noble metal material such as iridium (Ir). It is configured.
  • An oxygen-deficient transition metal oxide is an oxide having a lower oxygen content (atomic ratio: ratio of the number of oxygen atoms to the total number of atoms) than an oxide having a chemical quantitative composition. ..
  • Oxides with a stoichiometric composition usually have an insulator, or a very high resistance value.
  • the transition metal is Ta
  • the stoichiometric oxide composition is Ta2O5 and the ratio of the number of atoms of Ta to O (O / Ta) is 2.5. Therefore, in the oxygen-deficient Ta oxide, the atomic ratio of Ta and O is larger than 0 and smaller than 2.5.
  • the oxygen content of the second Ta oxide layer as the second transition metal oxide layer 83 is higher than the oxygen content of the first Ta oxide layer as the first transition metal oxide layer 82. Is also getting higher. In other words, the oxygen deficiency of the second Ta oxide layer is less than the oxygen deficiency of the first Ta oxide layer.
  • the degree of oxygen deficiency refers to the ratio of deficient oxygen to the amount of oxygen constituting the oxide of the stoichiometric composition in each transition metal. For example, when the transition metal is tantalum (Ta), the composition of the stoichiometric oxide is Ta2O5, so it can be expressed as TaO2.5. The oxygen deficiency of TaO2.5 is 0%.
  • the oxygen content is the ratio of the number of oxygen atoms contained to the total number of atoms constituting the transition metal oxide.
  • the oxygen content of Ta2O5 is the ratio of the number of oxygen atoms to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, the oxygen-deficient tantalum oxide has an oxygen content of more than 0 and less than 71.4 atm%.
  • a transition metal other than tantalum or a part of the metal may be used.
  • the transition metal tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W) and the like can be used, and as the metal, aluminum (Al) and the like can be used. .. Since the transition metal can take a plurality of oxidation states, it is possible to realize different resistance states by a redox reaction.
  • x is 0.9 or more and 1.6 or less and x is 0.9 or more and 1.6 or less when the composition of the first hafnium oxide layer as the first transition metal oxide layer 82 is HfOx.
  • the composition of the second hafnium oxide layer as the second transition metal oxide layer 83 is HfOy and y is larger than the value of x, the resistance value of the resistance changing layer 85 is stabilized. It has been confirmed that it changes at high speed.
  • the film thickness of the second hafnium oxide layer is preferably 3 nm or more and 4 nm or less.
  • x is 0.9 or more and 1.4 or less when the composition of the first zirconium oxide layer as the first transition metal oxide layer 82 is ZrOx, and
  • the composition of the second zirconium oxide layer as the second transition metal oxide layer 83 is ZrOy and y is larger than the value of x, the resistance value of the resistance changing layer 85 is stabilized. It has been confirmed that it changes at high speed.
  • the film thickness of the second zirconium oxide layer is preferably 1 nm or more and 5 nm or less.
  • the resistance changing layer 85 has a two-layer laminated structure, but it may be an oxygen-deficient transition metal oxide layer and may be composed of a single resistance changing layer.
  • the second electrode 84 connected to the second transition metal oxide layer 83 having a smaller oxygen deficiency is oxidized to a second transition metal such as platinum (Pt), iridium (Ir), palladium (Pd), and the like. It is composed of a transition metal constituting the material layer 83 and a material having a higher standard electrode potential than the material constituting the first electrode 81. With such a configuration, a redox reaction selectively occurs in the second transition metal oxide layer 83 near the interface between the second electrode 84 and the second transition metal oxide layer 83. , A stable resistance change phenomenon can be realized.
  • a second transition metal such as platinum (Pt), iridium (Ir), palladium (Pd), and the like. It is composed of a transition metal constituting the material layer 83 and a material having a higher standard electrode potential than the material constituting the first electrode 81.
  • a first transition metal oxide layer 82 composed of a first transition metal and a second transition metal composed of a second transition metal different from the first transition metal are used.
  • a laminated structure composed of the oxide layer 83 may be used.
  • the oxygen deficiency of the second transition metal oxide layer is smaller than the oxygen deficiency of the first transition metal oxide layer.
  • the resistance value of the second transition metal oxide layer 83 is higher than the resistance value of the first transition metal oxide layer 82.
  • the standard electrode potential of the second transition metal is smaller than the standard electrode potential of the first transition metal.
  • titanium oxide TiO2
  • the standard electrode potential of the second transition metal is smaller than the standard electrode potential of the first transition metal.
  • the resistance value of the second transition metal oxide layer 83 which has a higher resistance value than that of the first transition metal oxide layer 82, is formed to be, for example, about several hundred M ⁇ to 1 G ⁇ .
  • the resistance value of the filament 86 is about 100 k ⁇ to several M ⁇ even when it becomes a high resistance state due to the oxidation reaction.
  • the voltage applied between the first electrode 81 and the second electrode 84 is divided by the first transition metal oxide layer 82 and the second transition metal oxide layer 83, and the resistance value is higher.
  • the second transition metal oxide layer 83 is higher, but the associated current path is not uniform in the second transition metal oxide layer 83.
  • the current is concentrated in the region of the filament 86 having a lower resistance value in the second transition metal oxide layer 83. Therefore, control of the current and voltage that can stably and continuously perform the resistance change operation generated in the filament 86 is important in the case of the resistance change type non-volatile memory element that operates in the filament model.
  • FIG. 13 is a diagram showing a configuration of a resistance change type non-volatile storage device as a comparative example.
  • This comparative example is a circuit similar to the resistance change type non-volatile storage device of Patent Document 1, and shows a circuit of a 1T1R memory cell and its surroundings.
  • FIG. 13A shows a high resistance operation.
  • the thick downward arrow indicates the current HR cell energized in the resistance-changing non-volatile memory element RSE.
  • FIG. 13B shows a low resistance operation.
  • the thick arrow pointing upward indicates the current LRIcell energized in the resistance change type non-volatile memory element RSE.
  • the resistance change type non-volatile storage device of FIG. 13 is mainly different from FIG. 2A in that the source line drive circuit 22a is provided instead of the source line drive circuit 23.
  • the source line drive circuit 22a is a circuit that energizes the memory cell 3 with a single constant current square wave pulse in the low resistance operation.
  • the LR BL selection switch 13 and the LR SL selection switch 14 are controlled to be off, the HR BL selection switch 16 and the HR SL selection switch 18 are controlled to be ON for a predetermined period, and the source is controlled from the bit line BL.
  • a current HR cell is passed through the memory cell 3 in the direction of the line SL.
  • the LR BL selection switch 13 and the LR SL selection switch 14 are controlled on for a predetermined period, the HR BL selection switch 16 and the HR SL selection switch 18 are controlled off, and the source line SL is used.
  • a current LRIcell is passed through the memory cell 3 in the direction of the bit line BL.
  • the memory cell 3 can be evaluated in 1-bit units by applying a predetermined voltage to each terminal of the source line drive circuit 22a and the bit line drive circuit 22b.
  • the memory cell array is configured and evaluated. Is configured to share the source line drive circuit 22a and the bit line drive circuit 22b with a plurality of memory cells 3.
  • a plurality of memory cells can be selectively evaluated, and rewriting evaluation can be performed in units of 1 bit or in units of a plurality of bits of memory cell array.
  • the LR BL selection switch 13, the LR SL selection switch 14, the HR BL selection switch 16, and the HR SL selection switch 18 are general selection circuits composed of transistors, but the voltages at these points are used. The transistor size, transistor configuration, and gate voltage are set so that the drop is minimized and the current is not rate-determining.
  • the voltage VdL is connected to the LR power supply terminal 11
  • the voltage Vclamp ( ⁇ VdL) is connected to the LR clamp control terminal 12
  • the HR power supply terminal 17 is used.
  • the voltage VdH is constantly applied to.
  • a voltage VwH is applied to the memory cell gate terminal MG of the memory cell transistor 1, and the HR BL selection switch 16 and the HR SL selection switch 18 perform on control for a period of 100 ns.
  • the LR BL selection switch 13 and the LR SL selection switch 14 are set to off control.
  • a voltage VwL is applied to the memory cell gate terminal MG of the memory cell transistor 1 to make an LR BL selection switch.
  • the 13 and the LR SL selection switch 14 perform on control for a period of 100 ns.
  • the HR-based BL selection switch 16 and the HR-based SL selection switch 18 are set to off control.
  • the constant current source composed of the polyclonal current transistor 10 can limit the current to the constant current Iset, and the gate voltage is given so that the impedance of the memory cell transistor 1 operates sufficiently low. Therefore, the current Imos flowing in the memory cell transistor 1 and the current LRIcell flowing in the resistance change type non-volatile storage element RSE are limited to Set.
  • FIG. 4 is a diagram showing a processing flow for an experiment including a large number of rewriting processes.
  • the processing flow of FIG. 13 was performed for each of the resistance-changing non-volatile storage device of the comparative example of FIG. 13 and the resistance-changing non-volatile storage device 2 of FIG. 2A.
  • FIG. 4 first, the resistance reduction operation and the cell current measurement of a plurality of evaluation target bits (for example, about 1 kb) in the memory cell array are performed (S41, S42). Subsequently, the operation of increasing the resistance of the bit to be evaluated and the cell current measurement are performed (S43, S44). This resistance change operation is repeated 100,000 times to end (S45).
  • the cell current measurement confirms whether the memory cell 3 has been brought into a desired resistance state by the resistance change operation, and measures the current value by applying a low voltage at which the resistance change type non-volatile storage element RSE is not disturbed. It is a thing.
  • FIG. 15 is a diagram showing driving conditions of the resistance change type non-volatile storage device according to the embodiment. This driving condition was applied to the resistance-changing non-volatile storage device of the comparative example of FIG. 13 and the resistance-changing non-volatile storage device 2 of FIG. 2A.
  • the voltage VdL of the LR power supply terminal 11 is 2.8 V
  • the voltage V clamp of the LR clamp control terminal 12 is 1.73 V, which is an intermediate voltage.
  • the voltage VdH of the HR power supply terminal 17 is constantly applied to 1.7V.
  • 1.73 V is applied to the voltage Vclamp in order to configure a constant current source of 175 ⁇ A, but the set current value of the constant current source can be changed by changing the voltage Vclump.
  • the memory cell gate terminal MG of the memory cell transistor 1 applies 3.0 V at a voltage VwL, and the LR BL selection switch 13 and the LR SL selection switch 14 perform on control for a period of 100 ns.
  • the HR-based BL selection switch 16 and the HR-based SL selection switch 18 are set to off control.
  • the memory cell gate terminal MG of the memory cell transistor 1 applies 1.8 V at a voltage VwH, and the HR BL selection switch 16 and the HR SL selection switch 18 perform on control for a period of 100 ns.
  • the LR BL selection switch 13 and the LR SL selection switch 14 are set to off control.
  • both Vc1 and Vc2 gave 1.73V.
  • the photodiode transistor lengths of the LR current limiting elements 26 and 27 are the same, and the ratio of the transistor widths of the LR current limiting element 26 and the LR current limiting element 27 is set to 4: 3.
  • the LR conversion current limiting element 26 produces a first constant current value of 100 ⁇ A
  • the LR conversion current limiting element 27 produces a second constant current value of 75 ⁇ A.
  • FIG. 5 is a normal expected value plot diagram showing the cell current distribution of the 1T1R memory cell of the comparative example of FIG. 13 as an experimental result.
  • FIG. 5A is a plot of the normal expected values of the high resistance state (HR) and the low resistance state (LR) in the initial state in which the post-forming operation is stable when the set current value of the constant current source is set to 75 ⁇ A.
  • the cell current distribution (about 1 kb).
  • the white squares indicate the cell current in the high resistance state, and the white circles indicate the cell current in the low resistance state.
  • FIG. 5B is a plot of the normal expected values of the high resistance state (HR) and the low resistance state (LR) in the initial state in which the post-forming operation is stable when the set current value of the constant current source is set to 175 ⁇ A.
  • the cell current distribution (about 1 kb).
  • the white squares indicate the cell current in the high resistance state, and the white circles indicate the cell current in the low resistance state.
  • FIG. 5C shows an initial state in which the operation after forming is stable when the set current value of the constant current source is set to 175 ⁇ A, and a high resistance state (HR) and a low resistance state (LR) after rewriting 100,000 times. It is a transition of the cell current distribution (about 1 kb) plotted with the normal expected value of.
  • the white squares indicate the high resistance state in the initial state
  • the white circles indicate the low resistance state in the initial state
  • the black diamonds indicate the low resistance state after 100,000 times
  • the black triangles indicate the cell current in the high resistance state after 100,000 times. ..
  • the written low resistance state or high resistance state is read out by the sense amplifier circuit, and the operation of determining whether the data is "1" or "0" is performed. conduct. For that purpose, a difference (operation window) of a predetermined value or more is required between the minimum cell current value in the low resistance state and the maximum cell current value in the high resistance state.
  • the LR write current when the LR write current is set to a low current of 75 ⁇ A, the LR cell current decreases, the operation window becomes less than the predetermined value, and it is very small, and it is stable in the sense amplifier circuit. Data discrimination becomes difficult.
  • FIG. 6 is a normal expected value plot diagram showing the cell current distribution of the 1T1R memory cell in FIG. 2A according to the embodiment of the present disclosure.
  • the white squares indicate the high resistance state in the initial state
  • the white circles indicate the low resistance state in the initial state
  • the black diamonds indicate the low resistance state after 100,000 times
  • the black triangles indicate the cell current in the high resistance state after 100,000 times. ..
  • the pulse width is shorter than that of the conventional write current pulse (constant current 175 ⁇ A, pulse width 100 ns).
  • the filament 86 is annealed by applying a low current by a low current pulse (constant current 75 ⁇ A, 95 ns) in two periods, and the voids (defects) formed by the movement of oxygen ions in the filament 86 are uniformly and stabilized, and the number of rewrites is increased. Deterioration of resistance change operation due to increase (increased variation in cell current distribution) can be significantly reduced, and stable and continuous operation of rewriting is possible.
  • FIG. 7 is a block diagram showing a configuration example of the resistance change type non-volatile storage device according to the embodiment of the present disclosure.
  • the resistance change type non-volatile storage device 4000 includes a memory main body 300 on a semiconductor substrate, and the memory main body 300 includes a memory array 301, a column selection circuit 302, and a row selection circuit.
  • the peripheral circuit unit 306 includes a voltage generation circuit 308, a word line voltage switching circuit 316, an address input circuit 317, and an input / output circuit 318, and is a memory main unit 300 and a peripheral circuit unit 306 based on a control signal input from the outside. It is provided with a control circuit 307 that controls the operation of the above.
  • the voltage generation circuit 308 includes a word line power supply 309 for low resistance, a word line power supply 310 for high resistance, a word line power supply 311 for reading, a power supply 312 for a low resistance clamp, and a pulse power supply 313 for low resistance. It also includes a pulse power supply 314 for increasing resistance and a precharge power supply 315.
  • These power supplies use the external power supply VDD as an input and generate a predetermined set voltage value shown in FIG.
  • the values shown here are based on the voltage values in the constant current two-step reduction type drive in the low resistance described with reference to FIG. 1A.
  • the output VwL of the low resistance word line power supply 309, the output VwH of the high resistance word line power supply 310, and the output Vr of the read word line power supply 311 are supplied to the word line voltage switching circuit 316.
  • the output VwL is selected by the low resistance write instruction signal WEL
  • the output VwH is selected by the high resistance write instruction signal WEH
  • the output Vr is selected by the read instruction signal RE. It is supplied to 303.
  • the output Vc1 / Vc2 of the low resistance clamp power supply 312, the output VdL of the low resistance pulse power supply 313, and the output VdH of the high resistance pulse power supply 314 are supplied to the write circuit 304.
  • the output VPR of the precharge power supply 315 is supplied to the column selection circuit 302 and the write circuit 304.
  • Each power supply circuit is composed of a general step-down circuit that steps down the external power supply VDD to generate a predetermined voltage, and detailed description thereof will be omitted.
  • each power supply circuit has a trimming function that is generally used so that the output voltage value can be finely adjusted in order to reflect manufacturing variations and set the optimum operating point.
  • any or all of these power supply circuits may be configured to be generated by boosting the voltage from the external power supply VDD.
  • any or all of these power supply circuits do not necessarily have to be provided in the resistance change type non-volatile storage device 4000, and may be configured to provide a predetermined voltage as an external power supply.
  • the address input circuit 317 receives an address signal input from the outside and instructs the designated memory cell 3 of the memory array 301.
  • the input / output circuit 318 receives the data input signal Din input to the DQ terminal from the outside and supplies it to the memory main body 300 as a write signal, or receives the read output signal from the memory main body 300 and outputs the output signal Dout to the outside. Output via the DQ terminal.
  • the memory cells 3 described above as the basic data of the present disclosure are arranged in a matrix with m rows and n columns.
  • the upper left is M11, and M11, M21, ..., Mm1 in the row direction and M11, M12, ..., M1n in the column direction represent each memory cell.
  • a plurality of word lines WL1, WL2, ..., WLm output in the row direction from the row selection circuit 303 are connected to the memory cell gate terminal MG of each memory cell 3.
  • the plurality of bit lines BL1, BL2, ..., BLn and the plurality of source lines SL1, SL2, ..., SLn output in the column direction from the column selection circuit 302 are alternately arranged in parallel, and each memory cell 3 It is connected to the bit line BL and the source line SL.
  • the column selection circuit 302 and the write circuit 304 are arranged on the upper side and the lower side of the memory array 301, and control the writing from both ends of the bit lines BL1, BL2, ..., BLn and the source lines SL1, SL2, ..., SLn. It is composed.
  • This is arranged on both sides for the purpose of reducing the influence of IR drop caused by the wiring resistance of the bit line and the source line, but it depends on the number of memory cells 3 arranged and the wiring resistance value of the applied manufacturing process. Therefore, if the influence of IR drop is small, for example, an arrangement of only the lower side may be used.
  • the write operation to the memory cell 3 is the same as in the case of the description of the basic data of the present disclosure.
  • the bit line BL is set to a low potential and the source line SL is set to a high potential, the resistance is lowered and the bit line BL is set to a high potential.
  • the source line SL is set to a low potential, the resistance is increased.
  • FIG. 8 is a diagram showing a circuit example of the writing circuit 304.
  • the output VdL of the low resistance pulse power supply 313 is connected to the LR power supply terminal 11, and the output Vc1 / Vc2 of the low resistance clamp power supply 312 is the LR current limiting elements 26 and 27.
  • the current waveform control circuit 24 in which the voltage pulse Vi for reducing resistance output from the control circuit 307 is input to the write pulse width control terminal 33 to the gate terminal, and the constant current control switches 31 and 32 inside the current waveform control circuit 24. It is connected in series with the converted drain terminal and is connected to the source line input terminal SLin via a epitaxial transistor 333 whose gate input is the output of the inverter 332 which is connected in series with the low resistance write instruction signal WEL.
  • the source line input terminal SLin uses the high resistance write instruction signal WEH as the gate input, the SOI transistor 334 whose source is ground, the output VPR of the precharge power supply 315 as the source input, and the precharge instruction signal NPR as the gate input.
  • the epitaxial transistor 335 is connected to the OFDM transistor 342 whose source is ground with the read instruction signal RE as the gate input.
  • bit line writing circuit 336 the output VdH of the pulse power supply 314 for increasing resistance is connected to the source input, the output of the inverter 337 having the high resistance writing instruction signal WEH as input is connected to the gate input, and the bit line input terminal BLin is connected to the drain.
  • the polyclonal transistor 338 and the bit line input terminal BLin are used for the drain input, the low resistance write instruction signal WEL is used for the gate input, the nanotube transistor 339 for which the source is connected to the ground, and the precharge instruction signal NPR are used for the gate input.
  • the output VPR of the precharge power supply 315 is connected to the source input, the voltage line input terminal BLin is connected to the drain input, and the readout instruction signal RE is connected to the gate input, and the bit line input terminal BLin is connected to the drain input.
  • the line output signal BLout is composed of an nanotube transistor 341 connected to the source.
  • the bit line output signal BLout is connected to the read circuit 305.
  • the LR SL selection switch 14 corresponds to the polyclonal transistor 333
  • the LR BL selection switch 13 corresponds to the MIMO transistor 339
  • the HR BL selection switch 16 corresponds to the polyclonal transistor 338.
  • the HR-ized SL selection switch 18 corresponds to the MIMO transistor 334.
  • FIG. 9 shows a diagram showing a circuit example of the column selection circuit 302.
  • bit line selection circuit 350 and the source line selection circuit 353 are arranged alternately.
  • bit line BLi and source line SLi are connected to the bit line input terminal BLin and source line input terminal SLin, and the remaining non-selected bit line BLi and source line SLi are precharged to the VPR.
  • FIG. 10 is a diagram showing a circuit example of the row selection circuit 303.
  • the row selection circuit 303 includes a decode circuit 370 that generates a decode signal that specifies a select row based on the address selection instruction signal generated by the address input circuit 317, and a word line driver 371 that is connected to the decode signal. There is.
  • cycle T1 writes low resistance to memory cell M11
  • cycle T2 writes high resistance to memory cell M12
  • cycle T3 reads low resistance state of memory cell M11
  • cycle T4 is high of memory cell M12. An operation example of reading the resistance state is shown.
  • the precharge instruction signal NPR is a negative logic signal, and the precharge instruction is given at 0V.
  • the precharge instruction is given at 0V.
  • the input / output DQ terminal is set to a high level as data "1" writing.
  • the precharge instruction signal NPR is set to a high level, and the precharge state of the bit line input terminal BLin and the source line input terminal SLin is released.
  • the WL1 which is the selection word line and the column selection signal CL1 which is the selection column are set to the high level. At this time, the voltage of the word line WL1 becomes VwL for low resistance writing. Further, the bit line BL1 and the source line SL1 which are the selection columns are decharged and connected to the bit line input terminal BLin and the source line input terminal SLin. On the other hand, the precharge is maintained for the other non-selected bit lines and non-selected source lines.
  • the low resistance write instruction signal WEL is set to the high level and the negative logic voltage pulse Vi is set to the low level for a period of 100 ns, and the source line receives this.
  • the input terminal SLin is driven to the high potential side and the bit line input terminal BLin is driven to the low potential side, and the constant current two-step reduction low resistance write operation described in detail as the basic data of the present disclosure is performed on the selected memory cell M11. Will be.
  • the selection word line WL1 and the selection column selection signal CL1 are set to 0V, the memory cell M11 is in the non-selection state, and the bit lines BL1 and the source line SL1 are precharged. Is started.
  • the precharge instruction signal NPR is set to 0V, the precharge of the bit line input terminal BLin and the source line input terminal SLin is started, and the low resistance write cycle ends.
  • the input / output DQ terminal is set to a low level as data "0" writing.
  • the precharge instruction signal NPR is set to a high level, and the precharge state of the bit line input terminal BLin and the source line input terminal SLin is released.
  • the selection word line WL1 and the selection column column selection signal CL2 are set to high levels. At this time, the voltage of the word line WL1 becomes VwH for high resistance writing. Further, the bit line BL2 and the source line SL2, which are the selection columns, are decharged and connected to the bit line input terminal BLin and the source line input terminal SLin. On the other hand, the precharge is maintained for the other non-selected bit lines and non-selected source lines.
  • the high resistance write instruction signal WEH is set to a high level for a period of 100 ns in response to the data "0" write instruction of the input / output DQ terminal, and in response to this, the source line input terminal SLin is set to the low potential side and the bit.
  • the line input terminal BLin is driven to the high potential side, and the high anti-writing operation described in detail as the basic data of the present disclosure is performed on the selected memory cell M12.
  • the cell current in this timing chart shows the absolute value, and the flow direction is opposite to that of the cycle T1.
  • the selection word line WL1 and the selection column selection signal CL2 are set to 0V, the memory cell M12 is in the non-selection state, and the bit lines BL2 and the source line SL2 are precharged. Is started.
  • the precharge instruction signal NPR is set to 0V, the precharge of the bit line input terminal BLin and the source line input terminal SLin is started, and the high resistance write cycle ends.
  • the precharge instruction signal NPR is set to a high level, and the precharge state of the bit line input terminal BLin and the source line input terminal SLin is released.
  • the WL1 which is the selection word line and the column selection signal CL1 which is the selection column are set to the high level.
  • the voltage of the word line WL1 becomes Vr for reading.
  • the precharge of the bit line BL1 and the source line SL1 which are the selection columns is released, and the components are connected to the bit line input terminal BLin and the source line input terminal SLin.
  • the precharge is maintained for the other non-selected bit lines and non-selected source lines.
  • the read instruction signal RE is set to a high level during the read operation period (here, set to 150 ns), the NOTE transistor 342 is turned on, and the selected source line SL1 is driven to the low potential side via the source line input terminal SLin.
  • the NOTE transistor 341 is turned on, and the selected bit line BL1 is connected to the bit line output signal BLout via the bit line input terminal BLin.
  • the bit line output signal BLout is connected to the read circuit 305, and data “1” or data “0” is discriminated by the magnitude of the amount of current flowing from the bit line BL side to the source line SL side.
  • a low resistance state is written in the memory cell M11, a larger current flows than in the high resistance state, the read circuit 305 determines that the data is "1", and a high level is output from the input / output DQ terminals. ..
  • the selection word line WL1 and the selection column selection signal CL1 are set to 0V, the memory cell M11 is in the non-selection state, and the precharge of the bit line BL1 and the source line SL1 starts. Will be done.
  • the precharge instruction signal NPR is set to 0V, the precharge of the bit line input terminal BLin and the source line input terminal SLin is started, and the read operation cycle ends.
  • the read operation of the memory cell M12 in the cycle T4 in the high resistance state has a different selection column from the cycle T3, and the selected memory cell M12 is written in the high resistance state, so that the current is higher than in the case of the low resistance state. Since it is the same except that the read circuit 305 determines that the data is "0" and outputs a low level from the input / output DQ terminals, detailed description thereof will be omitted.
  • FIG. 12 is a bias diagram of a memory cell of the resistance change type non-volatile storage device according to the embodiment.
  • the memory cell state shown in FIG. 12 (a) is an example of the state of the selected memory cell in which low resistance writing is performed described as the present embodiment in a schematic cross-sectional view, and is in the cycle T1 described in FIG.
  • the state of the selected memory cell M11 corresponds to this.
  • the memory cell transistor 402 is composed of a gate electrode 404 which is also a word line, a gate oxide film 405, a drain 406 of an N-type diffusion layer connected to a source line SL, and a source 407 of an N-type diffusion layer on a semiconductor substrate 401.
  • the source 407 and the lower electrode of the resistance change type non-volatile memory element RSE are connected, and the bit wire BL and the upper electrode are connected.
  • the source line SL is set to approximately the voltage VdL- ⁇ ( ⁇ represents the voltage drop due to the LR current limiting elements 26 and 27), the bit line is set to a low voltage of 0V, and the word line is set to a low voltage of 0V.
  • the voltage VwL is given.
  • the memory cell transistor 402 is turned on, a channel 408 is formed, and a current flows from the drain 406 to the source 407.
  • the memory cells As the manufacturing process becomes finer, the memory cells also become finer, which enables higher integration. In that case, the plane size of the memory cell transistor 402 is reduced and the gate oxide film 405 is thinned, so that the maximum voltage that can be applied to the gate electrode 404 decreases as the miniaturization progresses.
  • the channel 408 is formed in the selected memory cell 400, an electric field between the gate electrode 404 and the channel 408 is substantially applied to the gate oxide film 405.
  • the electric field applied to the gate oxide film 405 is highest in the channel 408 near the source 407, which has a lower voltage.
  • the bit line BL is 0V
  • the potential of the source 407 is the voltage between terminals of the resistance change type non-volatile memory element RSE (about 1 to 1.2V).
  • the potential difference between the gate electrode 404 and the channel 408 can be substantially relaxed to about 1.8V to 2.0V.
  • the memory cell state shown in FIG. 12B is a schematic cross-sectional view illustrating the state of the non-selected memory cell in the same row as the selected memory cell in which the low resistance write is performed described as the present embodiment.
  • the state of the non-selected memory cell M12 and the like in the cycle T1 described with reference to FIG. 11 corresponds to this.
  • the source line SL and the bit line BL of the non-selected column are precharged to the voltage VPR (1.1V). Since the resistance-changing non-volatile memory element RSE has conductivity, the voltage of the source 407 of the N-type diffusion layer as well as the drain 406 of the N-type diffusion layer becomes VPR.
  • the gate electrode 404 has a voltage VwL, and both the gate-source potential and the gate-drain potential are equal to or higher than the threshold voltage of the memory cell transistor 402, the memory cell transistor 402 is turned on, and the channel 411 is formed.
  • the voltage of this channel 411 has the same VPR as the bit line BL and the source line SL. Therefore, the potential difference between the gate electrode 404 and the channel 411 can be relaxed to 1.9V.
  • the bit line BL and the source line SL of the non-selected memory cell in the same row as the selected memory cell in which the low resistance write is performed are conventionally generally performed.
  • the voltage of the channel 421 is 0V, which is the same as that of the bit line BL and the source line SL.
  • the potential difference between the gate electrode 404 and the channel 421 is 3.0 V, which is more than 1 V higher than the memory cell state of FIG. 12 (b), which is less desirable when applying a finer process.
  • the memory cell state of FIG. 12 (d) is the opposite of the memory cell state of FIG. 12 (c), and the bit line of the non-selected memory cell in the same row as the selected memory cell in which the low resistance write is performed.
  • the state when BL and the source line SL are precharged to the same voltage as the voltage VwL of the gate electrode 404 is illustrated. In this case, the memory cell transistor 402 is turned off and no channel is formed. Therefore, an electric field is applied to the gate oxide film 405 between the gate electrode 404 and the semiconductor substrate 401. Since 0 V is generally set for the semiconductor substrate 401, the electric field of the gate oxide film 405 in the memory cell state of FIG. 12 (c) is substantially 3.0 V, and a finer process is applied. It is not very desirable if you do.
  • the precharge voltage VPR of the source line SL and the bit line BL of the memory cell of the non-selected column is subtracted from the voltage VwL of the selected word line by the threshold voltage Vtss of the memory cell transistor 402 so that the channel is formed. It may be applied to a finer process by setting the relationship of a predetermined voltage lower than the voltage and higher than 0V. That is, the precharge voltage VPR may be set as follows.
  • the precharge voltage VPR it is desirable to set the precharge voltage VPR to a voltage lower than VwL-Vtuns and a higher voltage in terms of lowering the electric field of the gate oxide film 405, but on the other hand, all non-selective bit lines and non-selective bit lines and non-selective bit wires. Precharging the selected source line to a predetermined voltage also leads to the contradictory problem of increased power consumption.
  • VPR (VwL-Vtuns) / 2.
  • the current waveform control circuit 24 is provided on the LR power supply terminal 11 side in order to reduce the low resistance write current by two steps of constant current, but the current waveform control circuit having the same function is GND. Needless to say, it may be provided on the terminal side.
  • the memory cell transistor is used as the switch element, but in order to reduce the cell area, a bidirectional diode may be used.
  • tantalum oxide is used as the resistance changing layer 85, but the same effect can be obtained by using tantalum aluminum oxide (TaAlO) in which aluminum (Al) is added to the tantalum oxide. Can be done.
  • TaAlO tantalum aluminum oxide
  • FIG. 16 is a diagram showing a modified example of the main part of the resistance change type non-volatile storage device according to the embodiment.
  • the resistance change type non-volatile storage device 2 in the figure is different from FIG. 1A in that it includes a current waveform control circuit 24a instead of the current waveform control circuit 24.
  • a current waveform control circuit 24a instead of the current waveform control circuit 24.
  • the current waveform control circuit 24a includes a waveform generation unit 35, a DAC 36, and a transistor 37.
  • the waveform generation unit 35 generates waveform data Ctl, which is a digital signal showing a current waveform of a low resistance current.
  • the waveform generation unit 35 is composed of, for example, a ROM for storing time-series sample values showing waveform data Ctl, or a dedicated circuit.
  • the DAC 36 is a digital-to-analog conversion circuit that converts the waveform data Ctrl from the waveform generation unit 35 into an analog signal.
  • the DAC 36 supplies the converted analog signal as a gate voltage Vgp to the gate of the transistor 37.
  • the transistor 37 is a pMOS transistor as a current source that supplies a low resistance current having a waveform corresponding to the gate voltage Vgp to the memory cell 3 via the LR SL selection switch 14.
  • FIG. 17 is a diagram showing a modified example of the current waveform of the low resistance current in the embodiment.
  • (A) of the figure shows the gate voltage Vgp output from the DAC 36 to the gate of the transistor 37.
  • the current in (b) in the figure indicates a low resistance current output from the transistor 37. Since the transistor 37 is a pMOS transistor, the low resistance current has a waveform inverted with respect to a change in the gate voltage Vgp.
  • the current waveform of the low resistance current has once in the first period and the second period following the first period on the time axis.
  • the portion of the low resistance current corresponding to the first period is called the first current.
  • the portion of the low resistance current corresponding to the second period is called the second current.
  • the first current is a triangular wave and has a first peak current Ip1.
  • the second current is a substantially constant current and has a current value Ip2 smaller than the first peak current Ip1.
  • the first current at time t2 at the end of the first period is not 0, and the second current Ip2 at time t2 at the start of the second period is not 0. That is, the first current does not drop from the peak to zero within the first period, and the second current is a non-zero value at the start of the second period.
  • FIG. 18 is a diagram showing another modification of the current waveform of the low resistance current in the modification of the embodiment.
  • the low resistance current has a current waveform having the shape of a sawtooth wave having a steep fall in the first period.
  • the time width of the first period, the time width of the second period, the peak value Ip1 of the first current, and the second current Ip2 may be the same as those in FIG. 1B.
  • the low resistance current has a current waveform having the shape of a sawtooth wave having a steep rise in the first period.
  • the low resistance current has a triangular wave current shape in the first period, and has a current waveform in which the second current is stepwise reduced in the second period.
  • the low resistance current has two or more pairs of a first period and a second period as shown in (c) of the figure.
  • the time width of the first period, the time width of the second period, the peak value Ip1 of the first current, and the second current Ip2 do not have to be the same as those in FIG. 1B.
  • the resistance change type non-volatile storage device 2 includes a resistance change element (RSE) capable of reversibly changing between a high resistance state and a low resistance state, and the high resistance.
  • a current waveform control circuit 24a as a current supply circuit for energizing the resistance changing element with a low resistance current for changing from a state to the low resistance state is provided, and the current waveform of the low resistance current is a time axis.
  • the current supply circuit 24a has a first period and a second period following the first period, and the current supply circuit 24a applies the first current to the resistance changing element in the first period, and from the first current in the second period.
  • a small second current is applied to the resistance changing element, the first current at the end of the first period is not zero, and the second current at the beginning of the second period is not zero.
  • deterioration of the initial window can be suppressed in writing that changes from a high resistance state to a low resistance state, and deterioration of the operation window during high cycling (for example, when rewriting 100,000 times) is suppressed. be able to. For example, even when miniaturized, a highly reliable and stable rewriting operation can be realized over a long period of time.
  • the first current may be a constant current.
  • the first current may have a peak value larger than that of the second current.
  • the current waveform control circuit 24a can use a waveform that is not a constant current as the first current.
  • the low resistance current may have a downward stepped current waveform.
  • the current waveform control circuit 24a generates the first current and the second current as a downward stepped current waveform. This also suppresses the deterioration of the initial window, and also suppresses the deterioration of the operation window during high cycling (for example, when rewriting 100,000 times).
  • the current waveform control circuit 24a as the current supply circuit energizes the resistance changing element with the first constant current in the first period, and the second constant current smaller than the first constant current in the second period. May be energized in the resistance changing element.
  • a drive that reduces the constant current in two stages is performed.
  • This drive is called a constant current two-step reduction drive.
  • This drive is suitable for generating the downstep current waveform described above.
  • the period of energization is not limited to having only the first period and the second period, and may have the third, fourth, ... n periods separately.
  • the current waveform control circuit 24 as the current supply circuit includes an LR current limiting element 26 as a first constant current source and an LR current limiting element 27 as a second constant current source.
  • the current supply circuit generates the first constant current by superimposing the constant current from the first constant current source and the constant current from the second constant current source in the first period, and the first constant current is generated.
  • a constant current from either the first constant current source or the second constant current source may be generated as the second constant current in two periods.
  • the resistance changing element is energized with a current value higher than that in the second period in the first period, a sufficient initial window can be secured. Since the resistance changing element is energized with a current value lower than that of the first period in the second period, window deterioration during high cycling can be suppressed.
  • the current waveform control circuit 24 as the current supply circuit is further connected in series with the constant current control switch 31 as the first switch connected in series with the first constant current source and the second constant current source.
  • a constant current control switch 32 as a second switch connected to the current supply circuit is provided by making both the first switch and the second switch conductive in the first period.
  • the second constant current is applied to the resistance changing element to make one of the first switch and the second switch in a non-conducting state and the other in a conducting state in the second period.
  • a current may be applied to the resistance changing element.
  • the first period may be shorter than the second period.
  • the operation window is enlarged in the first period when the relatively high first constant current is energized, and the deterioration of the operation window due to the high cycling operation is caused in the second period when the relatively low second constant current is energized. It can be suppressed.
  • the first period may be 10% or less of the second period.
  • the operation window can be enlarged in the first period of 10% or less of the second period.
  • the first period may be 5 n seconds or less, and the second period may be 50 n seconds or more.
  • the writing operation to the low resistance state can be performed at high speed.
  • the second constant current may be 60% or less of the first constant current.
  • the first constant current may be 125 ⁇ A or more, and the second constant current may be 75 ⁇ A or less.
  • the resistance changing element RSE is interposed between the first electrode 81, the second electrode 84 formed facing the first electrode, and the first electrode 81 and the second electrode 84.
  • the resistance changing layer 85 may have a resistance changing layer 85, and the resistance changing layer 85 may include a transition metal oxide.
  • the transition metal oxide may contain at least one oxide of tantalum and hafnium.
  • the resistance changing element may be formed on a semiconductor substrate, and the second electrode 84 may be formed on the semiconductor substrate at a distance from the first electrode 81.
  • the resistance-changing non-volatile storage device includes a plurality of memory cells arranged in a matrix, and the memory cells include a switch element and the resistance-changing element connected in series with the switch element. You may have.
  • the switch element may be an IGMP transistor or a bidirectional diode.
  • the writing method of the resistance-changing non-volatile storage device is a resistance-changing non-volatile storage device having a resistance-changing element RSE that can reversibly change between a high-resistance state and a low-resistance state as a memory cell.
  • a first constant current is applied to the resistance changing element in the first period, and the second period succeeds the first period.
  • a second constant current smaller than the first constant current is applied to the resistance changing element in two periods.
  • a resistance-changing non-volatile storage device realized by making various modifications that can be conceived by those skilled in the art or by arbitrarily combining the components in the embodiment, and a writing method thereof, without departing from the gist of the present disclosure. Is also included in this disclosure.
  • a resistance change type non-volatile storage device having a memory cell composed of a resistance change element whose resistance value changes reversibly based on an electric signal and a switch element such as a transistor. It is useful for realizing a highly reliable memory because the number of rewritable times can be improved easily with a practical write control method and a circuit area without significantly increasing the array area.

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