WO2021095401A1 - 回路基板及び回路基板の製造方法 - Google Patents

回路基板及び回路基板の製造方法 Download PDF

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Publication number
WO2021095401A1
WO2021095401A1 PCT/JP2020/037876 JP2020037876W WO2021095401A1 WO 2021095401 A1 WO2021095401 A1 WO 2021095401A1 JP 2020037876 W JP2020037876 W JP 2020037876W WO 2021095401 A1 WO2021095401 A1 WO 2021095401A1
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Prior art keywords
circuit board
conductor
ceramic material
low
tapered
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2020/037876
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English (en)
French (fr)
Japanese (ja)
Inventor
知樹 加藤
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to DE112020004962.0T priority Critical patent/DE112020004962T5/de
Priority to CN202080078909.2A priority patent/CN114747301B/zh
Priority to JP2021555946A priority patent/JP7243856B2/ja
Publication of WO2021095401A1 publication Critical patent/WO2021095401A1/ja
Priority to US17/741,906 priority patent/US12133328B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • H05K1/0204Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00Arrangements for thermal protection or thermal control
    • H10W40/20Arrangements for cooling
    • H10W40/22Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69Insulating materials thereof
    • H10W70/692Ceramics or glasses
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/096Vertically aligned vias, holes or stacked vias
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827Tapered, e.g. tapered hole, via or groove
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1126Firing, i.e. heating a powder or paste above the melting temperature of at least one of its constituents
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/685Shapes or dispositions thereof comprising multiple insulating layers

Definitions

  • the present invention relates to a circuit board and a method for manufacturing a circuit board.
  • a circuit board on which a heat generating element such as a light emitting element or a semiconductor element is mounted a circuit board using a low temperature sintered ceramic material as an insulating material is known.
  • Patent Document 1 describes a light emitting element in which a penetrating metal body having a higher thermal conductivity than that of the insulating substrate is provided through the insulating substrate on an insulating substrate made of low-temperature fired ceramics fired at 1050 ° C. or lower.
  • the wiring board is disclosed.
  • Patent Document 1 a step of forming a through hole at a predetermined position of the ceramic green sheet, a step of laminating a metal sheet on the ceramic green sheet having the through hole formed, and a step of laminating a through hole forming portion in the ceramic green sheet from the metal sheet side.
  • a part of the metal sheet is embedded in the through hole, and the ceramic green sheet and the metal sheet are integrated.
  • a penetrating metal body is formed in the insulating substrate.
  • Patent Document 1 the insulating substrate and the penetrating metal body are joined by simultaneously firing a ceramic green sheet and a metal sheet.
  • the bonding strength is weak because the bonding area between the insulating substrate and the penetrating metal body is small. If the bonding strength between the insulating substrate and the penetrating metal body is weak, the insulating substrate and the penetrating metal body may be peeled off due to thermal stress caused by heat generation of the heat generating element mounted on the penetrating metal body. It has also been requested that the heat dissipation property of the penetrating metal body be further improved.
  • thermal via in the present specification a conductor (hereinafter referred to as thermal via in the present specification) suitable for heat dissipation from a heat generating element.
  • the circuit board of the present invention is a circuit board in which wiring is provided in an insulating layer containing a low-temperature sintered ceramic material, and the wiring includes a thermal via having an area of 0.0025 mm 2 or more when viewed from above.
  • the thermal via is characterized in that a plurality of tapered conductors having a tapered end face are laminated, and each end face of the tapered conductor is in contact with the insulating layer.
  • the method for manufacturing a circuit board of the present invention includes a step of forming a through hole in a ceramic green sheet containing a low-temperature sintered ceramic material, in which the top surface diameter and the bottom surface diameter are different and the top surface diameter area is 0.0025 mm 2 or more.
  • the step of filling the through hole with a conductor paste containing metal to form a via conductor, and a plurality of ceramic green sheets on which the via conductor is formed are laminated so that the positions of the via conductors overlap to form a laminated body. It is characterized by having a step of producing and a step of firing the laminate.
  • FIG. 1 is a cross-sectional view schematically showing an example of a part of the configuration of the circuit board of the present invention.
  • FIG. 2 is a diagram showing each layer of the tapered conductor of the thermal via shown in FIG. 1 separately.
  • FIG. 3 is an enlarged view schematically showing the end face of the tapered conductor.
  • FIG. 4 is a cross-sectional photograph showing a part of the thermal via and the insulating layer in contact with the thermal via included in the circuit board of the present invention.
  • FIG. 5 is a cross-sectional view schematically showing an example of a circuit board in which a high thermal conductive ceramic substrate in contact with the lower surface of the thermal via is provided and a heat generating element is mounted on the upper surface of the thermal via.
  • FIG. 6 is a cross-sectional view schematically showing an example of the laminated body.
  • FIG. 7 is a graph showing the joint strength in Example 1 and Comparative Example 1.
  • the present invention is not limited to the following configurations, and can be appropriately modified and applied without changing the gist of the present invention. It should be noted that the present invention is also a combination of two or more individual preferable configurations of the circuit board and the method for manufacturing the circuit board according to the embodiment of the present invention described below.
  • the circuit board of the present invention is provided with wiring in an insulating layer containing a low-temperature sintered ceramic material.
  • the wiring is provided with a thermal via having an area of 0.0025 mm 2 or more when viewed from above.
  • FIG. 1 is a cross-sectional view schematically showing an example of a part of the configuration of the circuit board of the present invention.
  • FIG. 1 schematically shows a portion of the circuit board 1 in which the insulating layer 20 is provided with the thermal via 30 which is a part of the wiring.
  • the insulating layer is a layer containing a low temperature sintered ceramic material.
  • the low-temperature sintered ceramic material means a ceramic material that can be sintered at a firing temperature of 1000 ° C. or lower and can be simultaneously fired with silver or copper, which is preferably used as a metal material for wiring. To do.
  • the low-temperature sintered ceramic material preferably contains SiO 2- CaO-Al 2 O 3- B 2 O 3 glass ceramic or SiO 2- Mg O-Al 2 O 3- B 2 O 3 glass ceramic.
  • Wiring is provided on the circuit board.
  • the wiring is preferably made of a metal having high electrical conductivity, which is mainly composed of silver or copper. It is also preferable that the material is the same as that of the thermal via described later. In this specification, the detailed description of the wiring other than the thermal via is omitted.
  • the thermal via is a wiring having an area of 0.0025 mm 2 or more when viewed from above.
  • Thermal vias are used as wiring for heat dissipation because of their large area.
  • a heat generating element can be mounted on the upper surface of the thermal via and used to dissipate heat from the lower surface of the thermal via through the thermal via.
  • the purpose of providing the thermal via is different from that of the stack via provided for making an electrical connection in the thickness direction of the circuit board.
  • the area of the thermal via is a 0.0025 mm 2 or more, preferably 0.015 mm 2 or more, and more preferably 0.25 mm 2 or more. Further, the area of the thermal via viewed from above is preferably 100 mm 2 or less.
  • the shape of the thermal via viewed from above is not particularly limited, and examples thereof include a circle and a polygon (square, rectangle, etc.). From the viewpoint that the area of the thermal via viewed from above is within the above range, when the shape of the thermal via viewed from above is circular, the diameter thereof is preferably 0.06 mm or more. Further, when the shape of the thermal via viewed from above is square, it is preferable that one side thereof is 0.05 mm or more.
  • the thermal via is formed by laminating a plurality of layers of tapered conductors whose end faces are tapered.
  • the thermal via 30 shown in FIG. 1 has a configuration in which four layers of tapered conductors are laminated.
  • a plurality of layers of tapered conductors are integrated, so the boundary between each layer of the tapered conductors is not shown in FIG.
  • the insulating layer corresponding to the plurality of tapered conductors is also integrated, the boundary between each layer of the insulating layer is not shown in FIG.
  • FIG. 2 is a diagram showing each layer of the tapered conductor of the thermal via shown in FIG. 1 separately.
  • the tapered conductors 31, 32, 33, 34 have tapered end faces 31a, 32a, 33a, 34a on the right side thereof, and the tapered end faces 31b, 32b, 33b, 34b are also provided on the left side thereof, respectively.
  • the end faces 31a, 32a, 33a, 34a of the tapered conductors 31, 32, 33, 34 are in contact with the insulating layers 21, 22, 23, 24, respectively.
  • the "tapered shape" in the present specification means a shape in which the direction of the end face in the cross-sectional view of the tapered conductor is not parallel to the thickness direction, and the upper surface or the lower surface of the tapered conductor protrudes.
  • FIG. 2 shows a tapered shape in which the upper surface of the tapered conductor protrudes
  • the tapered shape may have a protruding lower surface.
  • a tapered conductor having a protruding upper surface thereof and a tapered conductor having a protruding lower surface thereof may coexist.
  • the end face forming the tapered shape is not limited to a straight line in the cross-sectional view thereof, and the end face forming the tapered shape may be a curved line.
  • the thermal via has a shape in which a plurality of layers of tapered conductors having tapered end faces are laminated, and each end face of the tapered conductor is in contact with an insulating layer.
  • the bonding area in the connection between the end face of the tapered conductor and the insulating layer becomes large, an anchor effect is generated, and the thermal via and the insulating layer are firmly bonded.
  • the thermal via and the insulating layer are firmly bonded in this way, the thermal via and the insulating layer are prevented from being peeled off due to the thermal stress caused by the heat generated by the heat generating element.
  • a void may be present in a part of the joint surface between the end surface of the tapered conductor and the insulating layer.
  • FIG. 3 is an enlarged view schematically showing the end face of the tapered conductor.
  • the taper length is indicated by a double-headed arrow L.
  • the taper length is defined as the difference between the tip of the protruding surface (upper surface in FIG. 3) and the tip of the non-protruding surface (lower surface in FIG. 3) of the taper conductor.
  • FIG. 3 also shows a diffusion portion 25, which is a portion in which the metal material constituting the tapered conductor is diffused in the insulating layer. The diffusion portion will be described in detail later.
  • the taper conductor preferably contains a metal having high electrical conductivity, which is mainly composed of silver or copper. Silver or copper can be co-fired with the low temperature sintered ceramic material. Further, the tapered conductor preferably contains a metal and a low-temperature sintered ceramic material forming an insulating layer. By mixing the low-temperature sintered ceramic material with the metal, the difference in the coefficient of thermal expansion from the insulating layer around the thermal via is reduced, and the bonding strength between the thermal via and the insulating layer is improved. From the viewpoint of improving the bonding strength between the thermal via and the insulating layer, the weight ratio of the low-temperature sintered ceramic material to the tapered conductor is preferably 10% or more.
  • the weight ratio of the low-temperature sintered ceramic material to the tapered conductor should not be too large, so that the weight ratio of the low-temperature sintered ceramic material to the tapered conductor is 50% or less. Is preferable.
  • the thickness of the thermal via is preferably 50 ⁇ m or more, and more preferably 100 ⁇ m or more.
  • the thickness of the thermal via is preferably 5000 ⁇ m or less. Increasing the thickness of the thermal via reduces the resistance of the thermal via, which is preferable because a large current can be passed through the thermal via.
  • the number of laminated taper conductors constituting the thermal via is not particularly limited, but the number of laminated layers is preferably 4 or more, and more preferably 16 or more. Moreover, it is preferable that the number of layers is 40 or less.
  • the thickness of one layer of the tapered conductor is preferably 25 ⁇ m or more, and preferably 150 ⁇ m or less.
  • the thermal via has a large area in the top view, the ratio of the top view area of the thermal via to the thickness of the thermal via becomes large. That is, it is preferable that the aspect ratio represented by (the equivalent circle diameter / thickness of the top view area) of the thermal via is 1 or more. Moreover, it is preferable that the aspect ratio is 25 or less.
  • the insulating layer in contact with each end face of the tapered conductor constituting the thermal via has a diffusion portion in which the metal material constituting the tapered conductor is diffused in the insulating layer.
  • FIG. 3 schematically shows the diffusion portion 25 in the insulating layers 21 and 22. The presence of the diffused portion can be confirmed by performing elemental analysis by EDX and detecting the metal material (for example, silver, copper, etc.) constituting the tapered conductor in the insulating layer. The presence of a diffusion portion in the insulating layer improves the bonding strength between the thermal via and the insulating layer.
  • the difference in the coefficient of thermal expansion near the interface between the thermal via and the insulating layer becomes gentle, the strength against thermal stress due to the difference in the coefficient of thermal expansion is improved, and the joint portion in a high temperature environment (for example, held at 80 ° C./30 minutes). Deterioration is prevented.
  • the metal material can be diffused into the insulating layer to form a diffused portion.
  • the presence of the diffused portion provides evidence that the conductor paste and the ceramic green sheet were co-fired in the process of manufacturing the circuit board.
  • FIG. 4 is a cross-sectional photograph showing a part of the thermal via and the insulating layer in contact with the thermal via included in the circuit board of the present invention.
  • the photograph shown in FIG. 4 is a cross-sectional photograph of the circuit board obtained in Example 1 described later.
  • FIG. 4 shows the thermal via 30 and the insulating layer 20.
  • the taper conductor 31 is represented as the taper conductor, and the end face 31a of the taper conductor is shown as the end face of the taper conductor by reference numerals.
  • the diffusion portion 25 is a portion in the insulating layer 20 adjacent to the thermal via 30 in the photograph in which the color tone is slightly changed and the blackness is increased, and the reference reference numeral 25 represents a part of the position. Is shown.
  • the taper length is indicated by a double-headed arrow L.
  • L The taper length
  • the thermal via is formed by laminating a plurality of layers of tapered conductors having tapered end faces and each end face of the tapered conductor is in contact with the insulating layer, the end face of the tapered conductor and the insulating layer An anchor effect is generated in the bonding, and the thermal via and the insulating layer are firmly bonded. Further, when the diffusion portion is present in the insulating layer, the bonding strength between the thermal via and the insulating layer is improved.
  • FIG. 5 is a cross-sectional view schematically showing an example of a circuit board in which a high thermal conductive ceramic substrate in contact with the lower surface of the thermal via is provided and a heat generating element is mounted on the upper surface of the thermal via.
  • FIG. 5 shows a high thermal conductive ceramic substrate 40 in contact with the lower surface of the thermal via 30 of the circuit board 1 and a heat generating element 50 mounted on the upper surface of the thermal via 30 via solder 60.
  • the circuit board of the present invention may be provided with a high thermal conductive ceramic substrate in contact with the lower surface of the thermal via.
  • a high thermal conductive ceramic substrate in contact with the lower surface of the thermal via, the heat from the thermal via can be directly transferred to the high thermal conductive ceramic substrate.
  • the high thermal conductivity ceramic substrate is preferably a sintered ceramic substrate, and the material thereof is preferably silicon nitride, aluminum nitride, alumina, silicon carbide, or the like.
  • the heat generating element mounted on the upper surface of the thermal via is preferably at least one type of element selected from the group consisting of a power element, a control element, a passive component, and a light emitting element.
  • the power element is preferably an element made of a wide bandgap semiconductor. Further, the wide bandgap semiconductor is preferably silicon carbide or gallium nitride.
  • the light emitting element is preferably at least one element selected from the group consisting of an LED element, an organic EL element, a LIDAR element, a RADAR element, and a millimeter wave element.
  • the circuit board of the present invention has a step of forming a through hole in a ceramic green sheet containing a low-temperature sintered ceramic material, which has a different top surface diameter and a bottom surface diameter and an area of the top surface diameter of 0.0025 mm 2 or more, and the above-mentioned through hole.
  • a ceramic green sheet containing a low-temperature sintered ceramic material is prepared.
  • the powder of the low-temperature sintered ceramic material described above can be used.
  • the ceramic green sheet include a slurry obtained by adding a resin, a dispersant, a plasticizer, and a solvent to the above powder, and mixing the slurry to form a sheet having a predetermined thickness by a doctor blade method.
  • a through hole having a different top surface diameter and bottom surface diameter and an area of 0.0025 mm 2 or more on the top surface diameter is formed in the ceramic green sheet.
  • the through hole can be formed by punching using a punch having a shape in which the upper surface diameter and the bottom surface diameter are different and the area of the upper surface diameter is 0.0025 mm 2 or more. Further, it can be performed by a laser puncher in which the area of the upper surface diameter is 0.0025 mm 2 or more and the upper surface diameter and the bottom surface diameter are different.
  • the through hole is filled with a conductor paste containing metal to form a via conductor.
  • a conductor paste it is preferable to use a paste containing silver or copper.
  • the conductor paste contains the metal and the low-temperature sintered ceramic material contained in the ceramic green sheet, and the weight ratio of the low-temperature sintered ceramic material to the total weight of the metal and the low-temperature sintered ceramic material is 50% or less. It is preferable to do so. Further, it is preferable that the weight ratio of the low temperature sintered ceramic material to the total weight of the metal and the low temperature sintered ceramic material is 10% or more.
  • the conductor paste may contain a resin component, a solvent, a dispersant and the like.
  • FIG. 6 is a cross-sectional view schematically showing an example of the laminated body.
  • the laminated body 101 shown in FIG. 6 is formed by laminating ceramic green sheets 124, 123, 122, 121 on which via conductors 134, 133, 132, and 131 are formed, respectively.
  • the positions of the via conductors 134, 133, 132, and 131 overlap.
  • the positions of the via conductors are shown so as to be completely aligned in the vertical direction, but if the positions of the via conductors are overlapped so that they can be electrically connected, the positions of the via conductors are shifted in the vertical direction. May be good.
  • the laminate is preferably fired at a temperature suitable for sintering the low temperature sintered ceramic material, and for example, the firing temperature is preferably 1000 ° C. or lower. Further, it is more preferable that the firing temperature is 850 ° C. or higher and 990 ° C. or lower.
  • the firing time (holding time at the firing temperature) is preferably 10 minutes or more and 30 minutes or less. In addition, you may perform pressure firing which pressurizes and fires a laminated body.
  • the atmosphere at the time of firing is preferably an atmospheric atmosphere.
  • the restraint layer is a slurry obtained by adding and mixing a resin, a dispersant, a plasticizer, and a solvent to ceramic powder, which is a material that is not sintered in the firing step, and is formed into a sheet by a doctor blade method.
  • Alumina powder is preferable as the ceramic powder used for the restraint layer.
  • the thickness of the sheet is preferably 0.2 mm, for example.
  • the low temperature sintered ceramic material and the via conductor are fired at the same time.
  • an insulating layer and a thermal via are formed at the same time.
  • the metal material can be diffused in the insulating layer to form a diffused portion.
  • the difference in the coefficient of thermal expansion near the interface between the thermal via and the insulating layer becomes gentle, so that the strength against thermal stress due to the difference in the coefficient of thermal expansion is improved, and in a high temperature environment (for example, 80 ° C./ Deterioration of the joint portion during holding for 30 minutes) is prevented.
  • circuit board of the present invention and the method for manufacturing the circuit board are more specifically disclosed will be shown.
  • the present invention is not limited to these examples.
  • Example 1 Alumina powder is prepared as a starting material, and SiO 2 is contained in an amount of 59% by weight, B 2 O 3 is contained in 10% by weight, Ca O is contained in 25% by weight, and Al 2 O 3 is contained in a ratio of 6% by weight as glass powder.
  • a borosilicate glass powder having a composition was prepared. This glass powder is a low temperature sintered ceramic material. Then, the above-mentioned alumina powder and glass powder are mixed at a weight ratio of 40:60, and appropriate amounts of binder, dispersant, plasticizer, organic solvent and the like are added to the mixed powder and mixed to obtain a ceramic slurry. Was produced. Next, an appropriate amount of each of a binder, a dispersant, a plasticizer, an organic solvent and the like was added to the alumina powder and mixed to prepare a restraint layer slurry.
  • a ceramic green sheet and a restraint layer sheet having a thickness of 100 ⁇ m were prepared by the doctor blade method, respectively.
  • a 0.05 mm square through hole was formed in a ceramic green sheet having a thickness of 100 ⁇ m by punching so that the top diameter and the bottom diameter were different.
  • the formed through hole was filled with a conductor paste containing silver to form a via conductor.
  • the silver-containing conductor paste contains glass powder, which is a low-temperature sintered ceramic material contained in a ceramic green sheet.
  • the weight ratio of the low temperature sintered ceramic material to the total weight of the metal and the low temperature sintered ceramic material in the conductor paste was 10%.
  • each sheet was laminated according to the following procedure to prepare a laminated body.
  • one restraint layer sheet was laminated on the outermost layer, then 15 ceramic green sheets on which a via conductor was formed were laminated, and then one restraint layer sheet was laminated on the outermost layer.
  • the positions of the via conductors overlapped.
  • the laminated body obtained by the above laminating method was pressed in the thickness direction.
  • the laminated body after the press was fired at 900 ° C. to obtain a circuit board.
  • the low temperature sintered ceramic material and the via conductor were simultaneously fired to form an insulating layer and a thermal via at the same time.
  • the thickness of the insulating layer formed after firing when the thickness was 100 ⁇ m in the state of the ceramic green sheet, the thickness was 50 ⁇ m in the state of the insulating layer.
  • the restraint layers arranged above and below the laminated body were removed by temporarily cleaning with an ultrasonic cleaner and then blasting with a wet blaster.
  • Example 1 A ceramic green sheet and a restraint layer sheet were produced in the same manner as in Example 1. Next, a through hole having the same top surface diameter and bottom surface diameter of 0.05 mm square was formed in a ceramic green sheet having a thickness of 100 ⁇ m by punching.
  • one restraint layer sheet was laminated on the outermost layer, then 15 ceramic green sheets having through holes were laminated, and further, a restraint layer was laminated on the backmost layer. One sheet was laminated. When laminating the ceramic green sheets, the positions of the through holes overlap. Next, the laminated body obtained by the above laminating method was pressed in the thickness direction.
  • Example 2 the laminated body after the press was fired at 900 ° C. Subsequently, the restraint layers arranged above and below the laminated body were removed by temporarily cleaning with an ultrasonic cleaning machine and then performing a blasting treatment with a wet blasting machine.
  • a circuit board was obtained by the above procedure.
  • Nickel / gold plating was performed on the upper surface of the thermal via of the circuit board of Example 1 and the upper surface of the metal plate of the circuit board of Comparative Example 1, respectively. Subsequently, the lead wire was soldered to the nickel / gold plated surface. Subsequently, one end of the lead wire was grasped by a tensile strength measuring device, and the lead wire was pulled up while measuring the load, and the load at the time when the thermal via or the metal plate was removed from the circuit board was measured. The value obtained by dividing this load by the area of the through hole (0.05 mm square) was taken as the joint strength.
  • FIG. 7 is a graph showing the joint strength in Example 1 and Comparative Example 1. As shown in FIG. 7, in the circuit board of Example 1, the bonding strength at room temperature was high, and the decrease in bonding strength was small even after the high temperature treatment.
  • Example 2 A ceramic green sheet and a restraint layer sheet were produced in the same manner as in Example 1. Next, a 4 mm square through hole was formed in a ceramic green sheet having a thickness of 100 ⁇ m by punching so that the top diameter and the bottom diameter were different. The formed through hole was filled with a conductor paste containing copper to form a via conductor.
  • the copper-containing conductor paste contains glass powder, which is a low-temperature sintered ceramic material contained in a ceramic green sheet. The weight ratio of the low temperature sintered ceramic material to the total weight of the metal and the low temperature sintered ceramic material in the conductor paste was 10%.
  • a laminated body was prepared and fired in the same manner as in Example 1 except that the number of ceramic green sheets on which the via conductor was formed was changed to 20, and the restraint layer sheet was removed to obtain a circuit board.
  • Example 2 A ceramic green sheet and a restraint layer sheet were produced in the same manner as in Example 1. Next, eight 0.15 mm ⁇ through holes having the same top surface diameter and bottom surface diameter were drilled in a 4 mm square of a ceramic green sheet having a thickness of 100 ⁇ m at a pitch of 0.2 mm between the through holes. The formed through hole was filled with the same conductor paste as that used in Example 2 to form a via conductor.
  • a 4 mm square via pad was formed by printing on one of the ceramic green sheets.
  • the ceramic green sheet on which the via pad was formed was made to be the uppermost layer, and 19 ceramic green sheets on which the via conductor was formed were used to prepare a laminate.
  • restraint layer sheets were arranged above and below the laminated body. Other than that, the laminate was prepared and fired in the same manner as in Example 1, and the restraint layer sheet was removed to obtain a circuit board.
  • Example 3 A ceramic green sheet and a restraint layer sheet were produced in the same manner as in Example 1. Twenty ceramic green sheets were laminated, and restraint layer sheets were arranged above and below the laminated body to prepare and fire the laminated body. After removing the restraint layer sheet, a 4 mm square through hole having the same top surface diameter and bottom surface diameter was prepared for the insulating layer using a laser processing machine. Next, a copper metal plate having a top view of 4.02 mm square was press-fitted into the through hole. A circuit board was obtained by the above procedure.
  • Comparative Example 4 In Comparative Example 3, the same was applied up to the step of producing the through hole. Instead of the step of press-fitting a copper metal plate into the through hole, a copper metal plate having a top view of 3.9 mm square was inserted into the through hole and bonded to the insulating layer with an adhesive. A circuit board was obtained by the above procedure.
  • Example 3 A ceramic green sheet and a restraint layer sheet were produced in the same manner as in Example 1. Next, a 2 mm square through hole was formed in a ceramic green sheet having a thickness of 100 ⁇ m by punching so that the top diameter and the bottom diameter were different.
  • Silver was used as the metal contained in the conductor paste, and a plurality of types of conductor pastes were prepared in which the weight ratio of the low-temperature sintered ceramic material to the total weight of silver and the low-temperature sintered ceramic material was changed.
  • the weight ratio of the low temperature sintered ceramic material was 0% by weight, 10% by weight, 30% by weight, and 50% by weight. Then, the through hole formed earlier was filled with a conductor paste containing silver to form a via conductor.
  • a laminated body was produced and fired in the same manner as in Example 1 except that the number of ceramic green sheets on which the via conductor was formed was changed to 20, and the restraint layer sheet was removed to obtain a circuit board.
  • the 20 ceramic green sheets constituting the same laminate those in which the via conductor was formed by using the same conductor paste were used.
  • Example 5 A ceramic green sheet and a restraint layer sheet were produced in the same manner as in Example 1. Next, a 2 mm square through hole having the same top surface diameter and bottom surface diameter was formed in a ceramic green sheet having a thickness of 100 ⁇ m by punching.
  • a plurality of types of conductor sheets having a top view of 2.02 mm square and a thickness of 50 ⁇ m were prepared in which the weight ratio of the low temperature sintered ceramic material to the total weight of silver and the low temperature sintered ceramic material was changed.
  • the weight ratio of the low temperature sintered ceramic material was 0% by weight, 10% by weight, 30% by weight, and 50% by weight. Then, a conductor sheet was press-fitted into the through hole formed earlier to form a via conductor.
  • a laminated body was produced and fired in the same manner as in Example 1 except that the number of ceramic green sheets on which the via conductor was formed was changed to 20, and the restraint layer sheet was removed to obtain a circuit board.
  • the 20 ceramic green sheets constituting the same laminated body those in which the via conductor was formed by using the same conductor sheet were used.
  • Nickel / gold plating was performed on the upper surface of the thermal via of each circuit board of Example 3 and the upper surface of the conductor sheet of each circuit board of Comparative Example 5. Subsequently, the lead wire was soldered to the nickel / gold plated surface. Subsequently, one end of the lead wire was grasped by a tensile strength measuring device, the lead wire was pulled up while measuring the load, and the load at the time when the thermal via or the conductor sheet was removed from the circuit board was measured. The value obtained by dividing this load by the area of the through hole (2 mm square) was taken as the joint strength.
  • the joint strength evaluation test was conducted as an initial evaluation before the cycle test and as an evaluation after the cycle test (-40 ° C to 125 ° C, 1000 cycles), and the results are summarized in Table 2.
  • the circuit board of Example 3 has a high initial bonding strength, and the bonding strength is maintained high even after the cycle test. Further, the bonding strength is higher when the low-temperature sintered ceramic material is included than when the weight ratio of the low-temperature sintered ceramic material is 0%. This is because the taper conductor contains a low-temperature sintered ceramic material that constitutes the insulating layer, so that the difference in the coefficient of thermal expansion between the insulating layer around the thermal via and the tapered conductor is reduced, and the bonding strength between the thermal via and the insulating layer is improved. It supports what you do. It can also be seen that it is more preferable that the weight ratio of the low-temperature sintered ceramic material is 10% or more in order to improve the bonding strength between the thermal via and the insulating layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
PCT/JP2020/037876 2019-11-14 2020-10-06 回路基板及び回路基板の製造方法 Ceased WO2021095401A1 (ja)

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DE112020004962.0T DE112020004962T5 (de) 2019-11-14 2020-10-06 Leiterplatte und verfahren zur herstellung einer leiterplatte
CN202080078909.2A CN114747301B (zh) 2019-11-14 2020-10-06 电路基板以及电路基板的制造方法
JP2021555946A JP7243856B2 (ja) 2019-11-14 2020-10-06 回路基板及び回路基板の製造方法
US17/741,906 US12133328B2 (en) 2019-11-14 2022-05-11 Circuit board and method for producing circuit board

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Publication number Priority date Publication date Assignee Title
US20240072459A1 (en) * 2022-08-31 2024-02-29 Innolux Corporation Electrical connection structure and electronic device
WO2025173541A1 (ja) * 2024-02-13 2025-08-21 株式会社村田製作所 回路基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6196548U (https=) * 1984-11-30 1986-06-21
JPH0714421A (ja) * 1993-06-23 1995-01-17 Murata Mfg Co Ltd バイアホール用導電性ペーストおよびそれを用いた多層セラミック基板
JP2010171157A (ja) * 2009-01-22 2010-08-05 Sanyo Electric Co Ltd 電子素子用パッケージ及び電子部品

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5386339A (en) 1993-07-29 1995-01-31 Hughes Aircraft Company Monolithic microelectronic circuit package including low-temperature-cofired-ceramic (LTCC) tape dielectric structure and in-situ heat sink
US6187418B1 (en) * 1999-07-19 2001-02-13 International Business Machines Corporation Multilayer ceramic substrate with anchored pad
JP2002234781A (ja) 2001-02-06 2002-08-23 Murata Mfg Co Ltd 銅メタライズ組成物ならびにそれを用いたセラミック配線基板およびその製造方法
JP2005026368A (ja) * 2003-06-30 2005-01-27 Tdk Corp 放熱用ビアホールを備えた積層基板および該基板を用いたパワーアンプモジュール
US20070040245A1 (en) * 2003-11-17 2007-02-22 Jsr Corporation Anisotropic conductive sheet, manufacturing method thereof, and product using the same
JP4780939B2 (ja) 2004-07-28 2011-09-28 京セラ株式会社 発光装置
JP4493399B2 (ja) 2004-05-19 2010-06-30 京セラ株式会社 複合シート及び積層部品の製造方法
JP4748161B2 (ja) 2005-07-12 2011-08-17 株式会社村田製作所 多層配線基板及びその製造方法
TW200733143A (en) * 2006-01-23 2007-09-01 Hitachi Metals Ltd Conductor paste, multilayer ceramic substrate and fabrication method of multilayer ceramic substrate
JP2007208193A (ja) 2006-02-06 2007-08-16 Alps Electric Co Ltd セラミック基板
JP2008186919A (ja) 2007-01-29 2008-08-14 Alps Electric Co Ltd 積層セラミック配線板
JP4573185B2 (ja) * 2007-10-18 2010-11-04 日立金属株式会社 セラミック積層基板ならびにセラミック積層電子部品の製造方法
JP5024348B2 (ja) * 2009-03-23 2012-09-12 株式会社デンソー 基板の表面に樹脂絶縁膜のパターンを形成する方法及び半導体装置
US8563873B2 (en) * 2009-03-31 2013-10-22 Ibiden Co., Ltd. Substrate with metal film and method for manufacturing the same
CN104053302B (zh) * 2009-06-11 2017-08-29 罗杰斯公司 介电材料、由其形成子组件的方法以及由此形成的子组件
KR20110036149A (ko) * 2009-10-01 2011-04-07 삼성전기주식회사 다층 세라믹 기판 및 그 제조 방법
JP2012009609A (ja) * 2010-06-24 2012-01-12 Jtekt Corp 多層回路基板
JP2015038910A (ja) * 2012-07-13 2015-02-26 イビデン株式会社 配線板及びその製造方法
JP2015038909A (ja) * 2012-07-13 2015-02-26 イビデン株式会社 配線板及びその製造方法
JP6252000B2 (ja) * 2013-07-09 2017-12-27 三菱電機株式会社 基板
JP5999063B2 (ja) * 2013-10-08 2016-09-28 株式会社村田製作所 セラミック多層基板
WO2017047647A1 (ja) 2015-09-18 2017-03-23 株式会社村田製作所 セラミック多層基板
CN208597204U (zh) * 2016-01-07 2019-03-12 株式会社村田制作所 多层基板以及电子设备

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6196548U (https=) * 1984-11-30 1986-06-21
JPH0714421A (ja) * 1993-06-23 1995-01-17 Murata Mfg Co Ltd バイアホール用導電性ペーストおよびそれを用いた多層セラミック基板
JP2010171157A (ja) * 2009-01-22 2010-08-05 Sanyo Electric Co Ltd 電子素子用パッケージ及び電子部品

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US20220272837A1 (en) 2022-08-25
DE112020004962T5 (de) 2022-06-30

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