WO2021095251A1 - ストレージデバイスおよび制御方法 - Google Patents

ストレージデバイスおよび制御方法 Download PDF

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Publication number
WO2021095251A1
WO2021095251A1 PCT/JP2019/044931 JP2019044931W WO2021095251A1 WO 2021095251 A1 WO2021095251 A1 WO 2021095251A1 JP 2019044931 W JP2019044931 W JP 2019044931W WO 2021095251 A1 WO2021095251 A1 WO 2021095251A1
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WO
WIPO (PCT)
Prior art keywords
temperature
semiconductor wafer
prober
storage device
temperature control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2019/044931
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English (en)
French (fr)
Japanese (ja)
Inventor
康人 吉水
崇 福島
達郎 人見
新 井上
三浦　正幸
菅野　伸一
俊雄 藤澤
圭祐 中塚
朋也 佐貫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Priority to CN201980100500.3A priority Critical patent/CN114424331B/zh
Priority to PCT/JP2019/044931 priority patent/WO2021095251A1/ja
Priority to EP19952453.9A priority patent/EP4060721A4/en
Priority to JP2021555761A priority patent/JP7293389B2/ja
Priority to TW111115173A priority patent/TWI800355B/zh
Priority to TW109127283A priority patent/TWI765316B/zh
Publication of WO2021095251A1 publication Critical patent/WO2021095251A1/ja
Priority to US17/694,532 priority patent/US12384624B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433—Sockets for IC's or transistors
    • G01R1/0441—Details
    • G01R1/0458—Details related to environmental aspects, e.g. temperature
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65G—TRANSPORT OR STORAGE DEVICES, e.g. CONVEYORS FOR LOADING OR TIPPING, SHOP CONVEYOR SYSTEMS OR PNEUMATIC TUBE CONVEYORS
    • B65G1/00—Storing articles, individually or in orderly arrangement, in warehouses or magazines
    • B65G1/02—Storage devices
    • B65G1/04—Storage devices mechanical
    • B65G1/137—Storage devices mechanical with arrangements or automatic control means for selecting which articles are to be removed
    • B65G1/1373—Storage devices mechanical with arrangements or automatic control means for selecting which articles are to be removed for fulfilling orders in warehouses
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2865—Holding devices, e.g. chucks; Handlers or transport devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2893—Handling, conveying or loading, e.g. belts, boats, vacuum fingers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0434—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0602—Temperature monitoring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0403—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals during or with feedback to manufacture
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Definitions

  • Embodiments of the present invention relate to storage devices and control methods.
  • SSD solid state drive
  • HDD hard disk drive
  • a probe card is used as an inspection jig for relaying an electric signal between a semiconductor wafer on which a semiconductor chip is formed and an inspection device for inspecting the semiconductor chip.
  • the probe card is simply composed of a printed circuit board PCB and a probe. The prober brings the pad electrode formed on the semiconductor wafer into contact with the probe of the probe card to electrically connect the device on the printed circuit board PCB and the semiconductor wafer, for example.
  • One of the embodiments provides a storage device and a control method capable of appropriately performing various temperature controls on a semiconductor wafer including a plurality of non-volatile memory chips.
  • the storage device includes a prober and a stocker.
  • the prober writes data to or reads data from the semiconductor wafer storage, which includes a plurality of non-volatile memory chips.
  • the stocker stores a plurality of the semiconductor wafers in a state of being pulled out from the prober.
  • the prober has a first temperature control mechanism.
  • the first temperature control mechanism raises the temperature of the semiconductor wafer to the first temperature or higher.
  • the stocker has a second temperature control mechanism.
  • the second temperature control mechanism cools the semiconductor wafer to a second temperature or lower, which is lower than the first temperature.
  • FIG. 1 is a diagram showing a configuration example of a storage device of the embodiment.
  • FIG. 2 is a diagram showing a state in which the probe of the probe card is in contact with the pad electrode formed on the wafer in the storage device of the embodiment.
  • FIG. 3 is a block diagram schematically showing the storage device of the embodiment.
  • FIG. 4 is a diagram for explaining an example of setting a temperature control region for a stage in the storage device of the embodiment.
  • FIG. 5 is a diagram showing a configuration example of a heating / cooling mechanism provided in the stage of the storage device of the embodiment.
  • FIG. 6 is a diagram showing an example of arrangement of a heating / cooling mechanism in the stage of the storage device of the embodiment.
  • FIG. 1 is a diagram showing a configuration example of a storage device of the embodiment.
  • FIG. 2 is a diagram showing a state in which the probe of the probe card is in contact with the pad electrode formed on the wafer in the storage device of the embodiment.
  • FIG. 3 is a block
  • FIG. 7 is a diagram for explaining an example of temperature control by a heating / cooling mechanism provided on a stage in the storage device of the embodiment.
  • FIG. 8 is a diagram for explaining an example of a mechanism in which the device on the probe card centrally controls the temperature of the prober in the storage device of the embodiment.
  • FIG. 9 is a diagram showing a plurality of probes arranged on the first surface of a probe card in the storage device of the embodiment.
  • FIG. 10 is a diagram showing a plurality of controllers arranged on the second surface of the probe card in the storage device of the embodiment.
  • FIG. 11 is a diagram for explaining an operation example of a device mounted on a prober in the storage device of the embodiment.
  • FIG. 12 is a diagram showing a first example of a cooling mechanism provided in the stocker in the storage device of the embodiment.
  • FIG. 13 is a diagram showing a second example of a cooling mechanism provided in the stocker in the storage device of the embodiment.
  • FIG. 14 is a flowchart showing an example of the flow of temperature control at the time of wafer replacement executed by the storage device of the embodiment.
  • FIG. 1 is a diagram showing a configuration example of the storage device 1 of the present embodiment.
  • a probe card which is an inspection jig, is diverted to construct a large-capacity storage device 1 in units of semiconductor wafers without dicing. Furthermore, it is assumed that a storage device 1 having a larger capacity is constructed by mounting a plurality of semiconductor wafers so that the semiconductor wafers electrically connected to the probe can be replaced.
  • the semiconductor wafer in the prober has a high temperature of room temperature or higher and the temperature is kept uniform in the semiconductor wafer, while the semiconductor wafer stored outside the blower is at room temperature or lower. It is preferable to keep it at a low temperature.
  • the storage device 1 has a reader & writer (prober) 100, a storage transfer system 200, and a stocker 300.
  • FIG. 1 shows an example in which two probers 100 are provided, but the number of probers 100 is not limited to this, and the number of probers 100 can be changed in various ways.
  • the storage device 1 includes an air conditioning control mechanism 500 for replacing the gas phase atmosphere in the prober 100, the storage transfer system 200, and the stocker 300 with dry air, noble gas, inert gas, etc. that do not contain water. Have.
  • the storage device 1 mounts a semiconductor wafer (wafer 400) on which a plurality of NAND flash memory chips (NAND chips) are formed as storage. Further, the storage device 1 mounts a plurality of wafers 400, and appropriately selects and uses a predetermined number of wafers 400 (two wafers 400 in the case of the example of FIG. 1) from the plurality of wafers 400. Specifically, the storage device 1 can replace the wafer 400 in the prober 100 with the wafer 400 in the stocker 300.
  • wafer 400 semiconductor wafer
  • NAND chips NAND flash memory chips
  • the prober 100 has a probe card 110, a stage 120, and a drive unit 130.
  • the probe card 110 is a unit that electrically connects to the wafer 400 on the stage 120. As described above, the probe card 110 is composed of a printed circuit board PCB and a probe in a simplified manner. In the storage device 1 of the present embodiment, a controller that controls writing data to the NAND chip formed on the wafer 400 and reading data from the NAND chip is used as the device 111 on the printed circuit board PCB of the probe card 110. Be placed. Further, in the storage device 1 of the present embodiment, a temperature control mechanism (heating / cooling mechanism 112, cooling mechanism 113, heat insulating material 114) is provided in the probe card 110. The temperature control mechanism provided in the probe card 110 will be described later.
  • the stage 120 is a unit that holds the wafer 400.
  • a temperature control mechanism (heating / cooling mechanism 121) is also provided in the stage 120.
  • the temperature control mechanism provided in the stage 120 will also be described later.
  • the drive unit 130 is a unit that moves the stage 120 to bring the probe of the probe card 110 into contact with the pad electrode formed on the wafer 400.
  • the drive unit 130 is assumed to move the stage 120, but may move the probe card 110. Further, the drive unit 130 may move both the probe card 110 and the stage 120.
  • the drive unit 130 can also move the stage 120 so as to pull the probe in contact with the pad electrode away from the pad electrode.
  • FIG. 2 shows a state in which the probe 115 of the probe card 110 is in contact with the pad electrode 410 formed on the wafer 400 by the drive unit 130.
  • a controller arranged as one of the devices 111 on the printed circuit board PCB of the probe card 110 is electrically connected to the NAND chip formed on the wafer 400.
  • the controller can control writing data to the NAND chip, reading data from the NAND chip, and erasing data in the NAND chip.
  • the storage transfer system 200 has a storage transfer machine 210.
  • the storage transfer machine 210 transfers the wafer 400, which is the storage in the storage device 1 of the present embodiment, from the stocker 300 to the prober 100, or from the prober 100 to the stocker 300.
  • the configuration described below is an example, and the means for transporting the wafer 400 is not limited to this.
  • the storage carrier 210 is movable in the vertical direction and the horizontal direction.
  • the storage carrier 210 has a support 211 that is rotatable about the vertical direction and, for example, an elongated plate-like shape, and the other end is a support so that one end in the longitudinal direction protrudes in the horizontal direction. It is composed of a tray 212 supported by 211.
  • the storage transfer machine 210 When replacing the wafer 400 in the stocker 300, the storage transfer machine 210 first performs an operation for transferring the wafer 400 from the prober 100 to the stocker 300. Specifically, (1) the height of the tray 212 is moved vertically so as to be a suitable height for taking out the wafer 400 in the prober 100, and (2) the tray 212 is rotated so as to face the prober 100 side. Dynamic, (3) move horizontally to the prober 100 side to hold the wafer 400 in the prober 100 on the tray 212, (4) move horizontally to the opposite side of the prober 100 to remove the wafer 400 from inside the prober 100.
  • the storage transfer machine 210 secondly performs an operation for transferring the wafer 400 from the stocker 300 to the prober 100. Since this procedure is similar to the operation for transferring the wafer 400 from the prober 100 to the stocker 300, the description thereof will be omitted.
  • the stocker 300 stores a plurality of wafers 400 in a state of being removed from the prober 100.
  • a temperature control mechanism (cooling mechanism 310) is also provided in the stocker 300. The temperature control mechanism provided in the stocker 300 will be described later.
  • the air conditioning control mechanism 500 separates the space from the outside air and inflows dry air, noble gas, inert gas, etc. that does not contain water into the decompressed space by taking in air from the outside with an exhaust fan. It has a structure that replaces the inside of the space with dry air, noble gas, inert gas, etc. The reason why the air conditioning control mechanism 500 replaces the gas phase atmosphere in the prober 100, the storage transfer system 200, and the stocker 300 with water-free dry air, a rare gas, an inert gas, or the like will be described later.
  • FIG. 3 is a block diagram schematically showing a storage device 1 composed of a prober 100, a storage transfer system 200, and a stocker 300 described with reference to FIG.
  • the controller 111-1 that controls the writing of data to the NAND chip formed on the wafer 400 and the reading of data from the NAND chip prints the probe card 110. It is arranged as one of the devices 111 on the substrate PCB. A plurality of controllers 111-1 may be arranged. That is, all the NAND chips on the wafer 400 may be controlled by one controller 111-1 or may be controlled by a plurality of controllers 111-1.
  • a buffer memory 111-2 for temporarily storing write data and read data is arranged as one of the devices 111 on the printed circuit board PCB of the probe card 110 like the controller 111-1. Is shown.
  • the buffer memory 111-2 may be built in the controller 111-1.
  • the controller 111-1 is electrically connected to the NAND chip of the wafer 400 when the probe 115 of the probe card 110 comes into contact with the pad electrode 410 of the wafer 400 on the stage 120.
  • the controller 111-1 can control the writing of data to the NAND chip and the reading of data from the NAND chip in response to the request from the host 2. Further, the wafer 400 in the prober 100 can be replaced with the wafer 400 stored in the stocker 300 by the storage transfer system 200.
  • the storage device 1 has a control unit 10.
  • the control unit 10 includes, for example, an air conditioning control system 11, a temperature control system 12, a drive control system 13, and an interface control system 14, and controls the entire operation of the storage device 1.
  • Each control system of the control unit 10 is realized, for example, by the processor executing the firmware.
  • the air conditioning control system 11 controls the air conditioning control mechanism 500.
  • the temperature control system 12 includes a temperature control mechanism (heating / cooling mechanism 112, cooling mechanism 113) in the probe card 110, a temperature control mechanism (heating / cooling mechanism 121) in the stage 120, and a temperature control mechanism (cooling mechanism 310) in the stocker 300. ) Is controlled in an integrated manner.
  • the drive control system 13 controls the drive unit 130 and the storage carrier 210.
  • the interface control system 14 controls communication between the host 2 and the probe card 11. Further, the interface control system 14 controls the air conditioning control system 11, the temperature control system 12, and the drive control system 13 based on the control result of the communication.
  • the charge retention time can be lengthened by suppressing phonon scattering of the charge stored in the NAND chip. Therefore, the temperature at which the wafer 400 is stored is preferably low. Further, it is preferable that the device 111 mounted on the probe card 110 is operated at a temperature equal to or lower than the threshold value. As described above, when the wafer 400 is used as the storage, various temperature controls are required in the storage device 1. Therefore, in the storage device 1 of the present embodiment, temperature control mechanisms are provided in the prober 100, the storage transfer system 200, and the stocker 300, respectively, so that the storage device 1 as a whole performs appropriate temperature control. This point will be described in detail below.
  • temperature control mechanisms are provided in the probe card 110 and in the stage 120.
  • a heating / cooling mechanism 121 is provided inside the stage 120 that holds the wafer 400 to keep the temperature inside the wafer 400 electrically connected to the probe card 110 on the stage 120 as much as possible (see FIG. 1).
  • the heating / cooling mechanism 121 is, for example, a temperature control mechanism using electric heating and a cooling pipe.
  • the storage device 1 sets a temperature control region for each of a plurality of different regions having a smaller area than the wafer 400, for example, for each NAND chip region in the wafer 400, and each of them is different. The temperature can be controlled.
  • FIG. 4 is a diagram for explaining an example of setting a temperature control region related to the stage 120 in the storage device 1 of the present embodiment.
  • FIG. 4A shows the upper surface of the wafer 400 and shows an example of forming a NAND chip 420 in the wafer 400.
  • FIG. 4B shows the upper surface of the stage 120 holding the wafer 400, and shows an example of setting the temperature control region a1 related to the stage 120.
  • the storage device 1 of the present embodiment there is a one-to-one positional correspondence with a plurality of NAND chips 420 formed on the wafer 400 placed on the stage 120.
  • a plurality of temperature control regions a1 are set on the stage 120.
  • the plurality of temperature control regions a1 can be set so that one corresponds to two or more NAND chips 420 in position, for example. Further, the number of NAND chips 420 to which the temperature control region a1 is associated does not have to be the same in all the temperature control regions a1.
  • FIG. 5 is a diagram showing a configuration example of a heating / cooling mechanism 121 provided in the stage 120 for performing temperature control for each temperature control region a1 set as shown in FIG. 4, for example.
  • the cooling mechanism of the heating / cooling mechanism 121 has, for example, a structure in which the refrigerant b1 is circulated from one of the two cooling pipes 1211 to the other via the cooling branch pipe 1212.
  • the refrigerant b1 is water cooled by electronic cooling, liquid nitrogen, or the like.
  • the cooling branch pipe 1212 is arranged so that the wafer 400 on the stage 120 can be cooled in each temperature control region a1 set on the stage 120.
  • the cooling by the cooling branch pipe 1212 is controlled by the inflow amount of the refrigerant b1.
  • an electronically controlled motor valve 1213 and a flow meter 1214 are installed near the injection port of the cooling branch pipe 1212, for example.
  • the heating mechanism of the heating / cooling mechanism 121 is configured by using, for example, a heater wire 1215 arranged so that the wafer 400 on the stage 120 can be heated for each temperature control region a1 set on the stage 120. Heating by the heater wire 1215 can be controlled by, for example, a switch for switching the presence or absence of heating and a variable resistor for adjusting the amount of heat generated.
  • thermometer is provided which can output the temperature data for example I 2 C bus. Further, a thermometer may be provided in the wafer 400 as well.
  • a communication path capable of transferring the temperature measured by the thermometer provided in the stage 120 or the wafer 400 to the controller 111-1 is provided.
  • the controller 111-1 controls the heating / cooling mechanism 121 of the stage 120 based on the temperature measured by the thermometer provided in the stage 120 or the wafer 400.
  • the controller 111-1 also executes the control of the temperature control mechanism (heating / cooling mechanism 112, cooling mechanism 113) provided in the probe card 110, which will be described later.
  • the temperature control mechanism in the prober 100 is centrally controlled by the controller 111-1. It is also possible to prepare a device for centrally controlling the temperature control mechanism in the prober 100 separately from the controller 111-1 and arrange it on the probe card 110. Alternatively, an existing device other than the controller 111-1 may be equipped with a function for centrally controlling the temperature control mechanism in the prober 100.
  • FIG. 5 also shows the lift pin 131 of the drive unit 130 and the actuator 132.
  • the lift pin 131 is a member that is fitted into a hole provided in the stage 120 to move the stage 120 in the vertical direction or the horizontal direction.
  • the actuator 132 can move the stage 120 vertically or horizontally by moving the lift pin 131 vertically or horizontally.
  • the horizontal movement is performed to align the pad electrode 410 of the wafer 400 with the probe 115 of the probe card 110.
  • the vertical movement is performed to bring the pad electrode 410 of the wafer 400 into contact with the probe 115 of the probe card 110, or to separate the pad electrode 410 and the probe 115 in the contact state.
  • FIG. 6 is a diagram showing an example of arrangement of the heating / cooling mechanism 121 configured as shown in FIG. 5 in the stage 120.
  • FIG. 6A shows the upper surface of the wafer 400 and shows an example of forming the NAND chip 420 in the wafer 400.
  • FIG. 6B shows the upper surface of the stage 120 holding the wafer 400, and shows an example of arrangement of the heating / cooling mechanism 121 in the stage 120.
  • the cooling branch pipe 1212 for cooling and the heater wire 1215 for heating included in the heating / cooling mechanism 121 do not necessarily pass through all the temperature control regions a1. It does not have to be arranged so that it does. For example, it is possible to control the temperature of the target temperature control region a1 by using one or more cooling branch pipes 1212 or one or more heater wires 1215 in the vicinity.
  • FIG. 7 is a diagram for explaining an example of temperature control by the heating / cooling mechanism 121 provided on the stage 120.
  • FIG. 7A shows an example in which the temperature inside the wafer 400 on the stage 120 is non-uniform. Specifically, the wafer 400 shows a state in which the temperature at the central portion is high and the temperature is low from the central portion to the end portion.
  • FIG. 7B shows an example of temperature control by the heating / cooling mechanism 121 implemented when the wafer 400 is in the state shown in FIG. 7A.
  • the central portion of the wafer 400 is cooled by flowing the refrigerant b1 through the cooling branch pipe 1212 arranged in the central portion, and the end portion of the wafer 400 is cooled to the end portion. Heating is performed to heat the arranged heater wire 1215.
  • the flow rate of the refrigerant b1 to the cooling branch pipe 1212 is controlled so as to be larger toward the center and smaller toward the center, and conversely, the calorific value of the heater wire 1215 is smaller toward the center and from the center. It is controlled so that it becomes larger as the distance increases.
  • the temperature inside the wafer 400 on the stage 120 can be controlled to be uniform.
  • the temperature at the center of the wafer 400 has risen and the temperature inside the wafer 400 has become non-uniform.
  • the temperature inside the wafer 400 has become non-uniform.
  • the cooling mechanism 310 of the stocker 300 will be described later, but the wafer 400 stored in the stocker 300 is cooled to a low temperature of room temperature or lower, which is suitable for long-term storage of data.
  • writing data to the NAND chip 420 and reading data from the NAND chip 420 are preferably performed at a high temperature of room temperature or higher.
  • the low-temperature wafer 400 conveyed from the stocker 300 is electrically connected to the probe card 110 when the wafer 400 in the prober 100 is replaced.
  • the temperature can be raised to a temperature suitable for writing data to the NAND chip 420 and reading data from the NAND chip 420. Further, it is possible to prevent damage to both the probe 150 of the probe card 110 and the pad electrode 410 of the wafer 400 at the time of contact.
  • the wafer 400 on the stage 120 maintained at room temperature or higher is probed. After being electrically cut from the card 110 and before being transported to the stocker 300, it is also possible to cool the card 110 below room temperature, for example, on the stage 120.
  • the wafer 400 cooled on the stage 120 in the stocker 300 it is possible to prevent the temperature in the stocker 300 from rising even temporarily and affecting other wafers 400 in the stocker 300.
  • a cooling mechanism for cooling the wafer 400 maintained at room temperature or higher on the stage 120 of the prober 100 to room temperature or lower is provided in the storage transfer system 200 interposed between the prober 100 and the stocker 300. Good.
  • a heating / cooling mechanism 112 As the temperature control mechanism in the probe card 110, a heating / cooling mechanism 112, a cooling mechanism 113, and a heat insulating material 114 are provided (see FIG. 1).
  • the heating / cooling mechanism 112 is, for example, a temperature control mechanism using an electric heating and a cooling pipe similar to the heating / cooling mechanism 121 of the stage 120. Since it may be the same as the heating / cooling mechanism 121 of the stage 120, the description of its configuration will be omitted. The configuration may be different from that of the heating / cooling mechanism 121 of the stage 120.
  • the heating / cooling mechanism 112 makes the temperature of the probe card 110 substantially match the temperature of the wafer 400, more specifically, the temperature of the probe 115 substantially matches the temperature of the pad electrode 410, so that the wafer 400 on the stage 120 It is provided, for example, on the lower surface side in the probe card 110 facing the probe card 110.
  • the storage device 1 of the present embodiment can stabilize the electrical connection between the wafer 400 and the probe card 110 by bringing the probe 115 into contact with the pad electrode 410.
  • the cooling mechanism 113 of the probe card 110 is, for example, a temperature control mechanism using heat dissipation or a cooling pipe.
  • the cooling mechanism 113 operates the device 111 arranged on the printed circuit board PCB of the probe card 110 at a temperature below the threshold value.
  • the probe card It is provided on the upper surface side of the 110, for example.
  • the control of the cooling mechanism 113 is executed by the controller 111-1, which is one of the devices 111.
  • the controller 111-1 controls the cooling mechanism 113 based on the temperature of the controller 111-1 measured by itself and the temperature measured by another device on the printed circuit board PCB.
  • the cooling mechanism 113 can also perform temperature control for each preset temperature control region.
  • This temperature control area may correspond to the temperature control area a1 set on the stage 120, or may be set independently.
  • the storage device 1 of the present embodiment can continue to operate the device 111 arranged on the probe card 110 under an appropriate environment.
  • the probe card 110 is provided with a heat insulating material 114 having a high thermal resistance between, for example, the upper surface on which the device 111 is arranged and the lower surface, for example, facing the wafer 400.
  • the storage device 1 of the present embodiment can insulate the inside of the probe card 110 on the upper surface side and the lower surface side, and can maintain different temperatures. More specifically, for example, the upper surface side can be maintained at a temperature suitable for the device 111, and the lower surface side, for example, can be maintained at a temperature substantially equal to the temperature of the wafer 400 on the stage 120.
  • FIG. 8 is a diagram for explaining an example of a mechanism in which the device 111 (controller 111-1) on the probe card 110 centrally controls the temperature of the prober 100 in the storage device 1.
  • the probe card 110 is provided with a ceramic printed circuit board PCB 1101 having a high heat dissipation effect.
  • Some of the plurality of devices 111 arranged on, for example, the upper surface of the ceramic printed circuit board PCB 1101 include a thermometer 1111 for measuring the temperature of the device 111.
  • the controller 111-1 also includes a thermometer 1111.
  • the controller 111-1 is temperature-controlled by the cooling mechanism 113 so as to keep the temperature of the device 111 below the threshold value based on the temperature measured by these thermometers 1111 including the thermometer 1111 provided therein.
  • the controller 111-1 can execute the temperature control by the cooling mechanism 113 for each preset temperature control region.
  • the thermometer 1111 that measures the temperature of the device 111 may be outside the device 111.
  • the probe unit 1103 is arranged on, for example, the lower surface of the ceramic printed circuit board PCB 1101 via the interposer 1102.
  • the probe 115 is provided at the tip of the probe unit 1103. Further, on the lower surface side thereof, for example, a thermometer 1104 capable of outputting temperature data to the controller 111-1 is provided.
  • thermometers (430, 1201) are provided in at least one of the wafer 400 and the stage 120.
  • the controller 111-1 is provided in the temperature measured by the thermometer 1104 provided in the probe card 110, the temperature measured by the thermometer 430 provided in the wafer 400, or in the stage 120. Temperature control by the heating / cooling mechanism 112 of the probe card 110 and the heating / cooling mechanism 121 of the stage 120 so that the temperature of the probe 115 and the temperature of the pad electrode 410 substantially match based on the temperature measured by the thermometer 1201.
  • the controller 111-1 executes temperature control by the heating / cooling mechanism 121 of the stage 120 so that the temperature inside the wafer 400 becomes uniform.
  • the device 111 arranged on the probe card 110 can monitor the temperatures of the probe card 110, the stage 120, and the wafer 400 on the stage 120 at a plurality of locations.
  • the formation on the wafer 400 which is indicated by reference numeral c1, is an alignment mark used for aligning the probe 115 of the probe card 110 with respect to the pad electrode 410.
  • the X direction is the direction of the word line
  • the Y direction is the direction of the bit line.
  • the horizontal movement of the stage 120 holding the wafer 400 by the drive unit 130 is carried out with reference to the alignment mark c1.
  • the probe card 110 may be provided with a camera for detecting a representative position (here, alignment mark c1) on the wafer 400.
  • the drive control system 13 can more accurately recognize the reference position based on the information from the camera, and can perform precise alignment.
  • FIG. 9 is a diagram showing a plurality of probes 115 arranged on the first surface 110A of the probe card 110.
  • FIG. 9 illustrates a case where the same number of probes 115 as the number of pad electrodes 410 of all the NAND chips 420 of the wafer 400 are arranged on the first surface 110A of the probe card 110.
  • the probe 115 of the probe card 110 is collectively contacted with all the pad electrodes 410 of all the NAND chips 420 in the wafer 400, and all the NAND chips 420 can be controlled by the controller 111-1. ..
  • FIG. 10 is a diagram showing a plurality of controllers 111-1 arranged on the second surface 110B of the probe card 110.
  • controllers 111-1 (controllers 111-1-1, 111-1-2, ..., 1111-1-16) are arranged is illustrated.
  • one wafer 400 contains 1024 NAND chips 420 and 16 controllers 111-1 are arranged on the second surface 110B of the probe card 110, each controller 111-1 The 64 NAND chips 420 may be controlled via the probe 115.
  • FIG. 11 is a diagram for explaining an operation example of the device 111 mounted on the prober 100.
  • a connector 111-3 into which the riser cable 111A for connecting the probe card 110 to the outside such as the host 2 (see FIG. 3) is inserted is arranged on the probe card 110.
  • An interface switch for example, a PCIe (registered trademark) switch) 111-4 for exclusively and selectively connecting the connector 111-3 and one controller 111-1 among the plurality of controllers 111-1 is provided on the probe card 110. Be placed.
  • the interface switch 111-4 appropriately switches, for example, when a data read request is made from the host 2, the data read request is transmitted to the controller 111-1 that controls the corresponding NAND chip 420.
  • the controller 111-1 executes reading of data from the NAND chip 420 and transmits the read data to the host 2.
  • the data transmitted from the controller 111-1 is relayed to the connector 111-3 by the interface switch 111-4 and transferred to the host 2 via the riser cable 111A.
  • the temperatures of the plurality of devices 111 arranged on the probe card 110 are maintained below the threshold value by the cooling mechanism 113 of the probe card 110.
  • various LSI chips and semiconductor components such as FPGAs, relays, and capacitors can be mounted on the prober 100.
  • FIG. 12 is a diagram showing a first example of the cooling mechanism 310.
  • the stocker 300 is provided with shutters 301 that are opened and closed when the wafer 400 is taken in and out, as many as the number of wafers 400 that can be stored.
  • any shutter 301 in the plurality of shutters 301 is selectively opened and closed so as not to let the cold air in the stocker 300 escape to the outside. It is supposed to be done.
  • the shutter 301 may be used as one, and the entire storage (wafer 400) stock stored inside may be moved up and down inside.
  • the stocker 300 is provided with an intake port 311 for sending the cooling air d1 and an exhaust port 312 for discharging the cooling air d2 flowing through the stocker 300.
  • the cooling air d1 is, for example, air cooled at a high pressure.
  • the cooling mechanism 310 of the stocker 300 in this example closes the entrance and exit of the wafer 400 by the shutter 301, continues to send the cooling air d1 from the intake port 311 and fills the inside of the stocker 300 with the cooling air d1 kept below room temperature.
  • the entire stocker 300 is cooled. That is, the wafer 400 in the stocker 300 is cooled so that the temperature is suitable for long-term storage of data.
  • FIG. 13 is a diagram showing a second example of the cooling mechanism 310.
  • the cooling pipe 313 through which the refrigerant e1 flows is provided on the side wall of the stocker 300 so as to cover the entire side surface of the stocker 300, for example.
  • the refrigerant e1 is water cooled by electronic cooling, liquid nitrogen, or the like.
  • the cooling mechanism 310 of the stocker 300 in this example closes the entrance and exit of the wafer 400 by the shutter 301, circulates the refrigerant e1 through the cooling pipe 313 provided on the peripheral wall of the stocker 300, and cools the air in the stocker 300 to cool the stocker. Cool the entire 300. That is, the wafer 400 in the stocker 300 is cooled so that the temperature is suitable for long-term storage of data.
  • the cooling pipe 313 may be inside the stocker 300.
  • the portion of the stocker 300 that supports the wafer 400, the portion that is connected to the support portion, or the entire stocker 300 is electronically cooled by using a Peltier element.
  • a mechanism may be provided to cool the wafer 400 in the stocker 300.
  • the wafer 400 can be stored in the stocker 300 while maintaining a low temperature of room temperature or lower suitable for long-term storage of data. is there.
  • the wafer 400 in the stocker 300 is cooled to a low temperature of room temperature or lower. Therefore, in order to replace the wafer 400 in the prober 100 with the wafer 400 in the stocker 300, when the wafer 400 is taken out from the stocker 300 and the wafer 400 is conveyed to the prober 100, it is in the air in the storage transfer system 200. Water vapor may condense (that is, dew condensation occurs) on the low temperature wafer 400 or on the storage transfer machine 210 that conveys the wafer 400. In order to prevent this dew condensation, the storage device 1 of the present embodiment is provided with an air conditioning control mechanism 500 to change the gas phase atmosphere in the storage transfer system 200 to dry air containing no water, noble gas, inert gas, or the like. Replace.
  • an air conditioning control mechanism 500 to change the gas phase atmosphere in the storage transfer system 200 to dry air containing no water, noble gas, inert gas, or the like. Replace.
  • the air conditioning control mechanism 500 replaces not only the gas phase atmosphere in the storage transfer system 200 but also in the prober 100 and the stocker 300 with dry air containing no water, a rare gas, an inert gas, or the like.
  • dew condensation on the wafer 400 can be almost completely prevented. Since it is preferable that there is no oxygen in addition to water in the space where the wafer 400 is handled, the gas phase atmosphere in the prober 100, the storage transfer system 200, and the stocker 300 is replaced with a rare gas, an inert gas, or the like. It is preferable to do so.
  • a cooling mechanism may be provided in the storage transfer system 200.
  • the stocker 300 is cooled in order to maintain the charge retention characteristics for a long time.
  • the temperature is usually room temperature, but the charge retention characteristic becomes higher as the temperature is cooled, so that the temperature can be assumed to be 0 ° C. or lower.
  • electrical side effects due to the condensation of water in the atmosphere for example, a short circuit between wirings, can be considered.
  • the air conditioning control mechanism 500 which is a kind of temperature control mechanism, it is possible to prevent dew condensation on the wafer 400, the storage carrier 210, and the like.
  • FIG. 14 is a flowchart showing an example of the flow of temperature control at the time of replacement of the wafer 400 executed by the storage device 1 of the present embodiment.
  • the storage device 1 electrically cuts the wafer 400 on the stage 120 from the probe card 110 by the drive unit 130 (S1).
  • the storage device 1 cools the probe card 110 and the electrically cut wafer 400 on the stage 120 (S2).
  • controller 111-1 obtains the temperature from the thermometer (430,1201) via the I 2 C bus.
  • the storage device 1 transfers, for example, the wafer 400 cooled to room temperature or lower from the prober 100 to the stocker 300 by the storage transfer system 200 (S3).
  • the storage device 1 transports the wafer 400 to be accommodated in the prober 100 by replacing the wafer 400 taken out from the prober 100 from the stocker 300 to the prober 100 by the storage transfer system 200 (S4).
  • the storage device 1 heats the wafer 400 electrically connected to the probe card 110 on the stage (S5).
  • controller 111-1 for example, obtains the temperature from the thermometer (430,1201) via the I 2 C bus.
  • the storage device 1 electrically connects the wafer 400, which has been heated to a temperature higher than room temperature, suitable for writing or reading data to the NAND chip 420, to the probe card 110 by the drive unit 130 (S6).
  • the storage device 1 of the present embodiment in which the temperature control mechanism is provided in each of the prober 100, the storage transfer system 200, and the stocker 300 can appropriately perform various temperature controls related to the wafer 400.
  • the heating / cooling mechanism 121 provided on the stage 120 of the prober 100 can be used for refreshing the wafer 400.
  • the refresh is a process for recovering the variation between cells when writing or reading data to or from the cells in the NAND chip, which has deteriorated due to read / write stress. This process also restores the data retention function of the NAND chip.
  • the wafer 400 is heated on the stage 120 and refreshed.
  • the inside of the prober 100 is sealed with these inert gases by using the intake port provided in the prober 100 and the supply mechanism of nitrogen, argon, helium, krypton, xenon, etc. provided in the prober 100. To do.
  • the area in the prober 100 may be sealed in a different atmosphere.
  • the storage device 1 of the present embodiment may provide the prober 100 with a refresh mechanism for heating the wafer 400 on the stage 120 and sealing the periphery of the wafer 400 with an inert gas.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Environmental & Geological Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Control Of Temperature (AREA)
PCT/JP2019/044931 2019-11-15 2019-11-15 ストレージデバイスおよび制御方法 Ceased WO2021095251A1 (ja)

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CN201980100500.3A CN114424331B (zh) 2019-11-15 2019-11-15 存储器设备以及控制方法
PCT/JP2019/044931 WO2021095251A1 (ja) 2019-11-15 2019-11-15 ストレージデバイスおよび制御方法
EP19952453.9A EP4060721A4 (en) 2019-11-15 2019-11-15 STORAGE DEVICE AND CONTROL METHOD
JP2021555761A JP7293389B2 (ja) 2019-11-15 2019-11-15 ストレージデバイスおよび制御方法
TW111115173A TWI800355B (zh) 2019-11-15 2020-08-12 儲存器設備及儲存器設備的控制方法
TW109127283A TWI765316B (zh) 2019-11-15 2020-08-12 儲存器設備及儲存器設備的控制方法
US17/694,532 US12384624B2 (en) 2019-11-15 2022-03-14 Storage device and control method

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TW202127561A (zh) 2021-07-16
US12384624B2 (en) 2025-08-12
JP7293389B2 (ja) 2023-06-19
US20220204270A1 (en) 2022-06-30
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TWI765316B (zh) 2022-05-21
JPWO2021095251A1 (https=) 2021-05-20

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