WO2021052218A1 - 掺杂型金属氧化物半导体及薄膜晶体管与应用 - Google Patents

掺杂型金属氧化物半导体及薄膜晶体管与应用 Download PDF

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WO2021052218A1
WO2021052218A1 PCT/CN2020/114043 CN2020114043W WO2021052218A1 WO 2021052218 A1 WO2021052218 A1 WO 2021052218A1 CN 2020114043 W CN2020114043 W CN 2020114043W WO 2021052218 A1 WO2021052218 A1 WO 2021052218A1
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oxide
indium tin
thin film
oxide semiconductor
film transistor
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English (en)
French (fr)
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徐苗
徐华
吴为敬
陈为峰
王磊
彭俊彪
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华南理工大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • the present invention relates to the field of semiconductor manufacturing, in particular to materials and device structures used in the production of metal oxide semiconductor thin film transistor backplanes in flat panel display and detector applications, and in particular to a doped metal oxide semiconductor and thin film transistors and applications.
  • the 5s orbital of In 3+ ions is the main electron transport channel.
  • the bond-breaking energy of In ions and O ions is relatively low, there are a large number of oxygen vacancy defects in pure In 2 O 3 thin films. Oxygen vacancies are the main reason for the deterioration of the stability of metal oxide thin film transistors.
  • Zn 2+ ions equivalent to the amount of In 3+ ions need to be doped to keep the metal oxide film amorphous.
  • one of the objectives of the present invention is to provide a doped metal oxide semiconductor that can effectively improve the electrical stability of the oxide semiconductor, especially the electrical stability under light conditions.
  • the second object of the present invention is to provide a thin film transistor including the doped metal oxide semiconductor.
  • the third objective of the present invention is to provide the application of the thin film transistor.
  • the doped metal oxide semiconductor is indium tin oxide or indium tin zinc oxide doped with rare earth oxide;
  • the rare earth oxide is praseodymium oxide and/or ytterbium oxide, and the doping molar ratio of praseodymium and/or ytterbium to indium tin oxide or indium tin zinc oxide is 0.002-0.4:1;
  • the doped metal oxide semiconductor has a rapid recombination center of photogenerated carriers.
  • the doped metal oxide semiconductor provided by the present invention is a compound semiconductor based on indium tin oxide, praseodymium oxide or ytterbium oxide can suppress oxygen vacancies at a lower doping amount, and can make indium tin oxide or indium zinc oxide On the basis of its high mobility, tin improves the stability of indium tin oxide or indium zinc tin oxide under light conditions.
  • the molar ratio of In and Sn is 2-5:1. Indium tin oxide has better mobility. After a higher proportion of ytterbium or praseodymium is doped, such as a doping ratio of 0.4 molar ratio, the mobility can still be maintained at 10 cm 2 ⁇ V -1 ⁇ s -1 . Further, in the doped metal oxide semiconductor, the atomic ratio of In, Sn, and Zn in indium tin zinc oxide is as follows: 0.2 ⁇ In/(In+Sn+Zn) ⁇ 0.8, 0.2 ⁇ Sn/ (In+Sn+Zn) ⁇ 0.4, 0 ⁇ Zn/(In+Sn+Zn) ⁇ 0.5.
  • the indium tin zinc oxide within this range can ensure that the mobility is not less than 10 cm 2 ⁇ V -1 ⁇ s -1 after being doped with no more than 0.1 mole of praseodymium or ytterbium.
  • the doping molar ratio of the praseodymium and/or ytterbium to indium tin oxide or indium tin zinc oxide is 0.02-0.40:1. That is, within this doping range, praseodymium oxide or ytterbium oxide can be used to exhibit better suppression of the characteristics of photo-generated current, and at the same time, it can make the metal oxide semiconductor operate with better mobility. More preferably, the doping molar ratio of praseodymium and/or ytterbium in the doped metal oxide semiconductor is 0.10-0.20:1. Within this range, the mobility of the doped metal oxide semiconductor is relatively high, the current switching ratio is on the order of 10 7 -10 9 , and the light stability is excellent.
  • the thin film transistor includes an active layer, and the active layer is prepared from the above-mentioned doped metal oxide semiconductor through a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, a laser deposition process, or a solution method.
  • the present invention also provides a thin film transistor formed based on the active layer made of the doped metal oxide semiconductor. Further, the turn-on voltage change ⁇ V on of the thin film transistor under light and non-light conditions is less than 2V. Or further, the threshold voltage change ⁇ V on of the thin film transistor under light and non-light conditions is less than 1V.
  • the active layer is prepared by a magnetron sputtering process
  • the active layer is prepared by a magnetron sputtering physical vapor deposition process
  • the sputtering pressure is 0.1-0.6 Pa
  • the oxygen in the sputtering atmosphere The volume ratio is 10-50%
  • the substrate temperature is room temperature to 300°C.
  • a single-target sputtering or co-sputtering method is adopted. Under the sputtering conditions, an active layer with uniform texture, good adhesion, and good film texture can be deposited.
  • a single target magnetron sputtering method is used to prepare the active layer of the thin film transistor. Further, it also includes a substrate, a gate electrode, a gate insulating layer, a source and drain electrode, and a passivation layer.
  • the thin film transistor adopts an etch blocking structure or a self-aligned structure.
  • the passivation layer is a silicon oxide film, or a laminated structure composed of a silicon nitride and a silicon oxide film.
  • the thin film transistor adopts a back-channel etching structure and adopts an aluminate-based etching solution.
  • the passivation layer is a silicon nitride film or a silicon nitride-silicon oxide laminated structure.
  • the substrate can be rigid alkali glass, alkali-free glass, quartz glass and silicon substrate, or flexible polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate Ethylene glycol (PET), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyvinyl ether (PES) or metal flakes.
  • PI polyimide
  • PEN polyethylene naphthalate
  • PET polyethylene terephthalate Ethylene glycol
  • PE polyethylene
  • PE polypropylene
  • PS polystyrene
  • PES polyvinyl ether
  • the gate may be a transparent conductive oxide, graphene, a metal-oxide semiconductor stack or a metal-metal stack.
  • the transparent conductive oxide includes ITO, AZO, GZO, IZO, ITZO, FTO
  • the metal-oxide semiconductor stack includes ITO/Ag/ITO, IZO/Ag/IZO
  • the metal-metal stack includes Mo/Al/Mo , Ti/Al/Ti.
  • the grid can be prepared by sputtering, electroplating, thermal evaporation and other deposition methods. Sputtering deposition is preferred because the film and substrate prepared by this method have good adhesion and uniformity, and can be prepared in a large area.
  • the gate insulating layer may be one or a stack of two or more of silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, or polymer organic film layers.
  • the gate insulating layer can be formed by stacking various insulating films, which can form better insulating properties on the one hand, and can improve the interface characteristics between the active layer and the gate insulating layer on the other hand.
  • the gate insulating layer can be prepared in various ways, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser deposition, anodic oxidation, or solution method.
  • the preferred etching solution is a hydrogen peroxide water-based etching solution, mainly because the doped metal oxide semiconductor of the present invention can effectively resist the etching of a wet hydrogen peroxide water-based etching solution, and it is compatible with metals (such as molybdenum, molybdenum alloys, molybdenum alloys, etc.). Molybdenum/copper, titanium/copper, etc.) have a high etching selection ratio, the metal oxide semiconductor layer is basically not affected by the etching solution, and the prepared device has excellent performance and good stability.
  • the source and drain electrode etching solution of the present invention can use a stronger aluminate-based etching solution, because the doped metal oxide semiconductor of the present invention has better resistance to strong acids such as aluminate-based etching. Eclipse characteristics.
  • the bond between the O 2- ions can be used up to 753.0 ( ⁇ Hf298, kJ / mol) of praseodymium oxide and 715.1 ( ⁇ Hf298, kJ / mol) of ytterbium oxide on an indium oxide
  • the doping of tin or indium tin zinc oxide semiconductor requires only a small amount of rare earth ion doping to effectively suppress the oxygen vacancy concentration in the oxide semiconductor film. Therefore, under the condition of a considerable amount of oxygen vacancy concentration, the doping concentration can be greatly reduced, which is beneficial to maintain the overlap degree of the 5s orbital of In ions, thereby reducing the influence on the mobility of the material.
  • the novel praseodymium ion or ytterbium ion doped doped metal oxide semiconductor has a device mobility as high as 30 cm 2 /vs.
  • the present invention has the following beneficial effects:
  • the present invention provides a praseodymium oxide or ytterbium oxide doped metal oxide semiconductor, which can effectively suppress the oxygen vacancy concentration in the film at a relatively low doping concentration.
  • the doped metal oxide semiconductor of the present invention can be Indium tin oxide, indium tin zinc oxide semiconductors; compared with traditional indium tin zinc oxide semiconductors, the mobility of the device is basically not affected;
  • the doped metal oxide semiconductor provided by the present invention after being doped with praseodymium oxide or ytterbium oxide, will form a recombination center of photogenerated carriers within the range of the energy band close to the Fermi level ⁇ 0.3 eV. These recombination centers can provide fast recombination channels for photo-generated carriers, avoiding their influence on I-V characteristics and stability. Furthermore, the stability of the metal oxide semiconductor device under illumination is greatly improved.
  • FIG. 1 is a schematic diagram of the structure of the thin film transistor of the embodiment 9 and the embodiment 10;
  • FIG. 2 is a schematic diagram of the structure of the thin film transistor of Embodiment 11;
  • FIG. 3 is a schematic diagram of the structure of a thin film transistor of Embodiment 12;
  • Fig. 4 is a graph of the photo-generated current characteristics and the negative bias light stability curve of Example 9;
  • Fig. 5 is a graph of the photo-generated current characteristics and the negative bias light stability curve of Example 10.
  • Fig. 6 is the photo-generated current characteristic and the negative bias light stability curve of Example 11;
  • FIG. 7 is a graph of the photo-generated current characteristics and the negative bias light stability curve of Example 12.
  • Example 1 Ytterbium oxide doped indium tin oxide semiconductor material
  • a group of doped metal oxide semiconductors is: indium tin oxide (ITO) is doped with ytterbium oxide as a light stabilizer to form ytterbium oxide doped indium tin oxide (Yb:ITO) ) Of semiconductor materials.
  • ITO indium tin oxide
  • Yb:ITO ytterbium oxide doped indium tin oxide
  • Example 2 Ytterbium oxide doped indium tin zinc oxide semiconductor material
  • a group of doped metal oxide semiconductors is: indium tin zinc oxide (ITZO) is doped with ytterbium oxide as a light stabilizer to form ytterbium oxide doped indium tin zinc oxide (Yb : ITZO) semiconductor materials.
  • ITZO indium tin zinc oxide
  • Yb ytterbium oxide doped indium tin zinc oxide
  • the molar ratio of ytterbium to indium tin zinc oxide is 0.002, 0.020, 0.100, 0.200, 0.40, and 0.60, respectively.
  • Example 3 Praseodymium oxide doped indium tin zinc oxide semiconductor material
  • a doped metal oxide semiconductor is: indium tin zinc oxide (ITZO) is doped with praseodymium oxide as a light stabilizer to form praseodymium oxide doped indium tin zinc oxide (Pr: ITZO) semiconductor materials.
  • ITZO indium tin zinc oxide
  • Example 4 Praseodymium oxide doped indium tin zinc oxide semiconductor material
  • a group of doped metal oxide semiconductors is: indium tin zinc oxide (ITZO) is doped with praseodymium oxide as a light stabilizer to form praseodymium oxide doped indium tin zinc oxide (Pr : ITZO) semiconductor materials.
  • ITZO indium tin zinc oxide
  • Example 5 Ytterbium oxide doped indium tin oxide film
  • a set of metal oxide semiconductor thin films, the set of metal oxide semiconductor thin films are formed from the ytterbium oxide doped indium tin oxide semiconductor material of Example 1 by magnetron sputtering.
  • ITO indium tin oxide
  • Yb:ITO ytterbium oxide-doped indium tin oxide
  • the heteromolar ratio y is equal to 0.002, 0.020, 0.100, 0.200, 0.40, and 0.60, respectively.
  • the thickness of the film is 30 nm, the oxygen content in the sputtering atmosphere is 20%, and the sputtering pressure is 0.5 Pa.
  • the composition ratio of the film is calibrated by X-ray photoelectron spectroscopy combined with the characterization results such as transmission electron microscopy, and some thin films with very small content are obtained by reasoning of sputtering power.
  • Example 6 Ytterbium oxide doped indium tin zinc oxide film
  • a group of metal oxide semiconductor thin films are formed from the ytterbium oxide doped indium tin zinc oxide semiconductor material of the second embodiment by magnetron sputtering.
  • the thin film is prepared by co-sputtering. By adjusting the sputtering power of the two targets, the preparation of thin films with different composition ratios can be achieved.
  • the doping molar ratios of ytterbium and indium tin zinc oxide are respectively equal to 0.002, 0.020, 0.100, 0.200, 0.40 and 0.60.
  • the thickness of the film is 40 nm
  • the oxygen content in the sputtering atmosphere is 20%
  • the sputtering pressure is 0.5 Pa; after the film is deposited, it is annealed in a high-temperature oven at 350° C. for 30 minutes in an air atmosphere.
  • the composition ratio of the film is calibrated by X-ray photoelectron spectroscopy combined with the characterization results such as transmission electron microscopy, and some thin films with very small content are obtained by reasoning of sputtering power.
  • Example 7 Praseodymium oxide doped indium tin zinc oxide film
  • a group of metal oxide semiconductor thin films are formed by magnetron sputtering of the praseodymium oxide doped indium tin zinc oxide semiconductor material of the third embodiment.
  • the method of co-sputtering realizes the preparation of thin films with different composition ratios by adjusting the sputtering power of two target materials.
  • the doping molar ratio y of praseodymium and indium tin zinc oxide is equal to 0.002, 0.020, 0.100, 0.200, 0.40, and 0.60, respectively.
  • the thickness of the group of praseodymium oxide doped indium tin zinc oxide films is 30 nm
  • the oxygen content in the sputtering atmosphere is 20%
  • the sputtering pressure is 0.5 Pa
  • the substrate temperature is set to room temperature.
  • the composition ratio of the film is calibrated by X-ray photoelectron spectroscopy combined with the characterization results such as transmission electron microscopy, and some thin films with very small content are obtained by reasoning of sputtering power.
  • Example 8 Praseodymium oxide doped indium tin zinc oxide film
  • a set of metal oxide semiconductor thin films, the set of metal oxide semiconductor thin films are prepared from the praseodymium oxide doped indium tin zinc oxide semiconductor material of Example 4 by a solution method.
  • This group of praseodymium oxide doped indium tin zinc oxide films is prepared by the solution method, and the specific preparation method is as follows:
  • a group of thin film transistors adopts an etching barrier structure.
  • the schematic diagram of the structure is shown in Figure 1. It is provided with: a substrate 01, a gate 02 on the substrate 01, and a gate insulating layer on the substrate 01 and the gate 02 03.
  • the active layer 04 covering the upper surface of the gate insulating layer 03 and corresponding to the gate 02, the etching stop layer 05, the source 06-1 and the drain spaced apart from each other and electrically connected to both ends of the active layer 04 ⁇ 06-2 and passivation layer 07.
  • the active layer 04 is the active layer 04 formed by the thin film described in embodiment 5;
  • the substrate 01 is a glass substrate covered with a buffer layer of silicon oxide;
  • the material of the gate 02 is a molybdenum aluminum molybdenum (Mo/Al/Mo) metal laminate structure prepared by magnetron sputtering, and the thickness is 50/200/ 50nm;
  • the gate insulating layer 03 is a stack of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 250/50 nm; the silicon nitride is in contact with the gate 02 in the lower layer and is oxidized Silicon is in contact with the active layer 04 in the upper layer.
  • the materials of the etch barrier layer 05 and the passivation layer 07 are silicon oxide (SiO 2 ) films prepared by chemical vapor deposition, with a thickness of 300 nm, and a deposition temperature of 250°C.
  • the material of the source electrode 06-1 and the drain electrode 06-2 is a metal molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure with a thickness of 50/200/50 nm.
  • a group of thin film transistors adopts an etching barrier structure.
  • the schematic diagram of the structure is shown in Figure 1. It is provided with: a substrate 01, a gate 02 on the substrate 01, and a gate insulating layer on the substrate 01 and the gate 02 03.
  • the active layer 04 covering the upper surface of the gate insulating layer 03 and corresponding to the gate 02, the etching stop layer 05, the source 06-1 and the drain spaced apart from each other and electrically connected to both ends of the active layer 04 ⁇ 06-2, passivation layer 07.
  • the thin film of the active layer 04 is the thin film described in embodiment 6;
  • the substrate 01 is a glass substrate covered with a buffer layer of silicon oxide.
  • the material of the gate 02 is a molybdenum aluminum molybdenum (Mo/Al/Mo) metal laminate structure prepared by magnetron sputtering, and the thickness is 50/200/50 nm.
  • the gate insulating layer 03 is a stack of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 250/50 nm; the silicon nitride is in contact with the gate 02 in the lower layer and is oxidized Silicon is in contact with the active layer 04 in the upper layer.
  • the material of the etching barrier layer 05 and the passivation layer 07 is a silicon oxide (SiO 2 ) film prepared by chemical vapor deposition, the thickness is both 300 nm, and the deposition temperature is 230°C.
  • the material of the source electrode 06-1 and the drain electrode 06-2 is a metal molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure with a thickness of 50/200/50 nm.
  • a group of thin film transistors is a back-channel etched structure.
  • the schematic diagram of the structure is shown in Figure 2. It is provided with a substrate 01, a gate 02 on the substrate 01, and a gate on the substrate 01 and the gate 02.
  • the substrate 01 is a hard alkali-free glass substrate, which is covered with a buffer layer of silicon oxide.
  • the material of the gate 02 is a metal molybdenum/aluminum/molybdenum (Mo/Al/Mo) laminated structure prepared by magnetron sputtering, and the thickness is 50/200/50 nm.
  • the gate insulating layer 03 is a stack of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 250/50 nm.
  • the silicon nitride is in contact with the gate 02 in the lower layer and is oxidized. Silicon is in contact with the active layer 04 in the upper layer.
  • the active layer 04 is the thin film obtained in Example 7;
  • the material of source 06-1 and drain 06-2 is a metal molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure with a thickness of 50/200/50nm, which is patterned with a commercial aluminate-based etching solution Since the active layer of the present invention has good etching resistance to strong acids, it has less damage to the active layer 04 and can achieve an excellent etching selection ratio; and there is no obvious etching residue.
  • Mo/Al/Mo metal molybdenum aluminum molybdenum
  • the material of the passivation layer 07 is silicon oxide (SiO 2 ) prepared by chemical vapor deposition, the thickness is 300 nm, and the deposition temperature is 250°C.
  • a group of thin film transistors is a self-aligned structure.
  • the schematic diagram of the structure is shown in Figure 3. It is provided with: a substrate 01, a buffer layer 08, an active layer 04, a gate insulating layer 03 on the active layer 04, and a gate Electrode 02, spacer layer 09 covering the upper surface of active layer 04 and gate 02, source electrode 06-1 and drain electrode 06-2 on spacer layer 09 and electrically connected to both ends of active layer 04 .
  • the substrate 01 is a hard glass substrate.
  • the buffer layer 08 is silicon oxide prepared by plasma enhanced chemical vapor deposition.
  • the active layer 04 is the thin film of Example 8.
  • the gate insulating layer 03 is silicon oxide with a thickness of 300 nm; the gate electrode 02 is a molybdenum/copper (Mo/Cu) laminated structure prepared by magnetron sputtering, and the thickness is 200/20 nm.
  • Mo/Cu molybdenum/copper
  • the spacer layer 09 is a laminated structure of silicon oxide/silicon nitride with a thickness of 200/100 nm.
  • the material of the source electrode 06-1 and the drain electrode 06-2 is a molybdenum/copper (Mo/Cu) laminated structure prepared by magnetron sputtering, and the thickness is 200/20nm.
  • Mo/Cu molybdenum/copper
  • the substrate in the present invention is not particularly limited, and a substrate known in the art can be used.
  • a substrate known in the art can be used.
  • the gate material in the present invention is not particularly limited, and it can be arbitrarily selected from materials known in the art. Such as: transparent conductive oxides (ITO, AZO, GZO, IZO, ITZO, FTO, etc.), graphene, metals (Mo, Al, Cu, Ag, Ti, Au, Ta, Cr, Ni, etc.) and their alloys, and A composite conductive film formed by metal and oxide (ITO/Ag/ITO, IZO/Ag/IZO, etc.), metal and metal stacking (Mo/Al/Mo, Ti/Al/Ti, etc.).
  • transparent conductive oxides ITO, AZO, GZO, IZO, ITZO, FTO, etc.
  • graphene graphene
  • metals Mo, Al, Cu, Ag, Ti, Au, Ta, Cr, Ni, etc.
  • a composite conductive film formed by metal and oxide ITO/Ag/ITO, IZO/Ag/IZO, etc.
  • the preparation method of the gate film can be sputtering, electroplating, thermal evaporation and other deposition methods.
  • the sputtering deposition method is preferred because the film prepared by this method has good adhesion to the substrate, excellent uniformity, and can be prepared in a large area .
  • a transparent electrode is needed in a transparent display. It can be a single layer of ITO as the gate or ITO/Ag/ITO as the gate. pole.
  • high-temperature processes are required for applications in special fields, and metal alloy films that can withstand high temperatures can be selected for the gate electrode.
  • the material of the gate insulating layer in the present invention is not particularly limited, and it can be arbitrarily selected from materials known in the art. Such as: silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, and polymer organic film layers.
  • the composition of the gate insulating film may be inconsistent with the theoretical stoichiometric ratio.
  • the gate insulating layer can be formed by stacking various insulating films, which can form better insulating properties on the one hand, and can improve the interface characteristics between the active layer and the gate insulating layer on the other hand.
  • the gate insulating layer can be prepared in various ways, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser deposition, anodic oxidation, or solution method.
  • the thickness range of the active layer provided in this application can be selected from 5 nm to 100 nm, preferably 20-40 nm.
  • the carrier concentration of the metal oxide semiconductor thin film forming the active layer is less than 5 ⁇ 10 19 cm -3 .
  • the patterning process of the active layer film adopts a photolithography process in combination with a wet etching method.
  • the etching solution used in wet etching includes: a mixture of phosphoric acid, nitric acid, and glacial acetic acid, a commercial oxalic acid-based etching solution, a dilute hydrochloric acid etching solution, and an etching solution such as hydrofluoric acid.
  • the patterning process of the source and drain electrode films adopts a photolithography process in combination with a wet or dry etching method.
  • the etching solution used in wet etching includes: a mixture of phosphoric acid, nitric acid, and glacial acetic acid or a mixture based on hydrogen peroxide.
  • a plasma etching process can be selected, and the etching gas includes a chlorine-based or fluorine-based gas.
  • the doped metal oxide semiconductor adopts the vacuum magnetron sputtering process
  • single target sputtering or multi-target co-sputtering can be selected, and single target sputtering is preferred.
  • single-target sputtering can provide a film with better repeatability and stability, and the microstructure of the film is easier to control; unlike the co-sputtering film, the sputtered particles will be affected by more factors during the recombination process. Interference.
  • the power supply can be radio frequency (RF) sputtering, direct current (DC) sputtering or alternating current (AC) sputtering, preferably AC sputtering commonly used in the industry.
  • RF radio frequency
  • DC direct current
  • AC alternating current
  • the sputtering pressure can be selected from 0.1Pa-10Pa, preferably 0.2Pa-0.7Pa.
  • the oxygen partial pressure can be selected from 0-1 Pa, preferably 0.001-0.5 Pa, more preferably 0.01-0.1 Pa.
  • the oxygen volume ratio is preferably 0.1-0.5, more preferably 0.2-0.3.
  • the oxygen partial pressure has a direct effect on the carrier concentration of the film, and some oxygen vacancy-related defects will be introduced. Too low oxygen content may cause serious oxygen mismatch in the film and increase the carrier concentration; while too high oxygen vacancies will cause more weak bonding bonds and reduce the reliability of the device.
  • the substrate temperature is preferably room temperature to 300°C, more preferably 200-300°C.
  • a certain substrate temperature can effectively improve the bonding mode of the sputtered particles after they reach the substrate, reduce the probability of weak bonding bonds, and improve the stability of the device.
  • this effect can also be achieved by subsequent annealing treatment and other processes to achieve the same effect.
  • the thickness of the active layer can be selected from 2-100nm, preferably 5-50nm, more preferably 20-40nm.
  • the source and drain electrode materials in the present invention are not particularly limited, and they can be arbitrarily selected from materials known in the art without affecting the realization of various required structural devices.
  • materials known in the art such as: transparent conductive oxides (ITO, AZO, GZO, IZO, ITZO, FTO, etc.), graphene, metals (Mo, Al, Cu, Ag, Ti, Au, Ta, Cr, Ni, etc.) and their alloys, and A composite conductive film formed by metal and oxide (ITO/Ag/ITO, IZO/Ag/IZO, etc.), metal and metal stacking (Mo/Al/Mo, Ti/Al/Ti, etc.).
  • the method for preparing the source and drain electrode films can be sputtering, thermal evaporation and other deposition methods.
  • the sputtering deposition method is preferred because the film prepared by this method has good adhesion to the substrate, excellent uniformity, and can be prepared in a large area.
  • the source and drain electrodes and the active layer need to have a suitable etching selection ratio, otherwise the device cannot be fabricated.
  • the composite metal oxide semiconductor of the present invention has good etching resistance to strong acids such as aluminate. Therefore, in the preparation of back-channel etched devices, the source and drain electrodes can be etched by alumina-based strong acids. Etching solution, the etched source and drain electrodes have good morphology, no etching residue, excellent device performance and good stability.
  • the dry etching in the embodiment of the present invention is based on the conventional etching gas in the industry (such as chlorine-based gas, fluorine-based gas, etc.), which has little effect on the oxide semiconductor layer of the present invention, and the performance of the prepared device Excellent and good stability.
  • the conventional etching gas in the industry such as chlorine-based gas, fluorine-based gas, etc.
  • the passivation layer material in the present invention is not particularly limited, and it can be arbitrarily selected from materials known in the art. Such as: silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, and polymer organic film layers.
  • the composition of these insulating films may be inconsistent with the theoretical stoichiometric ratio.
  • the gate insulating layer can be formed by stacking various insulating films, which can form better insulating properties on the one hand, and can improve the interface properties of the active layer and the passivation layer on the other hand.
  • the passivation layer can be prepared in various ways, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser deposition, or solution method.
  • the deposition rate of the film is generally faster; the film does not have enough time to perform the relaxation process during the deposition process, which will cause a certain proportion of dislocation and stress Remains in the film.
  • This requires post-heat annealing treatment to continue to achieve the required relative steady state and improve the performance of the film.
  • the annealing treatment is mostly set after the deposition of the active layer and after the deposition of the passivation layer.
  • annealing treatment after the deposition of the active layer can effectively improve the in-situ defects in the active layer and improve the ability of the active layer to resist possible damage in subsequent processes.
  • this may require an "activation" process to further eliminate the interface state and some donor doping effects.
  • the treatment method may not only be heat treatment, but may include plasma treatment interface (such as gate insulating layer/semiconductor interface, active layer/passivation layer interface, etc.).
  • plasma treatment interface such as gate insulating layer/semiconductor interface, active layer/passivation layer interface, etc.
  • the performance of the device and the stability of the device can be effectively improved through the above-mentioned treatment process.
  • the thin film transistors of Embodiments 9 and 10 may be a closed structure including only the substrate, the gate, the gate insulating layer, the active layer, the etching stop layer, the source and drain, and the passivation layer, or it may further include a flattened structure. Layers, reflective electrodes, pixel definition layers, etc., can also be integrated with other devices.
  • the thin film transistor of embodiment 11 may be a closed structure including only a substrate, a gate, a gate insulating layer, an active layer, a source and a drain, and a passivation layer. It may also further include a flat layer, a reflective electrode, and a pixel definition. Layers, etc., can also be integrated with other devices.
  • the thin film transistor of Embodiment 12 may be a closed structure including only a substrate, an active layer, a gate insulating layer, a gate electrode, a spacer layer, a source electrode, and a drain electrode, or it may further include a passivation layer, a pixel definition layer, etc. , It can also be integrated with other devices.
  • a commercial white LED light source was used to illuminate the active layer of the thin film transistor devices of Examples 9-12 with a light intensity of 5000 nits.
  • the transfer characteristics of the device under light and no light conditions were evaluated, and the change in the switching voltage of the device was extracted. Strength; Among them, the device turn-on voltage is defined as the corresponding gate voltage when the current across the source and drain electrodes is 10 -9 A.
  • the light response characteristic is expressed by the change amplitude of the device's turn-on voltage ⁇ V on under light and no light conditions. A large value indicates a strong photo-generated current characteristic, and vice versa.
  • a commercial white LED light source is used to illuminate the active layer 04 of the thin film transistor device of Examples 9-12 with a light intensity of 5000 nits.
  • a voltage of -30V is applied to the gate of the device, and a bias voltage of 0V is applied to both ends of the source and drain electrodes ;
  • PL photoluminescence
  • the doping of rare earth oxides has a very obvious impact on the performance of the device.
  • the photogenerated current characteristics of the device are significantly suppressed.
  • the molar ratio of rare earth oxides doped into metal oxide semiconductors is positively correlated with threshold voltage, subthreshold swing, and stability, and is related to mobility, current-on-off ratio, and photocurrent Features are negatively correlated;
  • the doping molar ratio of praseodymium or ytterbium is 0.10:1, and the photogenerated current characteristics and negative bias light stability of the device are very excellent. , which greatly enhances its potential in practical applications.
  • ytterbium oxide is doped into the active layer formed by the indium tin oxide semiconductor film.
  • y is 0.02-0.40
  • the overall performance of the device is better, and more preferably, when y is 0.02 -0.20, the overall performance of the device is better, when y is 0.10-0.20, the overall performance of the device is the best; that is, when the doping ratio is 0.10-0.20, under light conditions, the threshold voltage of the device hardly changes , Excellent light stability on the surface.
  • the molar ratio of rare earth oxide doped into indium tin oxide or indium tin zinc oxide is preferably 0.02-0.40, more preferably 0.02-0.20, and most preferably 0.10-0.20.
  • the threshold voltage of the device is lower than 2V
  • subthreshold swing is less than 0.40V / decade
  • the current ratio between the switch 107 to the order of 109 wherein the weak photocurrent excellent stability.
  • the thin film transistor obtained in Examples 9-12 can be applied to a display panel, and the thin film transistor is used to drive a display unit in the display panel. Or it can be applied to a detector. The thin film transistor is used to drive the detection unit of the detector.

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Abstract

一种掺杂型金属氧化物半导体、薄膜晶体管及其应用，掺杂型金属氧化物半导体为掺杂有稀土氧化物的氧化铟锡或氧化铟锡锌半导体，可以在较低的氧化镱或氧化镨掺杂浓度下抑制薄膜中的氧空位浓度，迁移率可以保持在较高的值；从而形成的薄膜能避免光照对I-V特性和稳定性的影响，提高金属氧化物半导体器件在光照下的稳定性。

Description

掺杂型金属氧化物半导体及薄膜晶体管与应用 技术领域
本发明涉及半导体制造领域，尤其涉及平板显示和探测器应用中的金属氧化物半导体薄膜晶体管背板制作所用的材料和器件结构，具体涉及一种掺杂型金属氧化物半导体及薄膜晶体管与应用。
背景技术
对于现有的金属氧化物半导体体系中，In 3+离子的5s轨道是主要的电子输运通道。但是由于In离子与O离子成键后的断键能较低，所以在单纯的In 2O 3薄膜中存在大量的氧空位缺陷。而氧空位是导致金属氧化物薄膜晶体管稳定性劣化的主要原因。通常，需要掺杂与In 3+离子数量相当的Zn 2+离子使金属氧化物薄膜保持非晶特性。
Sn 4+离子主要是利用Sn-O键化学惰性的特性，提供抗酸刻蚀的能力。但是由于In、Sn、Zn离子与O离子成键后的断键能较低，所以在单纯的ITZO薄膜中存在大量的氧空位缺陷。而氧空位是导致金属氧化物薄膜晶体管稳定性劣化的主要原因。而且，Sn在薄膜中通常会作为电子的载流子来源，进一步增加了薄膜的载流子浓度。因此，目前常用的ITZO材料存在电学稳定性较差问题，特别是光照下的稳定性有待提高。
发明内容
为了克服现有技术的不足，本发明的目的之一在于提供能有效提高氧化物半导体的电学稳定性尤其是光照条件下的电学稳定性的掺杂型金属氧化物半导体。
本发明的目的之二在于提供包含该掺杂型金属氧化物半导体的薄膜晶体管。
本发明的目的之三在于提供该薄膜晶体管的应用。
本发明的目的之一采用如下技术方案实现：
掺杂型金属氧化物半导体，该掺杂型金属氧化物半导体为掺杂有稀土氧化物的氧化铟锡或氧化铟锡锌；
所述稀土氧化物为氧化镨和/或氧化镱，镨和/或镱与氧化铟锡或氧化铟锡锌的掺杂摩尔比为0.002-0.4:1；
所述掺杂型金属氧化物半导体存在光生载流子快速复合中心。
即本发明提供的掺杂型金属氧化物半导体是基于氧化铟锡的复合半导体，氧化镨或氧化镱可以在较低的掺杂量实现对氧空位的抑制，可以使氧化铟锡或氧化铟锌锡在具有较高的迁移率的基础上，提高氧化铟锡或氧化铟锌锡在光照条件下的稳定性。
进一步地，所述氧化铟锡中，In和Sn的摩尔比为2-5:1。氧化铟锡具有较佳的迁移率，可在掺杂较高比例的镱或镨后，如达到0.4摩尔比的掺杂比后，迁移率仍然维持在10cm 2·V -1·s -1。进一步地，掺杂型金属氧化物半导体中，氧化铟锡锌中In、Sn、Zn三种金属元素的原子比例关系如下：0.2≤In/(In+Sn+Zn)≤0.8，0.2≤Sn/(In+Sn+Zn)≤0.4，0≤Zn/(In+Sn+Zn)≤0.5。示例性地，氧化铟锡锌中，各氧化物的摩尔比如下，In 2O 3:SnO 2:ZnO＝1.5:2:5(mol)，即In:Sn:Zn＝3:2:5(mol)；或In 2O 3:SnO 2:ZnO＝1:2:1(mol)，即In:Sn:Zn＝2:2:1(mol)；或In 2O 3:SnO 2:ZnO＝2:3:3(mol)，即In:Sn:Zn＝4:3:3(mol)。该范围内的氧化铟锡锌可 以保证在掺杂不高于0.1摩尔的镨或镱后，迁移率不低于10cm 2·V -1·s -1。
进一步地，所述镨和/或镱与氧化铟锡或氧化铟锡锌的掺杂摩尔比为0.02-0.40:1。即在该掺杂范围内，可使用氧化镨或氧化镱表现出较佳的对光生电流特征的抑制性，同时，又能使金属氧化物半导体操持较佳的迁移率。更优选地，所述掺杂型金属氧化物半导体中镨和/或镱的掺杂摩尔比为0.10-0.20:1。在该范围内，掺杂型金属氧化物半导体的迁移率相对较高、电流开关比在10 7-10 9的数量级左右，同时光稳定性优异。
本发明的目的之二采用如下技术方案实现：
薄膜晶体管，包括有源层，所述有源层由上述的掺杂型金属氧化物半导体经物理气相沉积工艺、化学气相沉积工艺、原子层沉积工艺、激光沉积工艺或者溶液法制备而成。
即本发明还提供基于该掺杂型金属氧化物半导体制得的有源层形成的薄膜晶体管。进一步地，该薄膜晶体管在光照和非光照条件下开启电压变化△V on小于2V。或进一步地，该薄膜晶体管在光照和非光照条件下阈值电压变化△V on小于1V。
进一步地，所述有源层经磁控溅射工艺制备而成，所述有源层经磁控溅射物理气相沉淀工艺制备而成，溅射气压为0.1-0.6Pa，溅射氛围中氧气体积占比为10-50％，衬底温度为室温至300℃。具体地，采用单靶材溅射或共溅射的方式，在该溅射条件下，可以沉积得到质地均匀、附着力佳、薄膜质地佳的有源层。
优选地，采用单靶材磁控溅射方式制备薄膜晶体管的有源层。进一步地，还包括基板、栅极、栅绝缘层、源漏极和钝化层，所述薄膜晶体管采用刻蚀阻 挡型结构或自对准型结构。
进一步地，所述钝化层为氧化硅薄膜，或氮化硅和氧化硅薄膜组成的叠层结构。
进一步地，还包括基板、栅极、栅绝缘层、源漏极和钝化层，所述薄膜晶体管采用背沟道刻蚀型结构，采用铝酸基刻蚀液。
进一步地，所述钝化层为氮化硅薄膜或氮化硅-氧化硅叠层结构。
进一步地，基板可以是刚性的碱玻璃、无碱玻璃、石英玻璃和硅基板，或者是柔性的聚酰亚胺(PI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚苯乙烯(PS)、聚矾醚(PES)或者金属薄片。
进一步地，所述栅极可以是透明导电氧化物、石墨烯、金属-氧化物半导体叠层或金属-金属叠层。其中，透明导电氧化物包括ITO、AZO、GZO、IZO、ITZO、FTO、金属-氧化物半导体叠层包括ITO/Ag/ITO、IZO/Ag/IZO、金属-金属叠层包括Mo/Al/Mo、Ti/Al/Ti。
栅极的制备方法可以是溅射法、电镀、热蒸发和其他的沉积方式，优选溅射沉积方式，因为该方式制备的薄膜和基板的粘附性好、均匀性优异、可以大面积制备。
其中，栅绝缘层可以是氧化硅、氮化硅、氧化铝、氧化钽、氧化铪、氧化钇或高分子有机膜层中的一种或两种以上的叠设。其中，采栅绝缘层可以是多种绝缘膜叠设而成，一方面可以形成更好的绝缘特性，另一方面可以改善有源层和栅绝缘层的界面特性。而且，该栅绝缘层的制备方式多样，可以是物理气相沉积、化学气相沉积、原子层沉积、激光沉积、阳极氧化或溶液法等方式制 备。
另外，还需注意的是，在制备背沟道刻蚀型结构的器件中，源漏电极和有源层需要有合适的刻蚀选择比，否则无法实现器件的制备。较优的刻蚀液为双氧水基刻蚀液，主要是因为本发明的掺杂型金属氧化物半导体能有效抵抗湿法双氧水基刻蚀液的刻蚀，其和金属(如钼、钼合金、钼/铜、钛/铜等)具有很高的刻蚀选择比，该金属氧化物半导体层基本不受刻蚀液的影响，所制备的器件性能优异，稳定性好。
需要特别指出的是，本发明的源漏电极刻蚀液可以使用较强的铝酸基刻蚀液，因为本发明的掺杂型金属氧化物半导体对铝酸基等强酸具有较好的抗刻蚀特性。
本发明的目的之三采用如下技术方案实现：
上述的薄膜晶体管在显示面板或探测器中的应用。
本发明的原理如下：
本发明的掺杂型金属氧化物半导体，通过使用与O 2-离子之间的键能高达753.0(ΔHf298,kJ/mol)的氧化镨和715.1(ΔHf298,kJ/mol)的氧化镱对氧化铟锡或氧化铟锡锌半导体进行掺杂，只需要少量的稀土离子的掺杂，便可以有效的抑制氧化物半导体薄膜中的氧空位浓度。因此，在相当数量的氧空位浓度条件下，其掺杂浓度可以大幅降低，有利于保持In离子5s轨道的重叠程度，从而对材料的迁移率的影响降低。该新型的镨离子或镱离子掺杂的掺杂型金属氧化物半导体，器件迁移率可以高达30cm 2/vs。
相比现有技术，本发明的有益效果在于：
本发明提供一种氧化镨或氧化镱掺杂型金属氧化物半导体，可以在相对较 低的掺杂浓度下，有效抑制薄膜中的氧空位浓度，本发明的掺杂型金属氧化物半导体可以是氧化铟锡、氧化铟锡锌半导体；相比于传统的氧化铟锡锌半导体，器件的迁移率基本上不受影响；
本发明提供的掺杂型金属氧化物半导体，掺杂氧化镨或氧化镱后，会在能带的靠近费米能级±0.3eV范围内形成光生载流子的复合中心。这些复合中心，能提供光生载流子的快速复合通道，避免其对I-V特性以及稳定性的影响。进而大幅提高金属氧化物半导体器件在光照下的稳定性。
附图说明
图1为实施例9和实施例10的薄膜晶体管结构示意图；
图2为实施例11的薄膜晶体管结构示意图；
图3为实施例12的薄膜晶体管结构示意图；
图4为实施例9的光生电流特性和负偏压光照稳定性曲线；
图5为实施例10的光生电流特性和负偏压光照稳定性曲线；
图6为实施例11的光生电流特性和负偏压光照稳定性曲线；
图7为实施例12的光生电流特性和负偏压光照稳定性曲线；
图8为对实施例7中的未掺杂(y＝0)和掺杂(y＝0.1)镨的氧化铟锡锌薄膜进行PL光谱和寿命测试的表征结果。
图中，各附图标记：01、基板；02、栅极；03、栅绝缘层；04、有源层；05、刻蚀阻挡层；06-1、源极；06-2、漏极；07、钝化层；08、缓冲层；09、间隔层。
具体实施方式
下面，结合附图和具体实施方式，对本发明做进一步描述，需要说明的是，在不相冲突的前提下，以下描述的各实施例之间或各技术特征之间可以任意组合形成新的实施例。
以下是本发明具体的实施例，在下述实施例中所采用的原材料、设备等除特殊限定外均可以通过购买方式获得。
实施例1：氧化镱掺杂氧化铟锡半导体材料
一组掺杂型金属氧化物半导体，该组掺杂型金属氧化物半导体为：在氧化铟锡(ITO)中掺入氧化镱作为光稳定剂，形成氧化镱掺杂氧化铟锡(Yb:ITO)的半导体材料。
其中，氧化铟锡中，In 2O 3:SnO 2＝2:1(mol)；即In、Sn的摩尔比为In:Sn＝4:1；在氧化镱掺杂氧化铟锡中，镱与氧化铟锡的摩尔比依次为0.002、0.020、0.100、0.200、0.40和0.60。
实施例2：氧化镱掺杂氧化铟锡锌半导体材料
一组掺杂型金属氧化物半导体，该组掺杂型金属氧化物半导体为：在氧化铟锡锌(ITZO)中掺入氧化镱作为光稳定剂，形成氧化镱掺杂氧化铟锡锌(Yb:ITZO)的半导体材料。
在氧化铟锡锌中，In 2O 3:SnO 2:ZnO＝1.5:2:5(mol)；即In、Sn、Zn的摩尔比为In:Sn:Zn＝3:2:5；在氧化镱掺杂氧化铟锡锌中，镱与氧化铟锡锌的摩尔比分别为0.002、0.020、0.100、0.200、0.40和0.60。
实施例3：氧化镨掺杂氧化铟锡锌半导体材料
一种掺杂型金属氧化物半导体，该掺杂型金属氧化物半导体为：在氧化铟锡锌(ITZO)中掺入氧化镨作为光稳定剂，形成氧化镨掺杂氧化铟锡锌(Pr:ITZO)的半导体材料。
在氧化铟锡锌中，In、Sn、Zn的摩尔比为In:Sn:Zn＝2:2:1；在氧化镨掺杂氧化铟锡锌中，镨与氧化铟锡锌的摩尔比分别为0.002、0.020、0.100、0.200、0.40和0.60。
实施例4：氧化镨掺杂氧化铟锡锌半导体材料
一组掺杂型金属氧化物半导体，该组掺杂型金属氧化物半导体为：在氧化铟锡锌(ITZO)中掺入氧化镨作为光稳定剂，形成氧化镨掺杂氧化铟锡锌(Pr:ITZO)的半导体材料。
在氧化铟锡锌中，In、Sn、Zn的摩尔比为In:Sn:Zn＝4:3:3；在氧化镨掺杂氧化铟锡锌中，镨与氧化铟锡锌的摩尔比分别为0.002、0.020、0.100、0.200、0.40和0.60。
实施例5：氧化镱掺杂氧化铟锡薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例1的氧化镱掺杂氧化铟锡半导体材料经磁控溅射而成。
该组金属氧化物半导体薄膜采用氧化铟锡(ITO，y＝0)和氧化镱掺杂的氧化铟锡(Yb:ITO，y＝0.60)两个陶瓷靶材，采用共溅射的方式制备薄膜。通过调整两个靶材的溅射功率从而实现不同成分比例的薄膜制备。
其中氧化铟锡靶材的成分比例为In 2O 3:SnO 2＝2:1(mol)，标记为In(4)Sn(1)；氧化镱掺杂的氧化铟锡靶材比例为Yb:In(4)Sn(1)＝0.60:1.00(mol)，也即，通过调 整以上两个靶材的溅射功率可以获得一系列镱含量的薄膜，本实施例中镱和氧化铟锡的掺杂摩尔比y分别等于0.002、0.020、0.100、0.200、0.40和0.60。
薄膜的厚度均为30nm，溅射气氛中氧含量为20％，溅射气压为0.5Pa。薄膜的成分比例通过X射线光电子能谱并结合透视电镜等表征结果进行标定，部分极少含量的薄膜通过溅射功率推理得知。
实施例6：氧化镱掺杂氧化铟锡锌薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例2的氧化镱掺杂氧化铟锡锌半导体材料经磁控溅射而成。
该组氧化镱掺杂氧化铟锡锌薄膜是利用氧化铟锡锌(ITZO,y＝0)和氧化镱掺杂的氧化铟锡锌(Yb:ITZO,y＝0.60)两个陶瓷靶材，采用共溅射的方式制备薄膜。通过调整两个靶材的溅射功率从而实现不同成分比例的薄膜制备。其中氧化铟锡锌靶材的成分比例为In 2O 3:SnO 2:ZnO＝1.5:2:5(mol)，标记为In(3)Sn(2)Zn(5)；氧化镱掺杂的氧化铟锡锌靶材比例为Yb:In(3)Sn(2)Zn(5)＝0.60:1.00(mol)，也即，通过调整以上两个靶材的溅射功率可以获得一系列镱含量的薄膜，本实施例中镱和氧化铟锡锌的掺杂摩尔比分别等于0.002、0.020、0.100、0.200、0.40和0.60。
需要指出的是，薄膜的厚度均为40nm，溅射气氛中氧含量为20％，溅射气压为0.5Pa；薄膜沉积后在高温烘箱350℃空气气氛下退火30分钟。薄膜的成分比例通过X射线光电子能谱并结合透视电镜等表征结果进行标定，部分极少含量的薄膜通过溅射功率推理得知。
实施例7：氧化镨掺杂氧化铟锡锌薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例3的氧化镨掺杂氧化铟锡锌半导体材料经磁控溅射而成。
该组氧化镨掺杂氧化铟锡锌薄膜是利用氧化铟锡锌(ITZO,y＝0)和氧化镨掺杂的氧化铟锡锌(Pr:ITZO,y＝0.60)两个陶瓷靶材，采用共溅射的方式、通过调整两个靶材的溅射功率从而实现不同成分比例的薄膜制备。其中氧化铟锡锌靶材的成分比例为In:Sn:Zn＝2:2:1(mol)，标记为In(2)Sn(2)Zn(1)；氧化镨掺杂的氧化铟锡锌靶材比例为Pr:In(2)Sn(2)Zn(1)＝0.60:1.00(mol)，也即，通过调整以上两个靶材的溅射功率可以获得一系列镨含量的薄膜，本实施例中镨和氧化铟锡锌的掺杂摩尔比y分别等于0.002、0.020、0.100、0.200、0.40和0.60。
该组氧化镨掺杂氧化铟锡锌薄膜的厚度均为30nm，溅射气氛中氧含量为20％，溅射气压为0.5Pa，衬底温度设置为室温。薄膜的成分比例通过X射线光电子能谱并结合透视电镜等表征结果进行标定，部分极少含量的薄膜通过溅射功率推理得知。
实施例8：氧化镨掺杂氧化铟锡锌薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例4的氧化镨掺杂氧化铟锡锌半导体材料经溶液法制备而成。
该组氧化镨掺杂氧化铟锡锌薄膜是通过溶液法制备，具体制备方式如下：
(1)首先，按比例称取一定量的硝酸铟、氯化锡和硝酸锌(三者原子摩尔比为In:Sn:Zn＝4:3:3mol)，配置氧化铟锡锌基体溶液，标记为In(4)Sn(3)Zn(3)，即y＝0；然后再根据具体的实验需要掺入一定量的硝酸镨，配置不同镨含量的氧化镨掺杂氧化铟锡锌混合溶液；本实施例中，镨和氧化铟锡锌的掺杂摩尔比y分别等于0.002、0.020、0.100、0.200、0.40和0.60。其次，分别在各混合溶液 中加入乙醇胺、醋酸和溶剂乙二醇单甲醚，于常温下搅拌12h，静置老化12h，过滤得到前驱体溶液(淡黄色透明溶液，其中铟、锡、锌和镨的总浓度为0.06mol/L，乙醇胺浓度为1.2mol/L，醋酸浓度为1.3mol/L)；
(2)将需要制备有源层的衬底先用UV处理30min，提高表面黏附力，然后将片子放在旋涂机上，使用移液枪移取60μL步骤(1)得到的前驱体溶液，滴涂在片子上，静止20s；启动旋涂机，前期转速为500rpm，时间为3s，后期转速为3000rpm，时间为40s，使前驱体溶液均匀涂覆在片子上；然后先在120℃下前烘退火10min，再在500℃下后烘退火120min，得到镨掺杂的氧化铟锡锌薄膜(命名为Pr:ITZO)，薄膜厚度均为40nm。
实施例9：薄膜晶体管
一组薄膜晶体管，采用刻蚀阻挡型结构，其结构示意图如图1所示，设置有：基板01、位于基板01之上的栅极02、位于基板01和栅极02之上的栅绝缘层03、覆盖在栅绝缘层03上表面并与栅极02对应的有源层04、刻蚀阻挡层05、相互间隔并与有源层04的两端电性相连的源极06-1和漏极06-2以及钝化层07。
其中，有源层04为实施例5所述的薄膜形成的有源层04；
基板01为玻璃衬底，其上覆盖有缓冲层氧化硅；栅极02的材料为磁控溅射方式制备的钼铝钼(Mo/Al/Mo)金属叠层结构，厚度为50/200/50nm；
栅绝缘层03为化学气相沉积方式制备的氮化硅(Si 3N 4)和氧化硅(SiO 2)的叠层，厚度为250/50nm；其中氮化硅在下层和栅极02接触，氧化硅在上层和有源层04接触。
刻蚀阻挡层05和钝化层07的材料为化学气相沉积方式制备的氧化硅(SiO 2)薄膜，厚度均为300nm，沉积温度为250℃。
源极06-1以及漏极06-2的材料为金属钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
实施例10：薄膜晶体管
一组薄膜晶体管，采用刻蚀阻挡型结构，其结构示意图如图1所示，设置有：基板01、位于基板01之上的栅极02、位于基板01和栅极02之上的栅绝缘层03、覆盖在栅绝缘层03上表面并与栅极02对应的有源层04、刻蚀阻挡层05、相互间隔并与有源层04的两端电性相连的源极06-1和漏极06-2、钝化层07。
其中，有源层04的薄膜为实施例6所述的薄膜；
基板01为玻璃衬底，其上覆盖有缓冲层氧化硅。栅极02的材料为磁控溅射方式制备的钼铝钼(Mo/Al/Mo)金属叠层结构，厚度为50/200/50nm。
栅绝缘层03为化学气相沉积方式制备的氮化硅(Si 3N 4)和氧化硅(SiO 2)的叠层，厚度为250/50nm；其中氮化硅在下层和栅极02接触，氧化硅在上层和有源层04接触。
刻蚀阻挡层05和钝化层07的材料为化学气相沉积方式制备的氧化硅(SiO 2)薄膜，厚度均为300nm，沉积温度为230℃。
源极06-1以及漏极06-2的材料为金属钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
实施例11：薄膜晶体管
一组薄膜晶体管，为背沟道刻蚀型结构，其结构示意图如图2所示，设置 有：基板01、位于基板01之上的栅极02、位于基板01和栅极02之上的栅绝缘层03、覆盖在栅绝缘层03上表面并与栅极02对应的有源层04、相互间隔并与有源层04的两端电性相连的源极06-1和漏极06-2、钝化层07。
基板01为硬质无碱玻璃衬底，其上覆盖有缓冲层氧化硅。
栅极02的材料为磁控溅射方式制备的金属钼/铝/钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
栅绝缘层03为化学气相沉积方式制备的氮化硅(Si 3N 4)和氧化硅(SiO 2)的叠层，厚度为250/50nm，其中氮化硅在下层和栅极02接触，氧化硅在上层和有源层04接触。
有源层04为实施例7得到的薄膜；
源极06-1以及漏极06-2的材料为金属钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm，其采用商用的铝酸基刻蚀液进行图案化，由于本发明的有源层对强酸有良好的抗刻蚀特性，其对有源层04的损伤较小，能实现优异的刻蚀选择比；而且无明显的刻蚀残余。
钝化层07的材料为化学气相沉积方式制备的氧化硅(SiO 2)，厚度为300nm，沉积温度为250℃。
实施例12：薄膜晶体管
一组薄膜晶体管，为自对准型结构，其结构示意图如图3所示，设置有：基板01、缓冲层08、有源层04、位于有源层04之上的栅绝缘层03以及栅极02、覆盖在有源层04和栅极02上表面的间隔层09、在间隔层09之上并与有源层04的两端电性相连的源极06-1和漏极06-2。
基板01为硬质玻璃衬底。
缓冲层08为等离子增强化学气相沉积方式制备的氧化硅。
有源层04为实施例8的薄膜。
栅绝缘层03为氧化硅，厚度为300nm；栅极02为磁控溅射方式制备的钼/铜(Mo/Cu)叠层结构，厚度为200/20nm。
间隔层09为的氧化硅/氮化硅的叠层结构，厚度为200/100nm。
源极06-1以及漏极06-2的材料为磁控溅射方式制备的钼/铜(Mo/Cu)叠层结构，厚度为200/20nm。
在实施例9-12中，薄膜晶体管的各功能层的材质和制备方法如下所示。
本发明中的基板没有特别限制，可以使用本领域中公知的基板。如：硬质的碱玻璃、无碱玻璃、石英玻璃、硅基板等；亦可为可弯曲的聚酰亚胺(PI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚苯乙烯(PS)、聚矾醚(PES)或者金属薄片等。
本发明中的栅极材料没有特别限定，其可在本领域公知的材料中任意选取。如：透明导电氧化物(ITO、AZO、GZO、IZO、ITZO、FTO等)、石墨烯、金属(Mo、Al、Cu、Ag、Ti、Au、Ta、Cr、Ni等)及其合金、以及金属和氧化物(ITO/Ag/ITO、IZO/Ag/IZO等)、金属和金属叠设(Mo/Al/Mo、Ti/Al/Ti等)形成的复合导电薄膜。
栅极薄膜的制备方法可以是溅射法、电镀、热蒸发和其他的沉积方式，优选溅射沉积方式，因为该方式制备的薄膜和基板的粘附性好、均匀性优异、可以大面积制备。
这里，具体用哪种结构的栅极需要根据所需要达到的技术参数而定，如透 明显示中需要用到透明电极，其可由单层的ITO作为栅极，亦可由ITO/Ag/ITO作为栅极。另外，特殊领域的应用中需要有高温工艺，那栅电极可以选择可以抵抗高温的金属合金薄膜。
本发明中的栅绝缘层材料没有特别限定，其可在本领域公知的材料中任意选取。如：氧化硅、氮化硅、氧化铝、氧化钽、氧化铪、氧化钇、以及高分子有机膜层等。
需要指出的是，这些栅绝缘层薄膜的组分可以与理论上的化学计量比不一致。另外，栅绝缘层可以是多种绝缘膜叠设而成，一方面形成更好的绝缘特性，另一方面可以改善有源层和栅绝缘层的界面特性。而且，该栅绝缘层的制备方式多样，可以是物理气相沉积、化学气相沉积、原子层沉积、激光沉积、阳极氧化或溶液法等方式制备。
本申请提供的有源层的厚度范围可以选自5nm至100nm，优选为20-40nm。形成有源层的金属氧化物半导体薄膜的载流子浓度小于5×10 19cm -3。
有源层薄膜的图案化工艺采用光刻工艺、并结合湿法刻蚀的方式进行。湿法刻蚀采用的刻蚀液包括：磷酸、硝酸和冰醋酸的混合液，商用的草酸基刻蚀液，稀盐酸刻蚀液，以及氢氟酸等刻蚀液。
源漏电极薄膜的图案化工序采用光刻工艺、并结合湿法或干法的刻蚀方式进行。湿法刻蚀采用的刻蚀液包括：磷酸、硝酸和冰醋酸的混合液或者基于双氧水的混合液。干法刻蚀示例性的，可以选择等离子刻蚀工艺，刻蚀气体包括氯基或氟基气体。
掺杂型金属氧化物半导体采用真空磁控溅射工艺过程中，可选单靶材溅射或多靶材共溅射，优选为单靶材溅射。
因为单靶材溅射可以提供重复性更好、更稳定的薄膜，而且薄膜的微观结 构更易控制；而不至于像共溅射薄膜中，溅射粒子在重新组合的过程中会受到更多因素的干扰。
真空溅射沉积过程中，电源可以选取射频(RF)溅射、直流(DC)溅射或交流(AC)溅射，优选工业中常用的交流溅射。
溅射沉积过程中，溅射气压为0.1Pa-10Pa可选，优选为0.2Pa-0.7Pa。
溅射气压太低时，无法维持稳定的辉光溅射；溅射气压太高时，溅射粒子在向基板沉积的过程中受到的散射明显增加，能量损耗增加，到达基板后动能降低，形成的薄膜缺陷增加，从而严重影响器件的性能。
溅射沉积过程中，氧分压为0-1Pa可选，优选为0.001-0.5Pa，更优选为0.01-0.1Pa。氧体积占比优选为0.1-0.5，更优选为0.2-0.3。
通常而言，溅射制备氧化物半导体的过程中，氧分压对薄膜的载流子浓度有着直接的影响，而且会引入一些氧空位相关的缺陷。过低的氧含量，可能会造成薄膜中氧严重失配，载流子浓度增加；而过高的氧空位会引起较多的弱结合键，降低器件的可靠性。
溅射沉积过程中，衬底温度优选为室温至300℃，更优选为200-300℃。
有源层薄膜沉积的过程中，一定的衬底温度可以有效改善溅射粒子到达基板后的结合方式，降低弱结合键的存在几率，提升器件的稳定性。当然，这一效果亦可以通过后续的退火处理等工艺来实现同样的功效。
有源层的厚度为2-100nm可选，优选为5-50nm，更优选为20-40nm。
本发明中的源漏电极材料没有特别限定，在不影响实现各种所需结构器件的前提下其可在本领域公知的材料中任意选取。如：透明导电氧化物(ITO、AZO、GZO、IZO、ITZO、FTO等)、石墨烯、金属(Mo、Al、Cu、Ag、Ti、Au、Ta、Cr、Ni等)及其合金、以及金属和氧化物(ITO/Ag/ITO、IZO/Ag/IZO等)、 金属和金属叠设(Mo/Al/Mo、Ti/Al/Ti等)形成的复合导电薄膜。
源漏电极薄膜的制备方法可以是溅射法、热蒸发和其他的沉积方式，优选溅射沉积方式，因为该方式制备的薄膜和基板的粘附性好、均匀性优异、可以大面积制备。
这里，需要特别说明的是，在制备背沟道刻蚀型结构的器件中，源漏电极和有源层需要有合适的刻蚀选择比，否则无法实现器件的制备。
需要特别指出的是，本发明的复合金属氧化物半导体对铝酸等强酸具有良好的抗刻蚀特性，因此在背沟道刻蚀型器件制备中源漏电极刻蚀可选择铝酸基的强酸刻蚀液，所刻蚀的源漏电极形貌完好、无刻蚀残留，器件性能优异，稳定性好。
另外，本发明实施例中的干法刻蚀是基于工业界常规的刻蚀气体(如氯基气体，氟基气体等)，其对本发明的氧化物半导体层影响甚微，所制备的器件性能优异，稳定性好。
本发明中的钝化层材料没有特别限定，其可在本领域公知的材料中任意选取。如：氧化硅、氮化硅、氧化铝、氧化钽、氧化铪、氧化钇、以及高分子有机膜层等。
需要指出的是，这些绝缘薄膜的组分可以与理论上的化学计量比不一致。另外，栅绝缘层可以是多种绝缘膜叠设而成，一方面形成更好的绝缘特性，另一方面可以改善有源层和钝化层的界面特性。而且，该钝化层的制备方式多样，可以是物理气相沉积、化学气相沉积、原子层沉积、激光沉积或溶液法等方式制备。
下面，进一步对本发明实施的薄膜晶体管制备过程中的处理工艺进行说明。
相对而言，溅射制备的薄膜由于有高能等离子体的参与，所沉积薄膜的速 率一般也较快；薄膜在沉积过程中没有足够的时间执行弛豫过程，这会造成一定比例的错位和应力残留于薄膜中。这需要后期的加热退火处理，而继续达到所需的相对稳态，改善薄膜的性能。
在本发明的实施中，退火处理大都设置在有源层沉积后，以及钝化层沉积后。一方面在有源层沉积后进行退火处理，可以有效改善有源层中的原位缺陷，提高有源层抵抗后续工艺中可能的损伤的能力。另一方面，在后续的钝化层沉积过程中，由于等离子体的参与和活性基团的改性作用，这可能需要一个“激活”的过程，进一步消除界面态和一些施主掺杂等效应。
另外，在本发明的实施中，处理的方式可以不仅仅是加热处理，可以包括等离子体处理界面(如栅绝缘层/半导体界面，有源层/钝化层界面等)。
通过上述的处理工艺可以有效改善器件的性能，提高器件的稳定性。
对于实施例9和10的薄膜晶体管，可以为仅包括基板、栅极、栅绝缘层、有源层、刻蚀阻挡层、源极和漏极、钝化层的封闭结构，也可以进一步包括平坦层、反射电极、像素定义层等，还可以与其它器件集成等。
对于实施例11的薄膜晶体管，可以为仅包括基板、栅极、栅绝缘层、有源层、源极和漏极、钝化层的封闭结构，也可以进一步包括平坦层、反射电极、像素定义层等，还可以与其它器件集成等。
对于实施例12的薄膜晶体管，可以为仅包括基板、有源层、栅绝缘层、栅极、间隔层、源极和漏极的封闭结构，也可以进一步包括钝化层、以及像素定义层等，还可以与其它器件集成等。
性能检测与效果测试
1、光响应特征表征
采用商用白色LED光源，以5000nits的光照强度，照射实施例9-12的薄膜晶体管器件的有源层，通过评估光照和无光照条件下器件的转移特性，提取器件开启电压的变化情况来评估其强弱；其中，器件开启电压定义为源漏电极两端电流为10 -9A时所对应的栅极电压。光响应特征用光照和无光照条件下器件开启电压变化幅度△V on表示，值大表明其光生电流特性强，反之则弱。
2、负偏压光照稳定性表征
采用商用白色LED光源，以5000nits的光照强度，照射实施例9-12的薄膜晶体管器件的有源层04，同时在器件的栅极加上-30V的电压，源漏电极两端加0V偏压；通过间隔一段时间后测试器件的转移特性曲线可以得到器件在光照射下的负向偏压稳定性特性。器件特性变化幅度大表明其稳定性差，反之则优。
3、光致发光光谱和寿命测试
从原理上讲，光照射到样品上，被样品吸收，产生光激发过程。光激发导致电子跃迁到较高的激发态，然后在驰豫过程后释放能量，电子回到较低的能级。该过程中的光辐射或者发光就称为光致发光，即PL。采用商用的PL测试系统对本发明中未掺杂和掺杂的薄膜样品进行PL表征，探索光照后薄膜中光生载流子的输运情况。另外，通过对其寿命进行测试表征，进一步评估其复合机制。
实施例9的薄膜晶体管组器件1-7的具体参数和器件性能如下表所示，另外当y＝0.10时器件的光生电流特性和负偏压光照稳定性如图4(a)和4(b)所示。
表1
Figure PCTCN2020114043-appb-000001
实施例10的薄膜晶体管组器件1-7的具体参数和器件性能如下表所示，另外当y＝0.10时器件的光生电流特性和负偏压光照稳定性如图5(a)和5(b)所示。
表2
Figure PCTCN2020114043-appb-000002
实施例11的薄膜晶体管组器件1-3的具体参数和器件性能如下表所示，另外当y＝0.10时器件的光生电流特性和负偏压光照稳定性如图6(a)和6(b)所示。
表3
Figure PCTCN2020114043-appb-000003
实施例12的薄膜晶体管组器件1-7的具体参数和器件性能如下表所示，另外当y＝0.10时器件的光生电流特性和负偏压光照稳定性如图7(a)和7(b)所示。
表4
Figure PCTCN2020114043-appb-000004
由表1-4可知，稀土氧化物的掺入对器件性能有非常明显的影响，未掺入稀土氧化物的器件(对应y＝0)具有相对较高的迁移率，较小的亚阈值摆幅和较负的阈值电压，但是其光生电流特性非常强，即在有光照射条件下器件特性发生 非常明显的变化，表现在阈值电压负向漂移，亚阈值摆幅退化严重。但是，在掺入一定量的氧化镱或氧化镨后器件的光生电流特性得到了明显的抑制。当然，随着镱或镨含量的增加，器件的迁移率等特性也进一步退化，△V on减小，光生电流特性进一步改善。当过量的镱或镱掺入后，器件的迁移率明显退化，虽然器件的光生电流特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
从表1-4中可知，稀土氧化物掺入金属氧化物半导体的摩尔比，即y值，与阈值电压呈、亚阈值摆幅、稳定性呈正相关，与迁移率、电流开关比、光生电流特征呈负相关；
根据图4-7可知，在掺入一定量的稀土氧化镨或氧化镱后，使镨或镱的掺杂摩尔比为0.10:1，器件的光生电流特性和负偏压光照稳定性都非常优异，极大地提升了其在实际应用中的潜力。
图8为对本发明中实施例7中的未掺杂(y＝0)和掺杂(y＝0.1)镨的氧化铟锡锌薄膜进行PL光谱和寿命测试的表征结果。由图8(a)可知，未掺杂样品的发射光谱强度较弱，掺杂镨后强度整体进一步降低。由图8(b)可知，根据其寿命测试结果表明，载流子寿命未有明显变化，都为几个纳秒。以上可推测出薄膜中载流子的驰豫过程主要为非辐射跃迁的复合过程，也即薄膜中存在光生载流子快速复合中心。
从综合性能来考虑，从表1可知，氧化镱掺入氧化铟锡半导体薄膜形成的有源层中，当y为0.02-0.40时，器件的综合性能较佳，更优地，当y为0.02-0.20时，器件的综合性能更佳，当y为0.10-0.20时，器件的综合性能最佳；即当掺杂比在0.10-0.20时，在光照条件下，器件的阈值电压几乎不发生变化，表面优 异的光照稳定性。
由表2可知，氧化镱掺杂氧化铟锡锌半导体薄膜形成的有源层中，当y为0.02-0.40时，器件的综合性能较佳，更优地，当y为0.02-0.20时，器件的综合性能更佳，当y为0.10-0.20时，器件的综合性能最佳；
由表3可知，氧化镨掺杂氧化铟锡锌半导体薄膜形成的有源层中，当y为0.02-0.40时，器件的综合性能较佳，当y为0.02-0.20时，器件的综合性能更佳，当y为0.10-0.20时，器件的综合性能最佳；需要说明是，随着氧化镨的掺入，器件的亚阈值摆幅有较明显的增加，表现为器件转移曲线的亚阈值区域有“变缓”的趋势；特别是在低载流子的基体材料中表现得更为明显。表明在有源层材料的导带底附近有新的“陷阱”产生，结合材料的相关测试表征表明，其对光生载流子的“湮灭”作用是该材料光生特性改善的主要原因。
由表4可知，氧化镨掺杂氧化铟锡锌半导体薄膜形成的有源层中，当y为0.02-0.40时，器件的综合性能较佳，当y为0.02-0.20时，器件的综合性能更佳，当y为0.10-0.20时，器件的综合性能最佳。
总的来说，本发明中，稀土氧化物掺杂入氧化铟锡或氧化铟锡锌中的摩尔比优选为0.02-0.40，更优选的为0.02-0.20，最优选的为0.10-0.20。在最优选的状态下，器件的阈值电压低于2V，亚阈值摆幅低于0.40V/decade，电流开关比在10 7至10 9数量级之间，光生电流特征弱，稳定性优异。
实施例9-12得到的薄膜晶体管可以应用于显示面板，该薄膜晶体管用于驱动显示面板中的显示单元。或是应用于探测器，该薄膜晶体管用于驱动探测器的探测单元。
上述实施方式仅为本发明的优选实施方式，不能以此来限定本发明保护的 范围，本领域的技术人员在本发明的基础上所做的任何非实质性的变化及替换均属于本发明所要求保护的范围。

Claims (10)

  1. 掺杂型金属氧化物半导体，其特征在于，该掺杂型金属氧化物半导体为掺杂有稀土氧化物的氧化铟锡或氧化铟锡锌；
    所述稀土氧化物为氧化镨和/或氧化镱；镨和/或镱与氧化铟锡或氧化铟锡锌的掺杂摩尔比为0.002-0.4:1；
    所述掺杂型金属氧化物半导体存在光生载流子快速复合中心。
  2. 如权利要求1所述的掺杂型金属氧化物半导体，其特征在于，所述氧化铟锡中，In和Sn的摩尔比为2-5:1。
  3. 如权利要求1所述的掺杂型金属氧化物半导体，其特征在于，所述氧化铟锡锌中，In、Sn、Zn三种金属元素的原子比例关系如下：0.2≤In/(In+Sn+Zn)≤0.8，0.2≤Sn/(In+Sn+Zn)≤0.4，0≤Zn/(In+Sn+Zn)≤0.5。
  4. 如权利要求1所述的掺杂型金属氧化物半导体，其特征在于，镨和/或镱与氧化铟锡或氧化铟锡锌的掺杂摩尔比为0.02-0.40:1。
  5. 薄膜晶体管，其特征在于，包括有源层，所述有源层由如权利要求1-4任一项所述的掺杂型金属氧化物半导体经物理气相沉积工艺、化学气相沉积工艺、原子层沉积工艺、激光沉积工艺或者溶液法制备而成；
    所述薄膜晶体管在光照和非光照条件下开启电压变化△V on量小于2V。
  6. 如权利要求5所述的薄膜晶体管，其特征在于，所述有源层经磁控溅射工艺制备而成，溅射气压为0.1-0.6Pa，溅射氛围中氧气体积占比为10-50％，衬底温度为室温至300℃。
  7. 如权利要求5所述的薄膜晶体管，其特征在于，还包括基板、栅极、栅绝缘层、源漏极和钝化层，所述薄膜晶体管采用刻蚀阻挡型结构或自对准型结 构。
  8. 如权利要求7所述的薄膜晶体管，其特征在于，所述钝化层为氧化硅薄膜，或氮化硅和氧化硅组成的叠层结构。
  9. 如权利要求5所述的薄膜晶体管，其特征在于，还包括基板、栅极、栅绝缘层、源漏极和钝化层，所述薄膜晶体管采用背沟道刻蚀型结构，采用铝酸基刻蚀液。
  10. 如权利要求5-9任一项所述的薄膜晶体管在显示面板或探测器中的应用。
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