WO2022062454A1 - 一种金属氧化物半导体及薄膜晶体管与应用 - Google Patents

一种金属氧化物半导体及薄膜晶体管与应用 Download PDF

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WO2022062454A1
WO2022062454A1 PCT/CN2021/096780 CN2021096780W WO2022062454A1 WO 2022062454 A1 WO2022062454 A1 WO 2022062454A1 CN 2021096780 W CN2021096780 W CN 2021096780W WO 2022062454 A1 WO2022062454 A1 WO 2022062454A1
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oxide
oxide semiconductor
metal oxide
layer
thin film
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PCT/CN2021/096780
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French (fr)
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徐苗
徐华
李民
彭俊彪
王磊
邹建华
陶洪
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华南理工大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H01L29/247—Amorphous materials

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to materials and device structures used in the manufacture of metal oxide semiconductor thin film transistor backplanes in flat panel display and detector applications, in particular to metal oxide semiconductors and thin film transistors and their applications.
  • the indium ion (In 3+ ) has a relatively large ionic radius, which enables a higher probability of orbital overlap in the multicomponent metal oxide to ensure its efficient carrier.
  • the transport channel whose 5s orbital is the main electron transport channel.
  • Oxygen vacancies are the main reason for the deterioration of the stability of metal oxide thin film transistors.
  • the present invention provides a metal oxide semiconductor with relatively high mobility and strong photostability.
  • the metal oxide semiconductor utilizes the characteristics that the rare earth ion radius in rare earth oxides is comparable to the indium ion radius in indium oxide, and the 4f orbital electronic structure and indium ion in rare earth ions.
  • the 5s orbital can form an efficient charge conversion center to improve its electrical stability, especially under illumination.
  • Another object of the present invention is to provide a thin film transistor including the metal oxide semiconductor.
  • the third object of the present invention is to provide the application of the thin film transistor.
  • the present invention adopts the following technical scheme to realize:
  • the metal oxide semiconductor provided by the present invention is a compound semiconductor based on indium oxide that introduces rare earth oxide.
  • the characteristics of the rare earth ion radius in the rare earth oxide being equivalent to the indium ion radius in indium oxide, on the one hand, efficient doping can be ensured A solid solution is formed without phase separation, and the doping amount can reach a small amount and high efficiency; on the other hand, the doping of rare earth oxides can reduce the lattice mismatch in the film, so that the 5s orbital of indium ions can be fully overlapped;
  • the surface-shared polyhedron structure in the film is the main component, which reduces the serious carrier scattering caused by the corner-shared polyhedron structure in the pure indium oxide film, and ensures that the film has a high carrier mobility.
  • the rare earth ions are in a stable low-energy state. Due to the modulation of the Fermi level, the film has a high carrier concentration, which can effectively shield the carrier scattering effect caused by the conversion center. The electrical properties of the device were not significantly affected. Under negative bias, the electron orbital of rare earth element 4f and the 5s orbital of indium are coupled, and the rare earth ion is in an unstable activation state.
  • the conversion center can provide a fast recombination channel for photogenerated carriers, avoiding its influence on I-V characteristics and stability. Greatly improve the stability of metal oxide semiconductor devices under illumination.
  • M is one or a combination of any two or more materials selected from Zn, Ga, Sn, Ge, Sb, Al, Mg, Ti, Zr, Hf, Ta, and W.
  • the rare earth oxide RO is one or a combination of any two or more materials selected from praseodymium oxide, terbium oxide, cerium oxide, and dysprosium oxide, or the rare earth oxide RO is samarium oxide, europium oxide, and ytterbium oxide. One or any combination of two or more materials.
  • the ions with the ability to absorb electrons from strong to weak are Dy 4+ , Pr 4+ , Tb 4+ , Ce 4+ , Sm 3+ , Yb 3+ , Eu 3+ .
  • the selection of specific doping elements also needs to consider the ratio of the high valence state and the low valence state of the ion in the compound. In steady state, the higher the proportion of high-valence ions, the higher the probability of electron transfer.
  • the preferred elemental doping elements are Pr 4+ , Tb 4+ , Ce 4+ , Dy 4+ , Yb 3+ , Sm 3+ , Eu 3+ , in this order.
  • the photogenerated carrier conversion center is located at the bottom of the conduction band of the material (In 2 O 3 ) x (MO) y (RO) z to the conduction band of (In 2 O 3 ) x (MO) y (RO) z 0.8eV region below the band.
  • the metal oxide semiconductor is prepared into a film by adopting any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser deposition, reactive ion deposition, and solution method.
  • the second purpose of the present invention adopts the following technical scheme to realize:
  • a thin film transistor comprising a gate electrode, an active layer, an insulating layer between the gate electrode and the active layer, a source electrode and a drain electrode respectively electrically connected to both ends of the active layer, and
  • the spacer layer is characterized in that the active layer is the above-mentioned metal oxide semiconductor.
  • the present invention also provides a thin film transistor formed based on the active layer obtained from the metal oxide semiconductor.
  • the metal oxide semiconductor uses the rare earth ion radius in the rare earth oxide by introducing the rare earth oxide material into the indium-containing metal oxide.
  • the characteristics comparable to the indium ion radius in indium oxide and the electronic structure of the 4f orbital in the rare earth ion and the 5s orbital of the indium ion can form an efficient charge conversion center to improve its electrical stability, especially the stability under illumination.
  • the spacer layer is a structure of one of silicon oxide, silicon nitride, and silicon oxynitride thin films prepared by plasma enhanced chemical vapor deposition, or a stacked structure composed of any two or more.
  • the third purpose of the present invention adopts the following technical scheme to realize:
  • the present invention provides a metal oxide semiconductor formed by introducing a rare earth oxide into an indium-containing metal oxide, by utilizing the characteristic that the rare earth ion radius in the rare earth oxide is equivalent to that of indium ion in indium oxide, and in the rare earth ion
  • the electronic structure of the 4f orbital and the 5s orbital of the indium ion can form an efficient charge conversion center to improve its electrical stability, especially under illumination.
  • FIG. 1 is a schematic structural diagram of a thin film transistor of Embodiment 15;
  • Embodiment 16 is a schematic structural diagram of the thin film transistors of Embodiment 16, Embodiment 17, Embodiment 18 and Embodiment 21;
  • FIG. 3 is a schematic structural diagram of the thin film transistors of Embodiment 19 and Embodiment 20;
  • Fig. 4 is the light response characteristic diagram of embodiment 15;
  • Fig. 5 is the light response characteristic diagram of embodiment 16
  • Example 6 is a light response characteristic diagram of Example 17
  • Example 7 is a light response characteristic diagram of Example 18.
  • Example 8 is a light response characteristic diagram of Example 19
  • Example 9 is a light response characteristic diagram of Example 20.
  • FIG. 10 is a graph of the light response characteristic of Example 21.
  • FIG. 10 is a graph of the light response characteristic of Example 21.
  • each reference number 01, substrate; 02, buffer layer; 03, channel layer; 04, insulating layer; 05, gate; 06, spacer layer; 07-1, source electrode; 07-2, drain pole; 08, etching barrier layer.
  • Example 1 Praseodymium oxide doped indium tin zinc oxide semiconductor material
  • a group of metal oxide semiconductor materials is: indium tin zinc oxide (ITZO) is doped with praseodymium oxide as a charge conversion center to form praseodymium oxide doped indium tin zinc oxide (Pr:ITZO) semiconductors.
  • ITZO indium tin zinc oxide
  • Pr:ITZO praseodymium oxide doped indium tin zinc oxide
  • Example 2 Terbium oxide doped indium gallium zinc oxide semiconductor material
  • a group of metal oxide semiconductor materials is: doping terbium oxide in indium gallium zinc oxide (IGZO) as a charge conversion center to form terbium oxide doped indium gallium zinc oxide (Tb:IGZO) semiconductors.
  • IGZO indium gallium zinc oxide
  • Tb:IGZO terbium oxide doped indium gallium zinc oxide
  • Example 3 Ceria Doped Indium Oxide Semiconductor Materials
  • a group of metal oxide semiconductor materials is: indium oxide (In 2 O 3 ) is doped with cerium oxide as a charge conversion center to form indium cerium oxide semiconductor materials.
  • Example 4 Dysprosium oxide doped indium oxide semiconductor material
  • a group of metal oxide semiconductor materials is: indium oxide (In 2 O 3 ) is doped with dysprosium oxide as a charge conversion center to form indium and dysprosium oxide semiconductor materials.
  • Example 5 Samarium oxide doped indium zinc oxide semiconductor material
  • a group of metal oxide semiconductor materials is: indium zinc oxide (IZO) is doped with samarium oxide as a charge conversion center to form a semiconductor material of samarium oxide doped indium zinc oxide (Sm:IZO) .
  • IZO indium zinc oxide
  • Sm:IZO samarium oxide doped indium zinc oxide
  • Example 6 Europium oxide doped indium zinc oxide semiconductor material
  • a group of metal oxide semiconductor materials is: indium zinc oxide (IZO) is doped with europium oxide as a charge conversion center to form a semiconductor material of europium oxide doped indium zinc oxide (Eu:IZO) .
  • IZO indium zinc oxide
  • Eu:IZO europium oxide doped indium zinc oxide
  • Example 7 Ytterbium oxide doped indium oxide semiconductor material
  • a group of metal oxide semiconductor materials is: indium oxide (In 2 O 3 ) is doped with ytterbium oxide as a charge conversion center to form indium ytterbium oxide semiconductor materials.
  • Example 8 Praseodymium oxide doped indium tin zinc oxide thin film
  • a group of metal oxide semiconductor thin films is formed by magnetron sputtering of the praseodymium oxide doped indium tin zinc oxide semiconductor material of Example 1.
  • Example 9 Terbium oxide doped indium gallium zinc oxide thin film
  • a group of metal oxide semiconductor thin films is formed by magnetron sputtering of the terbium oxide doped indium gallium zinc oxide semiconductor material of the second embodiment.
  • a group of metal oxide semiconductor thin films, the group of metal oxide semiconductor thin films are prepared from the ceria-doped indium oxide semiconductor material of Example 3 by a solution method.
  • Example 11 Dysprosium oxide doped indium oxide thin film
  • a group of metal oxide semiconductor thin films is prepared from the dysprosium oxide-doped indium oxide semiconductor material of Example 4 by a solution method.
  • Example 12 Samarium oxide doped indium zinc oxide thin film
  • a group of metal oxide semiconductor thin films is formed by magnetron sputtering of the samarium oxide doped indium zinc oxide semiconductor material of Example 5.
  • Example 13 Europium oxide doped indium zinc oxide thin film
  • a group of metal oxide semiconductor thin films is prepared from the europium oxide doped indium zinc oxide semiconductor material of Example 6 by reactive ion deposition (Reactive-Plasma Deposition, RPD).
  • Example 14 Ytterbium Oxide Doped Indium Oxide Film
  • a group of metal oxide semiconductor thin films is prepared from the ytterbium oxide doped indium oxide semiconductor material of Example 7 by a solution method.
  • a group of thin film transistors adopts a back-channel etched structure.
  • the schematic diagram of the structure is shown in Figure 1.
  • layer 04 a channel layer 03 covering the upper surface of the insulating layer 04 and corresponding to the gate electrode 05, a source electrode 07-1 and a drain electrode 07-2 that are spaced apart from each other and electrically connected to both ends of the channel layer 03, and Spacer layer 06.
  • the substrate 01 is a hard alkali-free glass substrate covered with a buffer layer 02 of silicon oxide.
  • the material of the gate 05 is a metal copper/molybdenum (Cu/Mo) laminated structure prepared by magnetron sputtering, and the thickness is 250/20 nm.
  • the insulating layer 04 is a stack of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 250/50 nm, wherein the silicon nitride is in contact with the gate 05 in the lower layer, and the silicon oxide The upper layer is in contact with the channel layer 03 .
  • the material of the channel layer 03 is the praseodymium oxide doped indium tin zinc oxide semiconductor material of Example 1, using indium tin zinc oxide (ITZO) and praseodymium oxide doped indium oxide Gallium-zinc (Pr:ITZO) two ceramic targets are prepared by co-sputtering and adjusting the sputtering power of the two targets to achieve films with different composition ratios.
  • ITZO indium tin zinc oxide
  • Pr:ITZO praseodymium oxide doped indium oxide Gallium-zinc
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a metal copper/molybdenum (Cu/Mo) laminated structure with a thickness of 250/20nm, which is patterned with a commercial hydrogen peroxide-based etchant, which has a good effect on the channel.
  • the damage of layer 03 is small, and there is no obvious etching residue.
  • the material of the spacer layer 06 is silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 300 nm and a deposition temperature of 250°C.
  • the thin film transistor of this embodiment may be a closed structure including only a substrate 01, a gate 05, an insulating layer 04, a channel layer 03, a source electrode 07-1 and a drain electrode 07-2, and a spacer layer 06, or may further include a flat structure layers, reflective electrodes, pixel definition layers, etc., and can also be integrated with other devices.
  • the patterning process of the thin film is performed by a photolithography process combined with a wet or dry etching method.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source (the light intensity is set to 10000 nits) to illuminate the channel layer 03 of the thin film transistor device , by evaluating the transfer characteristics of the device under illumination and no-illumination conditions, and extracting the changes in the threshold voltage and sub-threshold swing of the device to evaluate its strength; a large change in the threshold voltage indicates that its photo-generated current characteristics are strong, and vice versa.
  • the incorporation of praseodymium oxide has a very significant effect on the device performance.
  • the characteristics of the lower device undergo a very significant change (threshold voltage shifts negatively, and subthreshold swing degrades severely).
  • the photogenerated current characteristics of the device were significantly suppressed after doping a certain amount of praseodymium oxide.
  • the device prepared in this example was tested for the corresponding photoresponse characteristics, where the z values were 0 and 0.04 respectively.
  • the threshold voltage of the device without praseodymium oxide was obvious. Negative shift; after doping a certain amount of praseodymium oxide, the threshold voltage of the device has almost no change; it shows excellent light stability, which corresponds to the weak photogenerated current characteristics in Table 1.
  • test results of this embodiment show that the present invention can effectively improve the photostability of the material by incorporating a certain amount of praseodymium oxide into the indium-tin-zinc oxide matrix material.
  • a group of thin film transistors adopts a top-gate self-aligned structure.
  • the schematic diagram of the structure is shown in FIG. 2 .
  • the substrate 01 is a hard glass substrate.
  • the buffer layer 02 is silicon oxide prepared by plasma enhanced chemical vapor deposition.
  • the material of the channel layer 03 is the terbium oxide doped indium gallium zinc oxide semiconductor material of the second embodiment, and the thickness is 30 nm.
  • the insulating layer 04 is silicon oxide with a thickness of 300 nm; the gate 05 is a copper/molybdenum (Cu/Mo) laminated structure prepared by magnetron sputtering with a thickness of 300/20 nm.
  • Cu/Mo copper/molybdenum
  • the spacer layer 06 is made of silicon oxide with a thickness of 300 nm.
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a copper/molybdenum (Cu/Mo) laminated structure prepared by magnetron sputtering, and the thickness is 300/20 nm.
  • the material of the channel layer 03 is the terbium oxide doped indium gallium zinc oxide semiconductor material of Example 2, using indium gallium zinc oxide (IGZO) and terbium oxide doped indium gallium oxide
  • IGZO indium gallium zinc oxide
  • Tb:IGZO Two ceramic targets of zinc
  • the thin film transistor of this embodiment may be a closed structure including only the substrate 01, the channel layer 03, the insulating layer 04, the gate electrode 05, the spacer layer 06, the source electrode 07-1 and the drain electrode 07-2, or may further include a passivation It can also integrate with other devices and so on.
  • the patterning of the thin film is performed by photolithography combined with wet or dry etching.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source to illuminate the channel layer of the thin film transistor device, and by characterizing the channel layer of the thin film transistor device under different light intensity conditions
  • the variation of the threshold voltage of the device is extracted to evaluate its strength; the threshold voltage varies greatly, indicating that its photo-generated current characteristics are strong, and vice versa.
  • the doping of terbium oxide has a very obvious effect on the device performance.
  • the photogenerated current characteristics of the device were significantly suppressed after doping a certain amount of terbium oxide.
  • the characteristics of the device such as mobility are further degraded, and the photogenerated current characteristics are further improved.
  • the mobility of the device is obviously degraded.
  • the photogenerated current characteristics of the device are extremely weak, this greatly limits its application field. Therefore, in practical applications, the relationship between the two needs to be weighed to select an appropriate amount of incorporation.
  • the device prepared in this example was tested for the corresponding photoresponse characteristics, where the y values were 0 and 0.01 respectively.
  • the threshold voltage of the device without terbium oxide doped was obvious.
  • the threshold voltage of the device has almost no change after doping a certain amount of terbium oxide; it shows excellent light stability, which corresponds to the weak photo-generated current characteristics in Table 2.
  • test results of this embodiment show that the present invention can effectively improve the photostability of the material by doping a certain amount of terbium oxide into the indium gallium zinc oxide matrix material.
  • a group of thin film transistors adopts a self-aligned structure.
  • the schematic diagram of the structure is shown in Figure 2, and is provided with: a substrate 01, a buffer layer 02, a channel layer 03, an insulating layer 04 located on the channel layer 03, and a gate 05.
  • a spacer layer 06 covering the channel layer 03 and the upper surface of the gate, and a source electrode 07-1 and a drain electrode 07-2 which are above the spacer layer 06 and are electrically connected to both ends of the channel layer.
  • the substrate 01 is a hard glass substrate.
  • the buffer layer 02 is silicon oxide prepared by plasma enhanced chemical vapor deposition.
  • the material of the channel layer 03 is the indium cerium oxide semiconductor material of Example 3, and the thickness is 20 nm.
  • the insulating layer 04 is silicon oxide with a thickness of 300 nm; the gate 05 is a molybdenum/aluminum molybdenum (Mo/Al/Mo) laminated structure prepared by magnetron sputtering with a thickness of 50/200/50 nm.
  • Mo/Al/Mo molybdenum/aluminum molybdenum
  • the spacer layer 06 is a silicon oxide film prepared by plasma-enhanced chemical vapor deposition, with a thickness of 300 nm.
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a molybdenum/aluminum molybdenum (Mo/Al/Mo) laminated structure prepared by magnetron sputtering, with a thickness of 50/200/50 nm.
  • the thin film transistor of this embodiment may be a closed structure including only the substrate 01, the channel layer 03, the insulating layer 04, the gate electrode 05, the spacer layer, the source electrode and the drain electrode, or may further include a passivation layer and a pixel definition layer etc., and can also be integrated with other devices.
  • the patterning of the thin film is performed by photolithography combined with wet or dry etching.
  • the specific parameters in this example and the performance of the prepared thin film transistor device are shown in Table 3.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source to illuminate the channel layer of the thin film transistor device, and by characterizing the device under different light intensities conditions
  • the transfer characteristic of the device is extracted by extracting the change of the threshold voltage of the device to evaluate its strength; the change of the threshold voltage is large, indicating that its photo-generated current characteristic is strong, and vice versa.
  • the doping of cerium oxide has a very significant effect on the device performance.
  • the characteristic modification of the device is obvious after doping a certain amount of ceria, because ceria can improve the bonding properties of corner-sharing in the film, and the polyhedral composition of edge-sharing increases.
  • the photogenerated current characteristics of the device were significantly suppressed.
  • the characteristics of the device such as mobility also degrade, and the photogenerated current characteristics are further improved.
  • the device prepared in this example was tested for the corresponding light response characteristics, where the z values were 0 and 0.01 respectively.
  • the threshold voltage of the device without cerium oxide was obviously The threshold voltage of the device has almost no change after a certain amount of cerium oxide is added; it exhibits excellent light stability, which corresponds to the weak photo-generated current characteristics in Table 3.
  • test results of this example show that the present invention can effectively improve the electrical properties of the device and the light stability of the material by doping a certain amount of cerium oxide into the indium oxide matrix material.
  • a group of thin film transistors adopts a self-aligned structure.
  • the schematic diagram of the structure is shown in Figure 2, and is provided with: a substrate 01, a buffer layer 02, a channel layer 03, an insulating layer 04 located on the channel layer 03, and a gate 05.
  • a spacer layer 06 covering the channel layer 03 and the upper surface of the gate, and a source electrode 07-1 and a drain electrode 07-2 which are above the spacer layer 06 and are electrically connected to both ends of the channel layer.
  • the substrate 01 is a hard glass substrate.
  • the buffer layer 02 is silicon oxide prepared by plasma enhanced chemical vapor deposition.
  • the material of the channel layer 03 is the indium dysprosium oxide semiconductor material of Example 4, and the thickness is 20 nm.
  • the insulating layer 04 is silicon oxide with a thickness of 300 nm; the gate 05 is a molybdenum/aluminum molybdenum (Mo/Al/Mo) laminated structure prepared by magnetron sputtering with a thickness of 50/200/50 nm.
  • Mo/Al/Mo molybdenum/aluminum molybdenum
  • the spacer layer 06 is a silicon oxide film prepared by plasma-enhanced chemical vapor deposition, with a thickness of 300 nm.
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a molybdenum/aluminum molybdenum (Mo/Al/Mo) laminated structure prepared by magnetron sputtering, with a thickness of 50/200/50 nm.
  • the thin film transistor of this embodiment may be a closed structure including only a substrate, a channel layer, an insulating layer, a gate electrode, a spacer layer, a source electrode and a drain electrode, or may further include a passivation layer, a pixel definition layer, etc., or Integration with other devices, etc.
  • the patterning of the thin film is performed by photolithography combined with wet or dry etching.
  • the specific parameters in this example and the performance of the prepared thin film transistor device are shown in Table 4.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source to illuminate the channel layer of the thin film transistor device, and by characterizing the device under different light intensities conditions
  • the transfer characteristic of the device is extracted by extracting the change of the threshold voltage of the device to evaluate its strength; the change of the threshold voltage is large, indicating that its photo-generated current characteristic is strong, and vice versa.
  • the incorporation of dysprosium oxide has a very significant effect on the device performance.
  • the properties of the device are significantly modified after doping a certain amount of dysprosium oxide, because dysprosium can improve the corner-shared binding properties in the film, and the edge-shared polyhedral composition increases.
  • the photogenerated current characteristics of the device were significantly suppressed.
  • the characteristics of the device such as mobility are also degraded, and the photogenerated current characteristics are further improved.
  • the mobility of the device is obviously degraded.
  • the photogenerated current characteristic of the device is extremely weak, this greatly limits its application field. Therefore, in practical applications, the relationship between the two needs to be weighed to select an appropriate amount of incorporation.
  • the device prepared in this example was tested for the corresponding light response characteristics, wherein the z values were 0 and 0.01 respectively.
  • the threshold voltage of the device without dysprosium oxide was obvious.
  • the threshold voltage of the device has almost no change after a certain amount of dysprosium oxide is added; it exhibits excellent light stability, which corresponds to the weak photogenerated current characteristics in Table 4.
  • test results of this embodiment show that the present invention can effectively improve the electrical properties of the device and the light stability of the material by doping a certain amount of dysprosium oxide into the indium oxide matrix material.
  • a group of thin film transistors adopts an etch stop type structure.
  • the schematic diagram of the structure is shown in FIG. 3 , and is provided with: a substrate 01 , a gate 05 located on the substrate 01 , and an insulating layer 04 located on the substrate 01 and the gate 05 .
  • the channel layer 03 covering the upper surface of the insulating layer 04 and corresponding to the gate electrode 05
  • the etching barrier layer 08 the source electrode 07-1 and the drain electrode 07 which are spaced apart from each other and electrically connected to both ends of the channel layer 03 -2, and the spacer layer 06.
  • the substrate 01 is a glass substrate covered with a buffer layer of silicon oxide.
  • the material of the gate 05 is a molybdenum-aluminum-molybdenum (Mo/Al/Mo) metal stack structure prepared by magnetron sputtering, with a thickness of 50/200/50 nm.
  • Mo/Al/Mo molybdenum-aluminum-molybdenum
  • the insulating layer 04 is a stack of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 250/50 nm; wherein the silicon nitride is in contact with the gate at the lower layer, and the silicon oxide is in contact with the gate. The upper layer is in contact with the channel layer.
  • the material of the channel layer 03 is the samarium oxide doped indium zinc oxide semiconductor material of Example 5, using indium zinc oxide (IZO) and samarium oxide doped indium zinc oxide (Sm:IZO) two ceramic targets were prepared by co-sputtering. By adjusting the sputtering power of the two targets, thin films with different composition ratios can be prepared.
  • the materials of the etch stop layer 08 and the spacer layer 06 are silicon oxide (SiO 2 ) thin films prepared by chemical vapor deposition, with a thickness of 300 nm and a deposition temperature of 300°C.
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a metal molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure with a thickness of 50/200/50 nm.
  • the thin film transistor of this embodiment may be a closed structure including only a substrate, a gate electrode, an insulating layer, a channel layer, an etching barrier layer, a source electrode and a drain electrode, and a passivation layer, or may further include a flat layer, a reflective layer, and a reflective layer. Electrodes, pixel definition layers, etc., can also be integrated with other devices, etc.
  • the patterning process of the thin film is performed by a photolithography process combined with a wet or dry etching method.
  • the specific parameters in this example and the performance of the prepared thin film transistor device are shown in Table 5.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source to illuminate the channel layer of the thin film transistor device.
  • the change of the threshold voltage of the device is extracted to evaluate its strength; a large change in the threshold voltage indicates that its photo-generated current characteristics are strong, and vice versa.
  • the doping of samarium oxide has a very significant effect on the device performance.
  • the characteristics of the lower device undergo a very significant change (threshold voltage shifts negatively, and subthreshold swing degrades severely).
  • the photogenerated current characteristics of the device were significantly suppressed when a certain amount of samarium oxide was doped.
  • the device prepared in this example was tested for the corresponding photoresponse characteristics, where the z values were 0 and 0.01 respectively.
  • the threshold voltage of the device without samarium oxide was obviously Negative shift; after doping a certain amount of samarium oxide, the threshold voltage of the device has almost no change; it shows excellent light stability, which corresponds to the weak photogenerated current characteristics in Table 5.
  • test results of this embodiment show that the present invention can effectively improve the photostability of the material by adding a certain amount of samarium oxide into the indium zinc oxide matrix material.
  • a group of thin film transistors adopts an etch stop type structure.
  • the schematic diagram of the structure is shown in FIG. 3 , and is provided with: a substrate 01 , a gate 05 located on the substrate 01 , and an insulating layer 04 located on the substrate 01 and the gate 05 .
  • the channel layer 03 covering the upper surface of the insulating layer 04 and corresponding to the gate electrode 05
  • the etching barrier layer 08 the source electrode 07-1 and the drain electrode 07 which are spaced apart from each other and electrically connected to both ends of the channel layer 03 -2, and the spacer layer 06.
  • the substrate 01 is a glass substrate covered with a buffer layer of silicon oxide.
  • the material of the gate 05 is a molybdenum-aluminum-molybdenum (Mo/Al/Mo) metal stack structure prepared by magnetron sputtering, with a thickness of 50/200/50 nm.
  • Mo/Al/Mo molybdenum-aluminum-molybdenum
  • the insulating layer 04 is a stack of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 250/50 nm; wherein the silicon nitride is in contact with the gate at the lower layer, and the silicon oxide is in contact with the gate. The upper layer is in contact with the channel layer.
  • the material of the channel layer 03 is the europium oxide doped indium zinc oxide semiconductor material of Example 6, and the corresponding indium zinc oxide (IZO) is used to dope different contents of europium oxide to prepare corresponding materials. Seven different proportions of ceramic targets.
  • the materials of the etch stop layer 08 and the spacer layer 06 are silicon oxide (SiO 2 ) thin films prepared by chemical vapor deposition, with a thickness of 300 nm and a deposition temperature of 300°C.
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a metal molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure with a thickness of 50/200/50 nm.
  • the thin film transistor of this embodiment may be a closed structure including only a substrate 01, a gate electrode, an insulating layer, a channel layer, an etching barrier layer, a source electrode and a drain electrode, and a passivation layer, or may further include a flat layer, Reflective electrodes, pixel definition layers, etc., can also be integrated with other devices, etc.
  • the patterning process of the thin film is performed by a photolithography process combined with a wet or dry etching method.
  • the specific parameters in this example and the performance of the prepared thin film transistor device are shown in Table 6.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source to illuminate the channel layer of the thin film transistor device.
  • the change of the threshold voltage of the device is extracted to evaluate its strength; a large change in the threshold voltage indicates that its photo-generated current characteristics are strong, and vice versa.
  • the doping of europium oxide has a very obvious effect on the device performance.
  • the characteristics of the lower device undergo a very significant change (threshold voltage shifts negatively, and subthreshold swing degrades severely).
  • the photogenerated current characteristics of the device were significantly suppressed when a certain amount of europium oxide was doped.
  • the characteristics of the device such as mobility are further degraded, and the photogenerated current characteristics are further improved.
  • the device prepared in this example was tested for the corresponding light response characteristics, wherein the z values were 0 and 0.01 respectively.
  • the threshold voltage of the device without europium oxide doped was obvious. Negative shift; and after doping a certain amount of europium oxide, the threshold voltage of the device has almost no change; it shows excellent light stability, which corresponds to the weak photo-generated current characteristics in Table 6.
  • test results of this embodiment show that the present invention can effectively improve the photostability of the material by incorporating a certain amount of europium oxide into the indium zinc oxide matrix material.
  • a group of thin film transistors adopts a self-aligned structure.
  • the schematic diagram of the structure is shown in Figure 2, and is provided with: a substrate 01, a buffer layer 02, a channel layer 03, an insulating layer 04 located on the channel layer 03, and a gate 05.
  • a spacer layer 06 covering the channel layer 03 and the upper surface of the gate, and a source electrode 07-1 and a drain electrode 07-2 which are above the spacer layer 06 and are electrically connected to both ends of the channel layer.
  • the substrate 01 is a hard glass substrate.
  • the buffer layer 02 is silicon oxide prepared by plasma enhanced chemical vapor deposition.
  • the material of the channel layer 03 is the indium dysprosium oxide semiconductor material of Example 7, and the thickness is 20 nm.
  • the insulating layer 04 is silicon oxide with a thickness of 300 nm; the gate 05 is a molybdenum/aluminum molybdenum (Mo/Al/Mo) laminated structure prepared by magnetron sputtering, with a thickness of 50/200/50 nm.
  • Mo/Al/Mo molybdenum/aluminum molybdenum
  • the spacer layer 06 is a silicon oxide film prepared by plasma enhanced chemical vapor deposition, and the thickness is 300 nm.
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a molybdenum/aluminum molybdenum (Mo/Al/Mo) laminated structure prepared by magnetron sputtering, with a thickness of 50/200/50 nm.
  • the thin film transistor of this embodiment may be a closed structure including only a substrate, a channel layer, an insulating layer, a gate electrode, a spacer layer, a source electrode and a drain electrode, or may further include a passivation layer, a pixel definition layer, etc., or Integration with other devices, etc.
  • the patterning of the thin film is performed by photolithography combined with wet or dry etching.
  • the specific parameters in this example and the performance of the prepared thin film transistor device are shown in Table 7.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source to illuminate the channel layer of the thin film transistor device, and by characterizing the device under different light intensities conditions
  • the transfer characteristic of the device is extracted by extracting the change of the threshold voltage of the device to evaluate its strength; the change of the threshold voltage is large, indicating that its photo-generated current characteristic is strong, and vice versa.
  • the doping of ytterbium oxide has a very obvious effect on the device performance.
  • the properties of the device are significantly modified after doping a certain amount of ytterbium oxide, because ytterbium can improve the corner-shared binding properties in the film, and the edge-shared polyhedral composition increases.
  • the photogenerated current characteristics of the device were significantly suppressed.
  • the device prepared in this example was tested for the corresponding light response characteristics, wherein the z values were 0 and 0.01 respectively.
  • the threshold voltage of the device without ytterbium oxide was obviously
  • the threshold voltage of the device has almost no change after a certain amount of ytterbium oxide is added; it shows excellent light stability, which corresponds to the weak photo-generated current characteristics in Table 7.
  • test results of this embodiment show that the present invention can effectively improve the electrical properties of the device and the light stability of the material by doping a certain amount of ytterbium oxide into the indium oxide matrix material.
  • the thickness of the channel layer is 30 nm
  • the oxygen content in the sputtering atmosphere is 20%
  • the sputtering gas pressure is 0.5Pa
  • the substrate temperature is set to room temperature; the film was annealed in a high temperature oven at 350°C for 30 minutes before patterning.
  • the composition ratio of the thin film was calibrated by X-ray photoelectron spectroscopy combined with the characterization results of XRD, and some thin films with very little content were known by sputtering power inference.
  • a display panel includes the thin film transistors in the above-mentioned embodiments 15-21, and the thin film transistors are used to drive display units in the display panel.
  • a detector includes the thin film transistors in the above-mentioned embodiments 15-21, and the thin film transistors are used to drive the detection unit of the detector.
  • the substrate in the present invention is not particularly limited, and a substrate known in the art can be used.
  • a substrate known in the art can be used.
  • the gate material in the present invention is not particularly limited, and can be arbitrarily selected from materials known in the art. Such as: transparent conductive oxides (ITO, AZO, GZO, IZO, ITZO, FTO, etc.), metals (Mo, Al, Cu, Ag, Ti, Au, Ta, Cr, Ni, etc.) and their alloys, as well as metals and oxides composite conductive films formed by metal and metal stacking (Mo/Al/Mo, Ti/Al/Ti, etc.)
  • the preparation method of the gate film can be sputtering, electroplating, thermal evaporation and other deposition methods, and the sputtering deposition method is preferred, because the film prepared by this method has good adhesion to the substrate, excellent uniformity, and can be prepared in a large area. .
  • a transparent electrode needs to be used in a transparent display, which can be a single layer of ITO as a gate electrode or ITO/Ag/ITO as a gate electrode. electrode.
  • a transparent display which can be a single layer of ITO as a gate electrode or ITO/Ag/ITO as a gate electrode. electrode.
  • high-temperature processes are required for applications in special fields, and the gate electrode can be selected from a metal alloy film that can withstand high temperatures.
  • the material of the insulating layer in the present invention is not particularly limited, and can be arbitrarily selected from materials known in the art. Such as: silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, and polymer organic film layers.
  • the composition of these insulating films can be inconsistent with the theoretical stoichiometric ratio.
  • the insulating layer can be formed by stacking multiple insulating films, which can form better insulating properties on the one hand, and improve the interface properties between the channel layer and the insulating layer on the other hand.
  • the insulating layer can be prepared in various ways, and can be prepared by physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser deposition, anodization, or solution method.
  • the etching solution used in wet etching includes: a mixed solution of phosphoric acid, nitric acid and glacial acetic acid or a mixed solution based on hydrogen peroxide.
  • the etching rate of the metal oxide semiconductor material in the hydrogen peroxide-based etching solution is less than 1 nm/min.
  • a plasma etching process can be selected, and the etching gas includes chlorine-based or fluorine-based gas.
  • single-target sputtering or multi-target co-sputtering can be selected, preferably single-target sputtering.
  • single-target sputtering can provide more repeatable and stable films, and the microstructure of the film is more controllable; unlike co-sputtered films, the sputtered particles are subject to more factors in the process of recombination interference.
  • the power source can be selected from radio frequency (RF) sputtering, direct current (DC) sputtering or alternating current (AC) sputtering, preferably AC sputtering commonly used in the industry.
  • RF radio frequency
  • DC direct current
  • AC alternating current
  • the sputtering gas pressure is optional to be 0.1Pa to 10Pa, preferably 0.3Pa to 0.7Pa.
  • the oxygen partial pressure is optionally 0-1 Pa, preferably 0.001-0.5 Pa, more preferably 0.01-0.1 Pa.
  • the oxygen partial pressure has a direct effect on the carrier concentration of the film, and some defects related to oxygen vacancies will be introduced. Too low oxygen content may cause serious oxygen mismatch in the film and increase the carrier concentration; while too high oxygen vacancies will cause more weak bonds and reduce the reliability of the device.
  • the substrate temperature is preferably 200-300°C.
  • a certain substrate temperature can effectively improve the bonding mode of the sputtered particles after they reach the substrate, reduce the probability of weak bonding bonds, and improve the stability of the device.
  • this effect can also be achieved by subsequent processes such as annealing treatment.
  • the thickness of the channel layer is optionally 2-100 nm, preferably 5-50 nm, and more preferably 20-40 nm.
  • the source-drain electrode material in the present invention is not particularly limited, and can be arbitrarily selected from materials known in the art on the premise of not affecting the realization of various required structural devices.
  • materials known in the art on the premise of not affecting the realization of various required structural devices.
  • transparent conductive oxides ITO, AZO, GZO, IZO, ITZO, FTO, etc.
  • metals Mo, Al, Cu, Ag, Ti, Au, Ta, Cr, Ni, etc.
  • metals and oxides composite conductive films formed by metal and metal stacking Mo/Al/Mo, Ti/Al/Ti, etc.
  • the preparation method of the source-drain electrode film can be sputtering, thermal evaporation and other deposition methods, and the sputtering deposition method is preferred because the film prepared by this method has good adhesion to the substrate, excellent uniformity, and can be prepared in a large area.
  • the etching solution for wet etching in the embodiment of the present invention is an etching solution based on conventional metals in the industry (eg, hydrogen peroxide-based etching solution), mainly because a metal oxide semiconductor material of the present invention can effectively resist wet
  • the etching of hydrogen peroxide-based etching solution has a high etching selectivity ratio with metals (such as molybdenum, molybdenum alloy, molybdenum/aluminum/molybdenum, etc.), and the metal oxide semiconductor layer is basically not affected by the etching solution.
  • the prepared device has excellent performance and good stability.
  • the dry etching in the embodiments of the present invention is based on conventional etching gases in the industry (such as chlorine-based gas, fluorine-based gas, etc.), which has little effect on the oxide semiconductor layer of the present invention, and the prepared device performance Excellent and stable.
  • the material of the passivation layer in the present invention is not particularly limited, and can be arbitrarily selected from materials known in the art. Such as: silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, and polymer organic film layers.
  • the composition of these insulating films can be inconsistent with the theoretical stoichiometric ratio.
  • the insulating layer can be formed by stacking multiple insulating films, which can form better insulating properties on the one hand, and improve the interface properties between the channel layer and the passivation layer on the other hand.
  • the passivation layer can be prepared in various ways, and can be prepared by physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser deposition or solution method.
  • the film deposited by sputtering generally has a faster rate of deposition; the film does not have enough time to perform the relaxation process during the deposition process, which will cause a certain proportion of dislocation and stress. remains in the film. This requires a later thermal annealing treatment to continue to achieve the desired relative steady state and improve the properties of the film.
  • the annealing treatment is mostly arranged after the deposition of the channel layer and after the deposition of the passivation layer.
  • performing annealing treatment after the deposition of the channel layer can effectively improve the in-situ defects in the channel layer and improve the ability of the channel layer to resist possible damage in subsequent processes.
  • this may require an "activation" process to further eliminate effects such as interface states and some donor doping.
  • the treatment method may not only be heat treatment, but may include plasma treatment of interfaces (eg, insulating layer/semiconductor interface, channel layer/passivation layer interface, etc.).
  • interfaces eg, insulating layer/semiconductor interface, channel layer/passivation layer interface, etc.
  • the performance of the device can be effectively improved and the stability of the device can be improved by the above-mentioned treatment process.

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Abstract

本发明公开了一种金属氧化物半导体，其为：在含铟的金属氧化物半导体中掺入少量稀土氧化物作为光生载流子转换中心，形成(In 2O 3) x(MO) y(RO) z半导体材料。本发明通过利用稀土离子半径和铟离子半径相当的特性以及稀土离子中4f轨道和铟离子的5s轨道能形成电荷转换中心，以提高在光照下的稳定性。本发明还提供基于该金属氧化物半导体的薄膜晶体管与应用。

Description

一种金属氧化物半导体及薄膜晶体管与应用 技术领域
本发明涉及半导体制造领域，尤其涉及平板显示和探测器应用中的金属氧化物半导体薄膜晶体管背板制作所用的材料和器件结构，具体涉及金属氧化物半导体及薄膜晶体管与应用。
背景技术
对于现有的金属氧化物半导体体系中，铟离子(In 3+)由于具有相对较大的离子半径，使得在多元金属氧化物中更高几率的轨道交叠而确保了其高效的载流子传输通道，其5s轨道是主要的电子输运通道。但是，一方面，由于铟与氧成键后In-O的断键能较低，所以在单纯的氧化铟(In 2O 3)薄膜中存在大量的氧空位缺陷。而氧空位是导致金属氧化物薄膜晶体管稳定性劣化的主要原因。另一方面，常规溅射成膜的氧化铟中存在较多的晶格失配，使得薄膜的载流子迁移率较低，限制了其在高性能薄膜晶体管中的应用。通常，需要掺杂与In 3+离子数量相当的Ga 3+离子对氧空位进行调控。同时，为了保证半导体器件的性能均匀性，需要金属氧化物半导体薄膜保持非晶薄膜结构。
由于ZnO的晶体结构与In 2O 3和Ga 2O 3两种材料的晶体结构差异较大，所以在薄膜中掺入与In离子数量相当Zn离子，可以抑制材料结晶，保持薄膜的非晶结构。因此，在目前的金属氧化物半导体材料中应用最为广泛的就是IGZO(In:Ga:Zn＝1:1:1mol)。但是，IGZO亦存在一些问题：Ga 3+和Zn 2+离子的大量加入，大大稀释了In 3+的浓度，进而减少了5s轨道的交叠程度，降低了电子迁移率。
另外，IGZO等材料在靠近价带处存在大量的陷阱态。这导致了即使在光照 能量低于禁带宽度时，亦会产生光生载流子，导致当前的金属氧化物半导体存在光稳定性差的问题。
发明内容
为了克服现有技术的不足，本发明提供一种迁移率相对较高、光稳定性强的金属氧化物半导体。该金属氧化物半导体通过向含铟的金属氧化物中引入稀土氧化物材料，利用稀土氧化物中稀土离子半径和氧化铟中的铟离子半径相当的特性以及稀土离子中4f轨道电子结构和铟离子的5s轨道能形成高效的电荷转换中心，以提高其电学稳定性，特别是光照下的稳定性。
本发明的目的之二在于提供包含该金属氧化物半导体的薄膜晶体管。
本发明的目的之三在于提供该薄膜晶体管的应用。
本发明采用如下技术方案实现：
一种金属氧化物半导体，该金属氧化物半导体为：在含铟的金属氧化物MO-In 2O 3半导体中掺入少量稀土氧化物RO作为光生载流子转换中心，形成(In 2O 3) x(MO) y(RO) z半导体材料，其中，x+y+z＝1，0.5≤x＜0.9999，0≤y＜0.5，0.0001≤z≤0.2。
即本发明提供的金属氧化物半导体是基于氧化铟的复合半导体中引入稀土氧化物，通过利用稀土氧化物中稀土离子半径和氧化铟中的铟离子半径相当的特性，一方面可以确保高效掺杂形成固溶体，而不致于出现相分离的现象，而且掺杂量可以达到少量高效；另一方面稀土氧化物的掺入可以降低薄膜中的晶格失配，使得铟离子5s轨道可以充分交叠；而且薄膜中面共享的多面体结构占主要成分，降低了单纯氧化铟薄膜中角共享的多面体结构造成的载流子散射严重的情况，确保薄膜具有较高的载流子迁移率。
同时，利用稀土离子中4f轨道电子结构特点，其和铟离子的5s轨道能形成高效的电荷转换中心。在正偏压下，稀土离子处于稳定的低能态，由于费米能级的调制作用使得薄膜中具有较高的载流子浓度，可以有效屏蔽该转换中心造成的载流子散射效应，从而对器件的电性特性等未有明显的影响。在负偏压下，稀土元素4f中的电子轨道的和铟的5s轨道发生耦合，稀土离子处于不稳定的活化状态。一方面，其造成了器件关态电流的增加，而且其对载流子的散射作用增强，使得器件的亚阈值摆幅稍有增大；另一方面，当有合适的光激发出光生载流子后，光生电子会被该活化的转换中心快速“俘获”，并通过其耦合轨道以非辐射跃迁的形式使该光生载流子重新回到“基态”；同时该活化中心重新处于活化状态。因此，该转换中心，在能提供光生载流子的快速复合通道，避免其对I-V特性以及稳定性的影响。大幅提高金属氧化物半导体器件在光照下的稳定性。
进一步地，所述MO中，M为Zn、Ga、Sn、Ge、Sb、Al、Mg、Ti、Zr、Hf、Ta、W中的一种或任意两种以上材料组合。
进一步地，所述稀土氧化物RO为氧化镨、氧化铽、氧化铈、氧化镝中的一种或任意两种以上材料组合，或者，所述稀土氧化物RO为氧化钐、氧化铕、氧化镱中的一种或任意两种以上材料组合。
在稀土元素的选择中，大多数元素都倾向于失去3个电子表现为+3价。而由于Hund’rule，La 3+，Gd 3+，Lu 3+三种元素分别具有全空、半满、全满的4f轨道。因此其价态非常稳定。如果选择以上元素作为掺杂元素，会导致稀土元素4f电子轨道，在与In的5s电子轨道发生电子转移后能量升高，因此电子转移路径被阻断，不能提供光生载流子的快速复合通道。而Ce 4+，Pr 4+，Tb 4+，Dy 4+四种离子，倾向于吸收一个电子转换为3+价态。另外，还有Eu 3+，Sm 3+，Yb 3+也 可以吸收一个电子转换为2+价态。其中，吸收电子能力从强到弱的离子为依次为Dy 4+，Pr 4+，Tb 4+，Ce 4+，Sm 3+，Yb 3+，Eu 3+。但是具体掺杂元素的选择，还需要考虑离子的高价态与低价态在化合物中的比例。在稳态下，高价态离子所占比例越高，电子转移几率越高。考虑这一点，优选的元素掺杂元素依次为Pr 4+，Tb 4+，Ce 4+，Dy 4+，Yb 3+，Sm 3+，Eu 3+。
进一步地，所述光生载流子转换中心位于材料(In 2O 3) x(MO) y(RO) z的导带底至(In 2O 3) x(MO) y(RO) z的导带底下0.8eV区域。
进一步地，0.001≤z≤0.1。较优选地，0.01≤z≤0.05。
进一步地，所述金属氧化物半导体通过采用物理气相沉积工艺、化学气相沉积工艺、原子层沉积工艺、激光沉积工艺、反应离子沉积工艺、溶液法工艺中的任意一种工艺的方法制备成膜。
本发明的目的之二采用如下技术方案实现：
一种薄膜晶体管，该薄膜晶体管包括栅极、有源层、位于所述栅极和有源层之间的绝缘层、分别电性连接在所述有源层两端的源极和漏极、以及间隔层，其特征在于，所述有源层为上述所述的金属氧化物半导体。
即本发明还提供基于该金属氧化物半导体制得的有源层形成的薄膜晶体管，该金属氧化物半导体通过向含铟的金属氧化物中引入稀土氧化物材料，利用稀土氧化物中稀土离子半径和氧化铟中的铟离子半径相当的特性以及稀土离子中4f轨道电子结构和铟离子的5s轨道能形成高效的电荷转换中心，以提高其电学稳定性，特别是光照下的稳定性。
进一步地，所述间隔层为采用等离子增强化学气相沉积方式制备的氧化硅、氮化硅、氮氧化硅薄膜中的一种结构或者任意两种以上组成的叠层结构。
本发明的目的之三采用如下技术方案实现：
所述的薄膜晶体管在显示面板或探测器中的应用。
相比现有技术，本发明的有益效果在于：
本发明提供一种通过在含铟的金属氧化物中引入稀土氧化物以形成的金属氧化物半导体，通过利用稀土氧化物中稀土离子半径和氧化铟中的铟离子半径相当的特性以及稀土离子中4f轨道电子结构和铟离子的5s轨道能形成高效的电荷转换中心，以提高其电学稳定性，特别是光照下的稳定性。
附图说明
图1为实施例15的薄膜晶体管结构示意图；
图2为实施例16、实施例17、实施例18和实施例21的薄膜晶体管结构示意图；
图3为实施例19和实施例20的薄膜晶体管结构示意图；
图4为实施例15的光响应特性图；
图5为实施例16的光响应特性图；
图6为实施例17的光响应特性图；
图7为实施例18的光响应特性图；
图8为实施例19的光响应特性图；
图9为实施例20的光响应特性图；
图10为实施例21的光响应特性图。
图中，各附图标记：01、基板；02、缓冲层；03、沟道层；04、绝缘层；05、栅极；06、间隔层；07-1、源极；07-2、漏极；08、刻蚀阻挡层。
具体实施方式
下面，结合附图和具体实施方式，对本发明做进一步描述，需要说明的是，在不相冲突的前提下，以下描述的各实施例之间或各技术特征之间可以任意组合形成新的实施例。
以下是本发明具体的实施例，在下述实施例中所采用的原材料、设备等除特殊限定外均可以通过购买方式获得。
实施例1：氧化镨掺杂氧化铟锡锌半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟锡锌(ITZO)中掺入氧化镨作为电荷转换中心，形成氧化镨掺杂氧化铟锡锌(Pr:ITZO)的半导体材料。
其中，氧化铟锡锌的成分比例为In 2O 3:SnO 2:ZnO＝1.5:1:1mol，标记为In(3)Sn(1)Zn(1)；Pr:ITZO中，MO为SnO 2:ZnO＝1:1mol，其中x＝0.5，y＝0.3333，z＝0.1667。但不限于上述的比例，在其他一些实施例中，x＝0.6300，y＝0.2700，z＝0.1000，或者，x＝0.7100，y＝0.2400，z＝0.0500，或者，x＝0.7800，y＝0.2100，z＝0.0100，在此不再赘述。
实施例2：氧化铽掺杂氧化铟镓锌半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟镓锌(IGZO)中掺入氧化铽作为电荷转换中心，形成氧化铽掺杂氧化铟镓锌(Tb:IGZO)的半导体材料。
其中，氧化铟镓锌的成分比例为In 2O 3:Ga 2O 3:ZnO＝2:0.5:1mol，标记为In(4)Ga(1)Zn(1)；Tb:IGZO中，MO为Ga 2O 3:ZnO＝0.5:1mol，其中x＝0.625，y＝0.3125，z＝0.0625。但不限于上述的比例，在其他一些实施例中，x＝0.8000，y＝0.1800，z＝0.0200，或者，x＝0.8300，y＝0.1600，z＝0.0100，或者，x＝0.8550，y＝0.1400，z＝0.0050，在此不再赘述。
实施例3：氧化铈掺杂氧化铟半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟(In 2O 3)中掺入氧化铈作为电荷转换中心，形成氧化铟铈的半导体材料。
其中，x＝0.850，z＝0.150。但不限于上述的比例，在其他一些实施例中，x＝0.9000，z＝0.1000，或者，x＝0.9500，z＝0.0500，或者，x＝0.9900，z＝0.0100，在此不再赘述。
实施例4：氧化镝掺杂氧化铟半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟(In 2O 3)中掺入氧化镝作为电荷转换中心，形成氧化铟镝的半导体材料。
其中，x＝0.850，z＝0.150。但不限于上述的比例，在其他一些实施例中，x＝0.9000，z＝0.1000，或者，x＝0.9500，z＝0.0500，或者，x＝0.9900，z＝0.0100，在此不再赘述。
实施例5：氧化钐掺杂氧化铟锌半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟锌(IZO)中掺入氧化钐作为电荷转换中心，形成氧化钐掺杂氧化铟锌(Sm:IZO)的半导体材料。
其中，氧化铟锌靶材的成分比例为In 2O 3:ZnO＝2:1mol，标记为In(4)Zn(1)；Sm:IZO靶材中，其中x＝0.5715，y＝0.2857，z＝0.1428。但不限于上述的比例，在其他一些实施例中，x＝0.7000，y＝0.2000，z＝0.1000，或者，x＝0.8000，y＝0.1500，z＝0.0500，或者，x＝0.8700，y＝0.1200，z＝0.0100，在此不再赘述。
实施例6：氧化铕掺杂氧化铟锌半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟锌(IZO)中掺入氧化铕作为电荷转换中心，形成氧化铕掺杂氧化铟锌(Eu:IZO) 的半导体材料。
其中，x＝0.800，z＝0.200。但不限于上述的比例，在其他一些实施例中，x＝0.9000，z＝0.1000，或者，x＝0.9500，z＝0.0500，或者，x＝0.9900，z＝0.0100，在此不再赘述。
实施例7：氧化镱掺杂氧化铟半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟(In 2O 3)中掺入氧化镱作为电荷转换中心，形成氧化铟镱的半导体材料。
其中，x＝0.800，z＝0.200。但不限于上述的比例，在其他一些实施例中，x＝0.9000，z＝0.1000，或者，x＝0.9500，z＝0.0500，或者，x＝0.9900，z＝0.0100，在此不再赘述。
实施例8：氧化镨掺杂氧化铟锡锌薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例1的氧化镨掺杂氧化铟锡锌半导体材料经磁控溅射而成。
实施例9：氧化铽掺杂氧化铟镓锌薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例2的氧化铽掺杂氧化铟镓锌半导体材料经磁控溅射而成。
实施例10：氧化铈掺杂氧化铟薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例3的氧化铈掺杂氧化铟半导体材料采用溶液法制备而成。
实施例11：氧化镝掺杂氧化铟薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例4的氧化镝掺杂氧化铟半导体材料采用溶液法制备而成。
实施例12：氧化钐掺杂氧化铟锌薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例5的氧化钐掺杂氧化铟锌半导体材料经磁控溅射而成。
实施例13：氧化铕掺杂氧化铟锌薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例6的氧化铕掺杂氧化铟锌半导体材料采用反应离子沉积(Reactive-Plasma Deposition,RPD)的方式制备而成。
实施例14：氧化镱掺杂氧化铟薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例7的氧化镱掺杂氧化铟半导体材料采用溶液法制备而成。
实施例15：薄膜晶体管
一组薄膜晶体管，采用背沟道刻蚀型结构，其结构示意图如图1所示，设置有：基板01、位于基板01之上的栅极05、位于基板01和栅极05之上的绝缘层04、覆盖在绝缘层04上表面并与栅极05对应的沟道层03、相互间隔并与沟道层03的两端电性相连的源极07-1和漏极07-2、以及间隔层06。
其中，基板01为硬质无碱玻璃衬底，其上覆盖有缓冲层02氧化硅。
栅极05的材料为磁控溅射方式制备的金属铜/钼(Cu/Mo)叠层结构，厚度为250/20nm。
绝缘层04为化学气相沉积方式制备的氮化硅(Si 3N 4)和氧化硅(SiO 2)的叠层，厚度为250/50nm，其中氮化硅在下层和栅极05接触，氧化硅在上层和沟道层03接触。
为测试不同氧化镨含量对器件性能的影响，沟道层03的材料为实施例1的氧化镨掺杂氧化铟锡锌半导体材料，利用氧化铟锡锌(ITZO)和氧化镨掺杂的氧化铟镓锌(Pr:ITZO)两个陶瓷靶材，采用共溅射的方式、通过调整两个靶材 的溅射功率从而实现不同成分比例的薄膜制备而成。
源极07-1以及漏极07-2的材料为金属铜/钼(Cu/Mo)叠层结构，厚度为250/20nm，其采用商用的双氧水基刻蚀液进行图案化，其对沟道层03的损伤较小，而且无明显的刻蚀残余。
间隔层06的材料为化学气相沉积方式制备的氧化硅(SiO 2)，厚度为300nm，沉积温度为250℃。
本实施例的薄膜晶体管可以为仅包括基板01、栅极05、绝缘层04、沟道层03、源极07-1和漏极07-2、间隔层06的封闭结构，也可以进一步包括平坦层、反射电极、像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化工序采用光刻工艺、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表1所示，其中，光生电流特性的表征方式为采用商用白色LED光源(光强设置为10000nits)照射薄膜晶体管器件的沟道层03，通过评估光照和无光照条件下器件的转移特性，提取器件阈值电压和亚阈值摆幅等的变化情况来评估其强弱；阈值电压变化幅度大表明其光生电流特性强，反之则弱。
表1
Figure PCTCN2021096780-appb-000001
由该表1可知，氧化镨的掺入对器件性能有非常明显的影响。首先，未掺氧化镨的器件(对应z＝0)具有相对较高的迁移率，较小的亚阈值摆幅和较负的阈值电压，但是其光生电流特性非常强，即在有光照射条件下器件特性发生非常明显的变化(阈值电压负向漂移，亚阈值摆幅退化严重)。但是，在掺入一定量的氧化镨后器件的光生电流特性得到了明显的抑制。当然，随着氧化镨含量的增加，器件的迁移率等特性也进一步退化，光生电流特性进一步改善。当过量的氧化镨掺入后(如z＝0.1667)，器件的迁移率明显退化，虽然器件的光生电流特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光响应特性测试，其中，z值分别为0和0.04，如图4所示，当有光照射在器件上时，未掺氧化镨的器件阈值电压明显负向偏移；而掺入一定量的氧化镨后，器件的阈值电压几乎没有变化；表现出了优异的光照稳定性，也即对应表1中的弱光生电流特性。
本实施例的试验结果表明，本发明在氧化铟锡锌基体材料中，掺入一定量的氧化镨能有效提高材料的光稳定性。
实施例16：薄膜晶体管
一组薄膜晶体管，采用顶栅自对准型结构，其结构示意图如图2所示，设置有：基板01、缓冲层02、沟道层03、位于沟道层03之上的绝缘层04以及栅极05、覆盖在沟道层03和栅极上表面的间隔层06、在间隔层06之上并与沟道层03的两端电性相连的源极07-1和漏极07-2。
其中，基板01为硬质玻璃衬底。
缓冲层02为等离子增强化学气相沉积方式制备的氧化硅。
沟道层03的材料为实施例2的氧化铽掺杂氧化铟镓锌半导体材料，厚度为 30nm。
绝缘层04为氧化硅，厚度为300nm；栅极05为磁控溅射方式制备的铜/钼(Cu/Mo)叠层结构，厚度为300/20nm。
间隔层06为的氧化硅，厚度为300nm。
源极07-1以及漏极07-2的材料为磁控溅射方式制备的的铜/钼(Cu/Mo)叠层结构，厚度为300/20nm。
为测试不同铽含量对器件性能的影响，沟道层03的材料为实施例2的氧化铽掺杂氧化铟镓锌半导体材，利用氧化铟镓锌(IGZO)和氧化铽掺杂的氧化铟镓锌(Tb:IGZO)两个陶瓷靶材，采用共溅射的方式、通过调整两个靶材的溅射功率从而实现不同成分比例的薄膜制备。
本实施例的薄膜晶体管可以为仅包括基板01、沟道层03、绝缘层04、栅极05、间隔层06、源极07-1和漏极07-2的封闭结构，也可以进一步包括钝化层、以及像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化采用光刻、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表2所示，其中，光生电流特性的表征方式为采用商用白色LED光源照射薄膜晶体管器件的沟道层，通过表征不同光强条件下器件的转移特性，提取器件阈值电压的变化情况来评估其强弱；阈值电压变化幅度大，表明其光生电流特性强，反之则弱。
表2
Figure PCTCN2021096780-appb-000002
由该表2可知，氧化铽的掺入对器件性能有非常明显的影响。首先，未掺氧化铽的器件(对应z＝0)具有相对较高的迁移率，较小的亚阈值摆幅和较负的阈值电压，但是其光生电流特性相对较强，即使在较弱的光照条件下器件特性依然会发生变化。但是，在掺入一定量的氧化铽后器件的光生电流特性得到了明显的抑制。当然，随着氧化铽含量的增加，器件的迁移率等特性也进一步退化，光生电流特性进一步改善。当过量的氧化铽掺入后，器件的迁移率明显退化，虽然器件的光生电流特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光响应特性测试，其中，y值分别为0和0.01，如图5所示，当有光照射在器件上时，未掺氧化铽的器件阈值电压明显负向偏移，而掺入一定量的氧化铽后器件的阈值电压几乎没有变化；表现出了优异的光照稳定性，也即对应表2中的弱光生电流特性。
本实施例的试验结果表明，本发明在氧化铟镓锌基体材料中，掺入一定量的氧化铽能有效提高材料的光稳定性。
实施例17：薄膜晶体管
一组薄膜晶体管，采用自对准型结构，其结构示意图如图2所示，设置有：基板01、缓冲层02、沟道层03、位于沟道层03之上的绝缘层04以及栅极05、覆盖在沟道层03和栅极上表面的间隔层06、在间隔层06之上并与沟道层的两端电性相连的源极07-1和漏极07-2。
其中，基板01为硬质玻璃衬底。
缓冲层02为等离子增强化学气相沉积方式制备的氧化硅。
沟道层03的材料为实施例3的氧化铟铈半导体材料，厚度为20nm。
绝缘层04为氧化硅，厚度为300nm；栅极05为磁控溅射方式制备的钼/铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
间隔层06为的等离子增强化学气相沉积制备的氧化硅薄膜，厚度为300nm。
源极07-1以及漏极07-2的材料为磁控溅射方式制备的钼/铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
本实施例的薄膜晶体管可以为仅包括基板01、沟道层03、绝缘层04、栅极05、间隔层、源极和漏极的封闭结构，也可以进一步包括钝化层、以及像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化采用光刻、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表3所示，其中光生电流特性的表征方式为采用商用白色LED光源照射薄膜晶体管器件的沟道层，通过表征不同光强条件下器件的转移特性，提取器件阈值电压的变化情况来评估其强弱；阈值电压变化幅度大，表明其光生电流特性强，反之则弱。
表3
Figure PCTCN2021096780-appb-000003
由该表3可知，氧化铈的掺入对器件性能有非常明显的影响。首先，由于纯氧化铟的薄膜晶格畸变严重，因而未掺氧化铈的器件(对应z＝0)的迁移率较低，器件的亚阈值摆幅较大，而且其光生电流特性相对较强，即使在较弱的光照条件下器件特性依然会发生变化。但是，在掺入一定量的氧化铈后器件的特性改性明显，因为铈可以改善薄膜中角共享的结合特性，边共享的多面体组分增加。此外，器件的光生电流特性得到了明显的抑制。当然，随着氧化铈含量的增加，器件的迁移率等特性也随之退化，光生电流特性进一步改善。当过量的氧化铈掺入后(如z＝0.15)，器件的迁移率明显退化，虽然器件的光生电流特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光响应特性测试，其中，z值分别为0和0.01，如图6所示，当有光照射在器件上时，未掺氧化铈的器件阈值电压明显负向偏移，而掺入一定量的氧化铈后器件的阈值电压几乎没有变化；表现出了优异的光照稳定性，也即对应表3中的弱光生电流特性。
本实施例的试验结果表明，本发明在氧化铟基体材料中，掺入一定量的氧 化铈能有效改善器件的电学特性，而且能有效提高材料的光稳定性。
实施例18：薄膜晶体管
一组薄膜晶体管，采用自对准型结构，其结构示意图如图2所示，设置有：基板01、缓冲层02、沟道层03、位于沟道层03之上的绝缘层04以及栅极05、覆盖在沟道层03和栅极上表面的间隔层06、在间隔层06之上并与沟道层的两端电性相连的源极07-1和漏极07-2。
其中，基板01为硬质玻璃衬底。
缓冲层02为等离子增强化学气相沉积方式制备的氧化硅。
沟道层03的材料为实施例4的氧化铟镝半导体材料，厚度为20nm。
绝缘层04为氧化硅，厚度为300nm；栅极05为磁控溅射方式制备的钼/铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
间隔层06为的等离子增强化学气相沉积制备的氧化硅薄膜，厚度为300nm。
源极07-1以及漏极07-2的材料为磁控溅射方式制备的钼/铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
本实施例的薄膜晶体管可以为仅包括基板、沟道层、绝缘层、栅极、间隔层、源极和漏极的封闭结构，也可以进一步包括钝化层、以及像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化采用光刻、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表4所示，其中光生电流特性的表征方式为采用商用白色LED光源照射薄膜晶体管器件的沟道层，通过表征不同光强条件下器件的转移特性，提取器件阈值电压的变化情况来评估其强弱；阈值电压变化幅度大，表明其光生电流特性强，反之则弱。
表4
Figure PCTCN2021096780-appb-000004
由该表4可知，氧化镝的掺入对器件性能有非常明显的影响。首先，由于纯氧化铟的薄膜晶格畸变严重，因而未掺氧化镝的器件(对应z＝0)的迁移率较低，器件的亚阈值摆幅较大，而且其光生电流特性相对较强，即使在较弱的光照条件下器件特性依然会发生变化。但是，在掺入一定量的氧化镝后器件的特性改性明显，因为镝可以改善薄膜中角共享的结合特性，边共享的多面体组分增加。此外，器件的光生电流特性得到了明显的抑制。当然，随着氧化镝含量的增加，器件的迁移率等特性也随之退化，光生电流特性进一步改善。当过量的氧化镝掺入后(如z＝0.15)，器件的迁移率明显退化，虽然器件的光生电流特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光响应特性测试，其中，z值分别为0和0.01，如图7所示，当有光照射在器件上时，未掺氧化镝的器件阈值电压明显负向偏移，而掺入一定量的氧化镝后器件的阈值电压几乎没有变化；表现出了优异的光照稳定性，也即对应表4中的弱光生电流特性。
本实施例的试验结果表明，本发明在氧化铟基体材料中，掺入一定量的氧 化镝能有效改善器件的电学特性，而且能有效提高材料的光稳定性。
实施例19：薄膜晶体管
一组薄膜晶体管，采用刻蚀阻挡型结构，其结构示意图如图3所示，设置有：基板01、位于基板01之上的栅极05、位于基板01和栅极05之上的绝缘层04、覆盖在绝缘层04上表面并与栅极05对应的沟道层03、刻蚀阻挡层08、相互间隔并与沟道层03的两端电性相连的源极07-1和漏极07-2、以及间隔层06。
其中，基板01为玻璃衬底，其上覆盖有缓冲层氧化硅。
栅极05的材料为磁控溅射方式制备的钼铝钼(Mo/Al/Mo)金属叠层结构，厚度为50/200/50nm。
绝缘层04为化学气相沉积方式制备的氮化硅(Si 3N 4)和氧化硅(SiO 2)的叠层，厚度为250/50nm；其中氮化硅在下层和栅极接触，氧化硅在上层和沟道层接触。
为测试不同含量的氧化钐对器件性能的影响，沟道层03的材料为实施例5的氧化钐掺杂氧化铟锌半导体材料，利用氧化铟锌(IZO)和氧化钐掺杂的氧化铟锌(Sm:IZO)两个陶瓷靶材，采用共溅射的方式制备薄膜。通过调整两个靶材的溅射功率从而实现不同成分比例的薄膜制备。
刻蚀阻挡层08和间隔层06的材料为化学气相沉积方式制备的氧化硅(SiO 2)薄膜，厚度均为300nm，沉积温度为300℃。
源极07-1以及漏极07-2的材料为金属钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
另外，本实施例的薄膜晶体管可以为仅包括基板、栅极、绝缘层、沟道层、刻蚀阻挡层、源极和漏极、钝化层的封闭结构，也可以进一步包括平坦层、反 射电极、像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化工序采用光刻工艺、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表5所示，其中光生电流特性的表征方式为采用商用白色LED光源照射薄膜晶体管器件的沟道层，通过评估光照和无光照条件下器件的转移特性，提取器件阈值电压的变化情况来评估其强弱；阈值电压变化幅度大表明其光生电流特性强，反之则弱。
表5
Figure PCTCN2021096780-appb-000005
由该表5可知，氧化钐的掺入对器件性能有非常明显的影响。首先，未掺氧化钐的器件(对应z＝0)具有相对较高的迁移率，较小的亚阈值摆幅和较负的阈值电压，但是其光生电流特性非常强，即在有光照射条件下器件特性发生非常明显的变化(阈值电压负向漂移，亚阈值摆幅退化严重)。但是，在掺入一定量的氧化钐器件的光生电流特性得到了明显的抑制。当然，随着氧化钐含量的增加，器件的迁移率等特性也进一步退化，光生电流特性进一步改善。当过量的氧化钐掺入后(如z＝0.1428)，器件的迁移率明显退化，虽然器件的光生电流 特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光响应特性测试，其中，z值分别为0和0.01，如图8所示，当有光照射在器件上时，未掺氧化钐的器件阈值电压明显负向偏移；而掺入一定量的氧化钐后，器件的阈值电压几乎没有变化；表现出了优异的光照稳定性，也即对应表5中的弱光生电流特性。
本实施例的试验结果表明，本发明在氧化铟锌基体材料中，掺入一定量的氧化钐能有效提高材料的光稳定性。
实施例20：薄膜晶体管
一组薄膜晶体管，采用刻蚀阻挡型结构，其结构示意图如图3所示，设置有：基板01、位于基板01之上的栅极05、位于基板01和栅极05之上的绝缘层04、覆盖在绝缘层04上表面并与栅极05对应的沟道层03、刻蚀阻挡层08、相互间隔并与沟道层03的两端电性相连的源极07-1和漏极07-2、以及间隔层06。
其中，基板01为玻璃衬底，其上覆盖有缓冲层氧化硅。
栅极05的材料为磁控溅射方式制备的钼铝钼(Mo/Al/Mo)金属叠层结构，厚度为50/200/50nm。
绝缘层04为化学气相沉积方式制备的氮化硅(Si 3N 4)和氧化硅(SiO 2)的叠层，厚度为250/50nm；其中氮化硅在下层和栅极接触，氧化硅在上层和沟道层接触。
为测试不同含量的氧化铕对器件性能的影响，沟道层03的材料为实施例6的氧化铕掺杂氧化铟锌半导体材料，利用氧化铟锌(IZO)掺杂不同含量的氧化铕制备对应七个不同比例的陶瓷靶材。
刻蚀阻挡层08和间隔层06的材料为化学气相沉积方式制备的氧化硅(SiO 2)薄膜，厚度均为300nm，沉积温度为300℃。
源极07-1以及漏极07-2的材料为金属钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
另外，本实施例的薄膜晶体管可以为仅包括基板01、栅极、绝缘层、沟道层、刻蚀阻挡层、源极和漏极、钝化层的封闭结构，也可以进一步包括平坦层、反射电极、像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化工序采用光刻工艺、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表6所示，其中光生电流特性的表征方式为采用商用白色LED光源照射薄膜晶体管器件的沟道层，通过评估光照和无光照条件下器件的转移特性，提取器件阈值电压的变化情况来评估其强弱；阈值电压变化幅度大表明其光生电流特性强，反之则弱。
表6
Figure PCTCN2021096780-appb-000006
由该表6可知，氧化铕的掺入对器件性能有非常明显的影响。首先，未掺 氧化铕的器件(对应z＝0)具有相对较高的迁移率，较小的亚阈值摆幅和较负的阈值电压，但是其光生电流特性非常强，即在有光照射条件下器件特性发生非常明显的变化(阈值电压负向漂移，亚阈值摆幅退化严重)。但是，在掺入一定量的氧化铕器件的光生电流特性得到了明显的抑制。当然，随着氧化铕含量的增加，器件的迁移率等特性也进一步退化，光生电流特性进一步改善。当过量的氧化铕掺入后(如z＝0.2)，器件的迁移率明显退化，虽然器件的光生电流特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光响应特性测试，其中，z值分别为0和0.01，如图9所示，当有光照射在器件上时，未掺氧化铕的器件阈值电压明显负向偏移；而掺入一定量的氧化铕后，器件的阈值电压几乎没有变化；表现出了优异的光照稳定性，也即对应表6中的弱光生电流特性。
本实施例的试验结果表明，本发明在氧化铟锌基体材料中，掺入一定量的氧化铕能有效提高材料的光稳定性。
实施例21：薄膜晶体管
一组薄膜晶体管，采用自对准型结构，其结构示意图如图2所示，设置有：基板01、缓冲层02、沟道层03、位于沟道层03之上的绝缘层04以及栅极05、覆盖在沟道层03和栅极上表面的间隔层06、在间隔层06之上并与沟道层的两端电性相连的源极07-1和漏极07-2。
其中，基板01为硬质玻璃衬底。
缓冲层02为等离子增强化学气相沉积方式制备的氧化硅。
沟道层03的材料为实施例7的氧化铟镝半导体材料，厚度为20nm。
绝缘层04为氧化硅，厚度为300nm；栅极05为磁控溅射方式制备的钼/铝 钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
间隔层06为的等离子增强化学气相沉积制备的氧化硅薄膜，厚度为300nm。
源极07-1以及漏极07-2的材料为磁控溅射方式制备的钼/铝钼(Mo/Al/Mo)叠层结构，厚度为50/200/50nm。
本实施例的薄膜晶体管可以为仅包括基板、沟道层、绝缘层、栅极、间隔层、源极和漏极的封闭结构，也可以进一步包括钝化层、以及像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化采用光刻、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表7所示，其中光生电流特性的表征方式为采用商用白色LED光源照射薄膜晶体管器件的沟道层，通过表征不同光强条件下器件的转移特性，提取器件阈值电压的变化情况来评估其强弱；阈值电压变化幅度大，表明其光生电流特性强，反之则弱。
表7
Figure PCTCN2021096780-appb-000007
由该表7可知，氧化镱的掺入对器件性能有非常明显的影响。首先，由于纯氧化铟的薄膜晶格畸变严重，因而未掺氧化镱的器件(对应z＝0)的迁移率较低，器件的亚阈值摆幅较大，而且其光生电流特性相对较强，即使在较弱的光 照条件下器件特性依然会发生变化。但是，在掺入一定量的氧化镱后器件的特性改性明显，因为镱可以改善薄膜中角共享的结合特性，边共享的多面体组分增加。此外，器件的光生电流特性得到了明显的抑制。当然，随着氧化镱含量的增加，器件的迁移率等特性也随之退化，光生电流特性进一步改善。当过量的氧化镱掺入后(如z＝0.2)，器件的迁移率明显退化，虽然器件的光生电流特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光响应特性测试，其中，z值分别为0和0.01，如图10所示，当有光照射在器件上时，未掺氧化镱的器件阈值电压明显负向偏移，而掺入一定量的氧化镱后器件的阈值电压几乎没有变化；表现出了优异的光照稳定性，也即对应表7中的弱光生电流特性。
本实施例的试验结果表明，本发明在氧化铟基体材料中，掺入一定量的氧化镱能有效改善器件的电学特性，而且能有效提高材料的光稳定性。
需要指出的是，在本实施例15～21中，若没特别说明的，沟道层的厚度均为30nm，溅射气氛中氧含量为20％，溅射气压为0.5Pa，衬底温度设置为室温；薄膜在图案化前经高温烘箱350℃空气气氛下退火30分钟。薄膜的成分比例通过X射线光电子能谱并结合透视电镜等表征结果进行标定，部分极少含量的薄膜通过溅射功率推理得知。
实施例22：显示面板
一种显示面板，包括上述实施例15-21中的薄膜晶体管，薄膜晶体管用于驱动显示面板中的显示单元。
实施例23：探测器
一种探测器，包括上述实施例15-21中的薄膜晶体管，薄膜晶体管用于驱动 探测器的探测单元。
下面，对本发明实施的薄膜晶体管的各功能层做进一步的说明。
本发明中的基板没有特别限制，可以使用本领域中公知的基板。如：硬质的碱玻璃、无碱玻璃、石英玻璃、硅基板等；亦可为可弯曲的聚酰亚胺(PI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚苯乙烯(PS)、聚矾醚(PES)或者金属薄片等。
本发明中的栅极材料没有特别限定，其可在本领域公知的材料中任意选取。如：透明导电氧化物(ITO、AZO、GZO、IZO、ITZO、FTO等)，金属(Mo、Al、Cu、Ag、Ti、Au、Ta、Cr、Ni等)及其合金、以及金属和氧化物(ITO/Ag/ITO、IZO/Ag/IZO等)、金属和金属叠设(Mo/Al/Mo、Ti/Al/Ti等)形成的复合导电薄膜。
栅极薄膜的制备方法可以是溅射法、电镀、热蒸发和其他的沉积方式，优选溅射沉积方式，因为该方式制备的薄膜和基板的粘附性好、均匀性优异、可以大面积制备。
这里，具体用哪种结构的栅电极需要根据所需要达到的技术参数而定，如透明显示中需要用到透明电极，其可由单层的ITO作为栅电极，亦可由ITO/Ag/ITO作为栅电极。另外，特殊领域的应用中需要有高温工艺，那栅电极可以选择可以抵抗高温的金属合金薄膜。
本发明中的绝缘层材料没有特别限定，其可在本领域公知的材料中任意选取。如：氧化硅、氮化硅、氧化铝、氧化钽、氧化铪、氧化钇、以及高分子有机膜层等。
需要指出的是，这些绝缘薄膜的组分可以与理论上的化学计量比不一致。另外，绝缘层可以是多种绝缘膜叠设而成，一方面形成更好的绝缘特性，另一 方面可以改善沟道层和绝缘层的界面特性。而且，该绝缘层的制备方式多样，可以是物理气相沉积、化学气相沉积、原子层沉积、激光沉积、阳极氧化或溶液法等方式制备。
湿法刻蚀采用的刻蚀液包括：磷酸、硝酸和冰醋酸的混合液或者基于双氧水的混合液。金属氧化物半导体材料在双氧水基的刻蚀液中的刻蚀速率小于1nm/min。干法刻蚀示例性的，可以选择等离子刻蚀工艺，刻蚀气体包括氯基或氟基气体。
金属氧化物半导体材料采用真空磁控溅射工艺过程中，可选单靶材溅射或多靶材共溅射，优选为单靶材溅射。
因为单靶材溅射可以提供重复性更好、更稳定的薄膜，而且薄膜的微观结构更易控制；而不至于像共溅射薄膜中，溅射粒子在重新组合的过程中会受到更多因素的干扰。
真空溅射沉积过程中，电源可以选取射频(RF)溅射、直流(DC)溅射或交流(AC)溅射，优选工业中常用的交流溅射。
溅射沉积过程中，溅射气压为0.1Pa～10Pa可选，优选为0.3Pa～0.7Pa。
溅射气压太低时，无法维持稳定的辉光溅射；溅射气压太高时，溅射粒子在向基板沉积的过程中受到的散射明显增加，能量损耗增加，到达基板后动能降低，形成的薄膜缺陷增加，从而严重影响器件的性能。
溅射沉积过程中，氧分压为0～1Pa可选，优选为0.001～0.5Pa，更优选为0.01～0.1Pa。
通常而言，溅射制备氧化物半导体的过程中，氧分压对薄膜的载流子浓度有着直接的影响，而且会引入一些氧空位相关的缺陷。过低的氧含量，可能会造成薄膜中氧严重失配，载流子浓度增加；而过高的氧空位会引起较多的弱结 合键，降低器件的可靠性。
溅射沉积过程中，衬底温度优选为200～300℃。
沟道层薄膜沉积的过程中，一定的衬底温度可以有效改善溅射粒子到达基板后的结合方式，降低弱结合键的存在几率，提升器件的稳定性。当然，这一效果亦可以通过后续的退火处理等工艺来实现同样的功效。
沟道层的厚度为2～100nm可选，优选为5～50nm，更优选为20～40nm。
本发明中的源漏电极材料没有特别限定，在不影响实现各种所需结构器件的前提下其可在本领域公知的材料中任意选取。如：透明导电氧化物(ITO、AZO、GZO、IZO、ITZO、FTO等)，金属(Mo、Al、Cu、Ag、Ti、Au、Ta、Cr、Ni等)及其合金、以及金属和氧化物(ITO/Ag/ITO、IZO/Ag/IZO等)、金属和金属叠设(Mo/Al/Mo、Ti/Al/Ti等)形成的复合导电薄膜。
源漏电极薄膜的制备方法可以是溅射法、热蒸发和其他的沉积方式，优选溅射沉积方式，因为该方式制备的薄膜和基板的粘附性好、均匀性优异、可以大面积制备。
这里，需要特别说明的是，在制备背沟道刻蚀型结构的器件中，源漏电极和沟道层需要有合适的刻蚀选择比，否则无法实现器件的制备。本发明实施例中湿法刻蚀的刻蚀液是基于工业界常规金属的刻蚀液(如：双氧水基刻蚀液)，主要是因为本发明的一种金属氧化物半导体材料能有效抵抗湿法双氧水基刻蚀液的刻蚀，其和金属(如钼、钼合金、钼/铝/钼等)具有很高的刻蚀选择比，该金属氧化物半导体层基本不受刻蚀液的影响，所制备的器件性能优异，稳定性好。另外，本发明实施例中的干法刻蚀是基于工业界常规的刻蚀气体(如氯基气体，氟基气体等)，其对本发明的氧化物半导体层影响甚微，所制备的器件性能优异，稳定性好。
本发明中的钝化层材料没有特别限定，其可在本领域公知的材料中任意选取。如：氧化硅、氮化硅、氧化铝、氧化钽、氧化铪、氧化钇、以及高分子有机膜层等。
需要指出的是，这些绝缘薄膜的组分可以与理论上的化学计量比不一致。另外，绝缘层可以是多种绝缘膜叠设而成，一方面形成更好的绝缘特性，另一方面可以改善沟道层和钝化层的界面特性。而且，该钝化层的制备方式多样，可以是物理气相沉积、化学气相沉积、原子层沉积、激光沉积或溶液法等方式制备。
下面，进一步对本发明实施的薄膜晶体管制备过程中的处理工艺进行说明。
相对而言，溅射制备的薄膜由于有高能等离子体的参与，所沉积薄膜的速率一般也较快；薄膜在沉积过程中没有足够的时间执行弛豫过程，这会造成一定比例的错位和应力残留于薄膜中。这需要后期的加热退火处理，而继续达到所需的相对稳态，改善薄膜的性能。
在本发明的实施中，退火处理大都设置在沟道层沉积后，以及钝化层沉积后。一方面在沟道层沉积后进行退火处理，可以有效改善沟道层中的原位缺陷，提高沟道层抵抗后续工艺中可能的损伤的能力。另一方面，在后续的钝化层沉积过程中，由于等离子体的参与和活性基团的改性作用，这可能需要一个“激活”的过程，进一步消除界面态和一些施主掺杂等效应。
另外，在本发明的实施中，处理的方式可以不仅仅是加热处理，可以包括等离子体处理界面(如绝缘层/半导体界面，沟道层/钝化层界面等)。
通过上述的处理工艺可以有效改善器件的性能，提高器件的稳定性。
上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受上述实施例的限制，其它的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。

Claims (10)

  1. 一种金属氧化物半导体，其特征在于，该金属氧化物半导体为：在含铟的金属氧化物MO-In 2O 3半导体中掺入少量稀土氧化物RO作为光生载流子转换中心，形成(In 2O 3) x(MO) y(RO) z半导体材料，其中，x+y+z＝1，0.5≤x＜0.9999，0≤y＜0.5，0.0001≤z≤0.2。
  2. 根据权利要求1所述的金属氧化物半导体，其特征在于，所述MO中，M为Zn、Ga、Sn、Ge、Sb、Al、Mg、Ti、Zr、Hf、Ta、W中的一种或任意两种以上材料组合。
  3. 根据权利要求1所述的金属氧化物半导体，其特征在于，所述稀土氧化物RO为氧化镨、氧化铽、氧化铈、氧化镝中的一种或任意两种以上材料组合，或者，所述稀土氧化物RO为氧化钐、氧化铕、氧化镱中的一种或任意两种以上材料组合。
  4. 根据权利要求1所述的金属氧化物半导体，其特征在于，所述光生载流子转换中心位于材料(In 2O 3) x(MO) y(RO) z的导带底至(In 2O 3) x(MO) y(RO) z的导带底下0.8eV区域。
  5. 根据权利要求1所述的金属氧化物半导体，其特征在于，0.001≤z≤0.1。
  6. 根据权利要求5所述的金属氧化物半导体，其特征在于，0.01≤z≤0.05。
  7. 根据权利要求1所述的金属氧化物半导体，其特征在于，所述金属氧化物半导体通过采用物理气相沉积工艺、化学气相沉积工艺、原子层沉积工艺、激光沉积工艺、反应离子沉积工艺、溶液法工艺中的任意一种工艺的方法制备成膜。
  8. 一种薄膜晶体管，该薄膜晶体管包括栅极、有源层、位于所述栅极和有源层之间的绝缘层、分别电性连接在所述有源层两端的源极和漏极、以及间隔层，其特征在于，所述有源层为权利要求1所述的金属氧化物半导体。
  9. 根据权利要求8所述的薄膜晶体管，其特征在于，所述间隔层为采用等离子增强化学气相沉积方式制备的氧化硅、氮化硅、氮氧化硅薄膜中的一种结构或者任意两种以上组成的叠层结构。
  10. 如权利要求8所述的薄膜晶体管在显示面板或探测器中的应用。
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