WO2022105174A1 - 一种金属氧化物半导体及薄膜晶体管与应用 - Google Patents

一种金属氧化物半导体及薄膜晶体管与应用 Download PDF

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WO2022105174A1
WO2022105174A1 PCT/CN2021/096784 CN2021096784W WO2022105174A1 WO 2022105174 A1 WO2022105174 A1 WO 2022105174A1 CN 2021096784 W CN2021096784 W CN 2021096784W WO 2022105174 A1 WO2022105174 A1 WO 2022105174A1
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oxide
metal oxide
oxide semiconductor
rare earth
thin film
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PCT/CN2021/096784
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English (en)
French (fr)
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徐苗
徐华
李民
彭俊彪
王磊
邹建华
陶洪
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华南理工大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H01L29/247—Amorphous materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to materials and device structures used in the manufacture of metal oxide semiconductor thin film transistor backplanes in flat panel display and detector applications, in particular to metal oxide semiconductors and thin film transistors and their applications.
  • the indium ion (In 3+ ) has a relatively large ionic radius, which enables a higher probability of orbital overlap in the multi-component metal oxide to ensure its efficient carrier.
  • the transport channel whose 5s orbital is the main electron transport channel.
  • Oxygen vacancies are the main reason for the deterioration of the stability of metal oxide thin film transistors.
  • IGZO also has some problems: the large addition of Ga 3+ and Zn 2+ ions greatly dilutes the In 3+ concentration, thereby reducing the overlap of the 5s orbital and reducing the electron mobility.
  • the present invention provides a metal oxide semiconductor with relatively high mobility and strong photostability, which is a new co-doping strategy utilizing the special 4f electron orbital characteristics of rare earth oxides , in the oxide film with a high In ratio, while achieving higher mobility, the carrier concentration can be controlled, and a metal oxide semiconductor with strong photostability can be obtained.
  • the novel co-doping strategy of the present invention is to simultaneously introduce two oxide materials of rare earth element R and oxide materials of rare earth element R' with different functions into the metal oxide containing indium, wherein the oxidation of rare earth element R
  • the compound is the carrier concentration control agent
  • the oxide of the rare earth element R' is the light stabilizer, that is, the oxide of the rare earth element R' is the charge conversion center
  • its working principle is as follows:
  • the carrier concentration control agent is Yb 2+ ion and Eu 2+ ion in ytterbium oxide and europium oxide using oxides of rare earth element R, which have fully and partially filled 4f electron orbits, respectively. Therefore, the divalent ion in the oxide of the rare earth element R has lower energy than the trivalent ion in the oxide. In oxide semiconductors, the carrier concentration can be significantly reduced when In 3+ ions are replaced by doping.
  • the bond breaking enthalpy changes ( ⁇ Hf298) of Yb-O and Eu-O are 715.1kJ/mol and 557.0kJ/mol, respectively, which are much larger than the bond breaking energy (360.0kJ/mol) of In-O, they can effectively Control the oxygen vacancy concentration.
  • the introduction of oxides of rare earth element R can effectively control the oxygen vacancies of oxide semiconductor thin films under high In system, in which, due to the ionic radius of Yb 2+ compared with Eu 2 + is smaller, which is more conducive to reducing the In-In distance in the oxide semiconductor, so it can also maintain its better high mobility characteristics.
  • the light stabilizer is based on the characteristics of the rare earth ion radius of praseodymium oxide, terbium oxide, cerium oxide, dysprosium oxide and other materials in the oxide of rare earth element R', which are comparable to the indium ion radius in indium oxide, and the 4f orbital electronic structure in rare earth ions. And the 5s orbital of indium ion can form an efficient charge conversion center to improve its electrical stability, especially the stability under illumination.
  • Another object of the present invention is to provide a thin film transistor including the metal oxide semiconductor.
  • the third object of the present invention is to provide the application of the thin film transistor.
  • the present invention adopts the following technical scheme to realize:
  • the metal oxide semiconductor provided by the present invention is a compound semiconductor based on indium oxide, and two types of rare earth oxides with different functions but complementary roles are introduced by means of co-doping.
  • the optional materials for the oxides of rare earth element R are ytterbium oxide and europium oxide, which are used as carrier concentration control agents, using Yb 2+ ions and Eu 2+ ions in ytterbium oxide and europium oxide, respectively with full and A half-filled 4f electron orbital. Therefore, the divalent ion in the oxide of the rare earth element R has lower energy than the trivalent ion in the oxide.
  • the carrier concentration can be significantly reduced when In 3+ ions are replaced by doping.
  • the bond breaking enthalpy changes ( ⁇ Hf298) of Yb-O and Eu-O are 715.1kJ/mol and 557.0kJ/mol, respectively, which are much larger than the bond breaking energy (360.0kJ/mol) of In-O, they can effectively Control the oxygen vacancy concentration.
  • the introduction of oxides of rare earth element R can effectively control the oxygen vacancies of oxide semiconductor films under high In systems.
  • the ionic radius of Yb 2+ is smaller than that of Eu 2+ , it is more beneficial to reduce the In-In distance in the oxide semiconductor, so it can maintain its better high mobility characteristics.
  • the oxides of rare earth element R' can be selected from praseodymium oxide, terbium oxide, cerium oxide, and dysprosium oxide.
  • the material selection is based on the electronic structure characteristics of the 4f orbital in the rare earth ion, which can form an efficient charge conversion center with the 5s orbital of the indium ion.
  • the rare earth ions are in a stable low-energy state. Due to the modulation of the Fermi level, the film has a high carrier concentration, which can effectively shield the carrier scattering effect caused by the conversion center. The electrical properties of the device were not significantly affected.
  • the electron orbital of rare earth element 4f and the 5s orbital of indium are coupled, and the rare earth ion is in an unstable activation state.
  • it causes an increase in the off-state current of the device, and its scattering effect on carriers is enhanced, so that the subthreshold swing of the device is slightly increased;
  • the photogenerated electrons will be quickly "captured” by the activated conversion center, and the photogenerated carriers will recombine with the ionized oxygen vacancies in the form of non-radiative transitions through their coupling orbitals, and the activated center will return to the activated state. . Therefore, the conversion center can provide a fast recombination channel for photogenerated carriers, avoiding its influence on I-V characteristics and stability. Greatly improve the stability of metal oxide semiconductor devices under illumination.
  • the oxide of the rare earth element R is a carrier concentration control agent; the oxide of the rare earth element R is one or a combination of two materials of ytterbium oxide and europium oxide.
  • the oxide of the rare earth element R' is a light stabilizer; the oxide of the rare earth element R' is one of praseodymium oxide, terbium oxide, cerium oxide, and dysprosium oxide, or a combination of any two or more materials.
  • M is one or a combination of any two or more materials selected from Zn, Ga, Sn, Ge, Sb, Al, Mg, Ti, Zr, Hf, Ta, and W.
  • the metal oxide semiconductor is prepared into a film by adopting any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser deposition, reactive ion deposition, and solution method.
  • the second purpose of the present invention adopts the following technical scheme to realize:
  • a thin film transistor comprising a gate electrode, an active layer, an insulating layer between the gate electrode and the active layer, a source electrode and a drain electrode respectively electrically connected to both ends of the active layer, and A spacer layer, wherein the active layer is the above-mentioned metal oxide semiconductor.
  • the present invention also provides a thin film transistor formed based on the active layer obtained from the metal oxide semiconductor.
  • the metal oxide semiconductor is formed by introducing two oxides of rare earth elements R with different functions into the metal oxide containing indium simultaneously.
  • An oxide of rare earth element R' wherein the oxide of rare earth element R is used as a carrier concentration control agent, and the oxide of rare earth element R' is used as a light stabilizer, so that it can maintain good high mobility characteristics, and It can improve its electrical stability, especially the stability under illumination.
  • the spacer layer is a structure of one of silicon oxide, silicon nitride, and silicon oxynitride thin films prepared by plasma enhanced chemical vapor deposition, or a stacked structure composed of any two or more.
  • the third purpose of the present invention adopts the following technical scheme to realize:
  • the present invention adopts a new co-doping strategy to introduce two rare earth oxide materials with different functions into the indium-based metal oxide to simultaneously control the carrier concentration and achieve the effects of good device light stability. , which provides a new idea for the realization of high-performance metal-oxide-semiconductor materials in the future.
  • the rare earth element R oxides and rare earth element R' oxides are introduced into the indium-containing metal oxide to form a metal oxide semiconductor, and the rare earth element R oxides are used as carriers to control .
  • the oxide of rare earth element R' acts as photostability enhancement, and its purpose is to effectively control the carrier concentration in the oxide semiconductor by utilizing the extremely high oxygen bond breaking energy in the oxide of rare earth element R.
  • the 4f orbital electronic structure of the rare earth element R' ion and the 5s orbital of the indium ion can form an efficient charge conversion center to improve its electrical stability by utilizing the characteristics of the radii of rare earth ions that are comparable to those of indium ions in indium oxide. Especially the stability under light.
  • FIG. 1 is a schematic structural diagram of the thin film transistor of Embodiment 13 and Embodiment 14;
  • FIG. 2 is a schematic structural diagram of the thin film transistors of Embodiment 15, Embodiment 16 and Embodiment 17;
  • FIG. 3 is a schematic structural diagram of the thin film transistor of Embodiment 18;
  • Example 4 is a graph of device transfer characteristics and photo-generated current characteristics of Example 13;
  • Example 5 is a graph of device transfer characteristics and photo-generated current characteristics of Example 14.
  • Example 6 is a graph of device transfer characteristics and photo-generated current characteristics of Example 15;
  • Example 7 is a graph of device transfer characteristics and photo-generated current characteristics of Example 16.
  • Example 8 is a graph of device transfer characteristics and photo-generated current characteristics of Example 17;
  • FIG. 9 is a graph showing device transfer characteristics and photo-generated current characteristics of Example 18.
  • each reference number 01, substrate; 02, buffer layer; 03, channel layer; 04, insulating layer; 05, gate; 06, spacer layer; 07-1, source electrode; 07-2, drain pole; 08, etching barrier layer.
  • Example 1 Praseodymium oxide and europium oxide doped indium tin zinc oxide semiconductor material
  • a group of metal oxide semiconductor materials is: indium tin oxide (InSnZnO) is doped with praseodymium oxide as a charge conversion center, and europium oxide is doped as a carrier control agent to form praseodymium oxide, Europium oxide co-doped indium tin zinc oxide (Pr-Eu:InSnZnO) semiconductor material.
  • indium tin oxide InSnZnO
  • europium oxide is doped as a carrier control agent to form praseodymium oxide
  • Pr-Eu:InSnZnO Europium oxide co-doped indium tin zinc oxide
  • Example 2 Co-doped indium zinc oxide semiconductor material with praseodymium oxide and ytterbium oxide
  • a group of metal oxide semiconductor materials is: indium zinc oxide (InZnTiO) is doped with praseodymium oxide as a charge conversion center, and ytterbium oxide is doped as a carrier control agent to form praseodymium oxide, Ytterbium oxide co-doped indium zinc titanium oxide (Pr-Yb:InZnTiO) semiconductor material.
  • InZnTiO indium zinc oxide
  • ytterbium oxide is doped as a carrier control agent to form praseodymium oxide
  • Pr-Yb:InZnTiO Ytterbium oxide co-doped indium zinc titanium oxide
  • Example 3 terbium oxide and europium oxide co-doped indium gallium zinc oxide semiconductor material
  • a group of metal oxide semiconductor materials is: indium gallium zinc oxide (InGaZnO) is doped with terbium oxide as a charge conversion center, and doped with europium oxide as a carrier control agent to form terbium oxide, Europium oxide co-doped indium gallium zinc oxide (Tb-Eu:InGaZnO) semiconductor material.
  • InGaZnO indium gallium zinc oxide
  • Tb-Eu:InGaZnO Europium oxide co-doped indium gallium zinc oxide
  • Example 4 Terbium oxide and ytterbium oxide co-doped indium gallium zirconium oxide semiconductor material
  • a group of metal oxide semiconductor materials is: indium gallium zirconium oxide (InGaZrO) is doped with terbium oxide as a charge conversion center, and ytterbium oxide is doped as a carrier control agent to form terbium oxide, Ytterbium oxide co-doped indium gallium zirconium oxide (Tb-Yb:InGaZrO) semiconductor material.
  • InGaZrO indium gallium zirconium oxide
  • ytterbium oxide is doped as a carrier control agent to form terbium oxide
  • Tb-Yb:InGaZrO Ytterbium oxide co-doped indium gallium zirconium oxide
  • Example 5 Co-doped indium zinc oxide semiconductor material with cerium oxide and europium oxide
  • a group of metal oxide semiconductor materials is: indium zinc oxide (InZnO) is doped with cerium oxide as a charge conversion center, and europium oxide is doped as a carrier control agent to form cerium oxide, oxide Europium co-doped indium zinc oxide (Ce-Eu:InZnO) semiconductor material.
  • InZnO indium zinc oxide
  • Ce-Eu:InZnO oxide Europium co-doped indium zinc oxide
  • MO zinc oxide
  • Example 6 Dysprosium oxide and ytterbium oxide co-doped indium zinc oxide tantalum semiconductor material
  • a group of metal oxide semiconductor materials is: indium zinc oxide (InZnTaO) is doped with dysprosium oxide as a charge conversion center, and ytterbium oxide is doped as a carrier control agent to form dysprosium oxide, Ytterbium oxide co-doped indium zinc tantalum oxide (Dy-Yb:InZnTaO) semiconductor material.
  • InZnTaO indium zinc oxide
  • ytterbium oxide is doped as a carrier control agent to form dysprosium oxide
  • Ytterbium oxide co-doped indium zinc tantalum oxide (Dy-Yb:InZnTaO) semiconductor material Ytterbium oxide co-doped indium zinc tantalum oxide
  • Example 7 Co-doped indium tin zinc oxide film of praseodymium oxide and europium oxide
  • a group of metal oxide semiconductor thin films is formed by magnetron sputtering of the praseodymium oxide and europium oxide co-doped indium tin zinc oxide semiconductor material in Example 1.
  • Example 8 Co-doped indium-zinc-titanium oxide film of praseodymium oxide and ytterbium oxide
  • a group of metal oxide semiconductor thin films is formed by magnetron sputtering of the praseodymium oxide and ytterbium oxide co-doped indium zinc oxide semiconductor materials in Example 2.
  • Example 9 Terbium oxide and europium oxide co-doped indium gallium zinc oxide film
  • a group of metal oxide semiconductor thin films is prepared by magnetron sputtering from the terbium oxide and europium oxide co-doped indium gallium zinc oxide semiconductor material of Example 3.
  • Example 10 Terbium oxide and ytterbium oxide co-doped indium gallium zirconium oxide film
  • a group of metal oxide semiconductor thin films is prepared by magnetron sputtering from the terbium oxide and ytterbium oxide co-doped indium gallium zirconium oxide semiconductor material of Example 4.
  • Example 11 Co-doped indium zinc oxide film of cerium oxide and europium oxide
  • a group of metal oxide semiconductor thin films are prepared from the cerium oxide and europium oxide co-doped indium zinc oxide semiconductor material of Example 5 by a solution method.
  • Example 12 Dysprosium oxide and ytterbium oxide co-doped indium zinc tantalum oxide film
  • a group of metal oxide semiconductor thin films is prepared from the dysprosium oxide and ytterbium oxide co-doped indium zinc oxide tantalum semiconductor material of Example 6 by magnetron sputtering.
  • a group of thin film transistors adopts a back-channel etched structure.
  • the schematic diagram of the structure is shown in Figure 1.
  • layer 04 a channel layer 03 covering the upper surface of the insulating layer 04 and corresponding to the gate electrode 05, a source electrode 07-1 and a drain electrode 07-2 that are spaced apart from each other and electrically connected to both ends of the channel layer 03, and Spacer layer 06.
  • the substrate 01 is a hard alkali-free glass substrate covered with a buffer layer 02 of silicon oxide.
  • the material of the gate 05 is a metal molybdenum/copper (Mo/Cu) laminated structure prepared by magnetron sputtering, and the thickness is 20/400 nm.
  • the insulating layer 04 is a stack of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 250/50 nm, wherein the silicon nitride is in contact with the gate 05 in the lower layer, and the silicon oxide The upper layer is in contact with the channel layer 03 .
  • the material of the channel layer 03 is the praseodymium oxide and europium oxide co-doped indium tin zinc oxide semiconductor material of Example 1, using indium tin zinc oxide (InSnZnO), europium oxide doped Hetero indium tin zinc oxide (Eu:InSnZnO), and praseodymium oxide, europium oxide co-doped indium tin zinc oxide (Pr-Eu:InSnZnO) three ceramic targets, using a single target or two co-sputtering methods , by adjusting the sputtering power of the two targets to achieve the preparation of thin films with different composition ratios.
  • indium tin zinc oxide InSnZnO
  • Eu:InSnZnO europium oxide doped Hetero indium tin zinc oxide
  • Pr-Eu:InSnZnO europium oxide co-doped indium tin zinc oxide
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a metal molybdenum/copper (Mo/Cu) laminated structure with a thickness of 20/400nm, which is patterned with a commercial hydrogen peroxide-based etchant, which has a good effect on the channel.
  • the damage of layer 03 is small, and there is no obvious etching residue.
  • the material of the spacer layer 06 is silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 300 nm and a deposition temperature of 250°C.
  • the thin film transistor of this embodiment may be a closed structure including only a substrate 01, a gate 05, an insulating layer 04, a channel layer 03, a source electrode 07-1 and a drain electrode 07-2, and a spacer layer 06, or may further include a flat structure layers, reflective electrodes, pixel definition layers, etc., and can also be integrated with other devices.
  • the patterning process of the thin film is performed by a photolithography process combined with a wet or dry etching method.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source (the light intensity is set to 10000 nits) to illuminate the channel layer 03 of the thin film transistor device , by evaluating the transfer characteristics of the device under illumination and no-illumination conditions, and extracting the changes in the threshold voltage and sub-threshold swing of the device to evaluate its strength; a large change in the threshold voltage indicates that its photo-generated current characteristics are strong, and vice versa.
  • the photogenerated current characteristics of the device were significantly suppressed after doping a certain amount of praseodymium oxide.
  • the increase of the content of praseodymium oxide the mobility and other characteristics of the device are further degraded, and the photogenerated current characteristics are further improved.
  • the device prepared in this example is tested for the corresponding photo-generated current characteristics, as shown in Figures 4(b) and 4(c), the corresponding m values are 0 and 0.05 respectively.
  • test results of this example show that the present invention can effectively control the carrier concentration of the material and improve the light stability by doping a certain amount of praseodymium oxide and europium oxide in the indium tin zinc oxide matrix material.
  • a group of thin film transistors adopts a back-channel etched structure.
  • the schematic diagram of the structure is shown in Figure 1.
  • layer 04 a channel layer 03 covering the upper surface of the insulating layer 04 and corresponding to the gate electrode 05, a source electrode 07-1 and a drain electrode 07-2 that are spaced apart from each other and electrically connected to both ends of the channel layer 03, and Spacer layer 06.
  • the substrate 01 is a hard alkali-free glass substrate covered with a buffer layer 02 of silicon oxide.
  • the material of the gate 05 is a metal molybdenum/copper (Mo/Cu) laminated structure prepared by magnetron sputtering, and the thickness is 20/400 nm.
  • the insulating layer 04 is a stack of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 250/50 nm, wherein the silicon nitride is in contact with the gate 05 in the lower layer, and the silicon oxide The upper layer is in contact with the channel layer 03 .
  • the material of the channel layer 03 is the praseodymium oxide and ytterbium oxide co-doped indium zinc oxide semiconductor material of Example 2, using indium zinc titanium oxide (InZnTiO), praseodymium oxide doped Hetero indium-zinc-titanium oxide (Pr:InZnTiO), and praseodymium oxide, ytterbium oxide co-doped indium-zinc-titanium oxide (Pr-Yb:InZnTiO) three ceramic targets, using a single target or two targets for co-sputtering By adjusting the sputtering power of the two targets, films with different composition ratios can be prepared.
  • indium zinc titanium oxide InZnTiO
  • Pr:InZnTiO praseodymium oxide doped Hetero indium-zinc-titanium oxide
  • Pr-Yb:InZnTiO praseodymium oxide, ytterbium oxide co-do
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a metal molybdenum/copper (Mo/Cu) laminated structure with a thickness of 20/400nm, which is patterned with a commercial hydrogen peroxide-based etchant, which has a good effect on the channel.
  • the damage of layer 03 is small, and there is no obvious etching residue.
  • the material of the spacer layer 06 is silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 300 nm and a deposition temperature of 250°C.
  • the thin film transistor of this embodiment may be a closed structure including only a substrate 01, a gate 05, an insulating layer 04, a channel layer 03, a source electrode 07-1 and a drain electrode 07-2, and a spacer layer 06, or may further include a flat structure layers, reflective electrodes, pixel definition layers, etc., and can also be integrated with other devices.
  • the patterning process of the thin film is performed by a photolithography process combined with a wet or dry etching method.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source (the light intensity is set to 10000 nits) to illuminate the channel layer 03 of the thin film transistor device , by evaluating the transfer characteristics of the device under illumination and no-illumination conditions, and extracting the changes in the threshold voltage and sub-threshold swing of the device to evaluate its strength; a large change in the threshold voltage indicates that its photo-generated current characteristics are strong, and vice versa.
  • the device prepared in this example was tested for the corresponding photo-generated current characteristics, as shown in Figures 5(b) and 5(c), the corresponding m values were 0.05, and the n values were 0.001 and 0.05, respectively.
  • test results of this embodiment show that the present invention can effectively control the carrier concentration of the material and improve the photostability by doping a certain amount of praseodymium oxide and ytterbium oxide into the indium zinc oxide matrix material.
  • a group of thin film transistors adopts a top-gate self-aligned structure.
  • the schematic diagram of the structure is shown in FIG. 2 .
  • the substrate 01 is a hard glass substrate.
  • the buffer layer 02 is silicon oxide prepared by plasma enhanced chemical vapor deposition.
  • the material of the channel layer 03 is the terbium oxide and europium oxide co-doped indium gallium zinc oxide semiconductor material of the third embodiment, and the thickness is 30 nm.
  • the insulating layer 04 is silicon oxide with a thickness of 300 nm; the gate 05 is a titanium/copper (Ti/Cu) laminated structure prepared by magnetron sputtering, with a thickness of 20/400 nm.
  • the spacer layer 06 is made of silicon oxide with a thickness of 300 nm.
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a titanium/copper (Ti/Cu) laminated structure prepared by magnetron sputtering, and the thickness is 20/400 nm.
  • the material of the channel layer 03 is the terbium oxide and europium oxide co-doped indium gallium zinc oxide semiconductor material of Example 3, using indium gallium zinc oxide (InGaZnO), terbium oxide doping Indium gallium zinc oxide (Tb: InGaZnO), and terbium oxide, europium oxide co-doped indium gallium zinc oxide (Tb-Eu: InGaZnO) three ceramic targets, using a single target or two targets co-sputtering By adjusting the sputtering power of the two targets, films with different composition ratios can be prepared.
  • indium gallium zinc oxide InGaZnO
  • Tb InGaZnO
  • Tb-Eu InGaZnO
  • the thin film transistor of this embodiment may be a closed structure including only the substrate 01, the channel layer 03, the insulating layer 04, the gate electrode 05, the spacer layer 06, the source electrode 07-1 and the drain electrode 07-2, or may further include a passivation It can also integrate with other devices and so on.
  • the patterning of the thin film is performed by photolithography combined with wet or dry etching.
  • the specific parameters in this example and the performance of the prepared thin film transistor device are shown in Table 3.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source to illuminate the channel layer of the thin film transistor device.
  • the variation of the threshold voltage of the device is extracted to evaluate its strength; the threshold voltage varies greatly, indicating that its photo-generated current characteristics are strong, and vice versa.
  • the device prepared in this example was tested for the corresponding photo-generated current characteristics, as shown in Figures 6(b) and 6(c), the corresponding m values were both 0.05, and the n values were 0.001 and 0.05, respectively.
  • test results of this example show that the present invention can effectively control the carrier concentration of the material and improve the light stability by doping a certain amount of terbium oxide and europium oxide in the indium gallium zinc oxide matrix material.
  • a group of thin film transistors adopts a top-gate self-aligned structure.
  • the schematic diagram of the structure is shown in FIG. 2 .
  • the substrate 01 is a hard glass substrate.
  • the buffer layer 02 is silicon oxide prepared by plasma enhanced chemical vapor deposition.
  • the material of the channel layer 03 is the terbium oxide and ytterbium oxide co-doped indium gallium zirconium oxide semiconductor material of Example 4, and the thickness is 30 nm.
  • the insulating layer 04 is silicon oxide with a thickness of 300 nm; the gate 05 is a titanium/copper (Ti/Cu) laminated structure prepared by magnetron sputtering, with a thickness of 20/400 nm.
  • the spacer layer 06 is made of silicon oxide with a thickness of 300 nm.
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a titanium/copper (Ti/Cu) laminated structure prepared by magnetron sputtering, and the thickness is 20/400 nm.
  • the material of the channel layer 03 is the terbium oxide and ytterbium oxide co-doped indium gallium zirconium oxide semiconductor material of Example 4, and indium gallium zirconium oxide (InGaZrO) and terbium oxide are used for doping Indium gallium zirconium oxide (Tb: InGaZrO), and terbium oxide, ytterbium oxide co-doped indium gallium zirconium oxide (Tb-Yb: InGaZrO) three ceramic targets, using a single target or two targets co-sputtering By adjusting the sputtering power of the two targets, films with different composition ratios can be prepared.
  • InGaZrO Indium gallium zirconium oxide
  • Tb-Yb InGaZrO
  • the thin film transistor of this embodiment may be a closed structure including only the substrate 01, the channel layer 03, the insulating layer 04, the gate electrode 05, the spacer layer 06, the source electrode 07-1 and the drain electrode 07-2, or may further include a passivation It can also integrate with other devices and so on.
  • the patterning of the thin film is performed by photolithography combined with wet or dry etching.
  • the specific parameters in this example and the performance of the prepared thin film transistor device are shown in Table 4.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source to illuminate the channel layer 03 of the thin film transistor device.
  • the variation of the threshold voltage of the device is extracted to evaluate its strength; the threshold voltage varies greatly, indicating that its photo-generated current characteristics are strong, and vice versa.
  • the photogenerated current characteristics of the device were significantly suppressed after doping a certain amount of terbium oxide.
  • the characteristics of the device such as mobility are further degraded, and the photogenerated current characteristics are further improved.
  • the device prepared in this example is tested for the corresponding photo-generated current characteristics, as shown in Figures 7(b) and 7(c), the corresponding n values are all 0.05, and the m values are 0 and 0.05 respectively.
  • the threshold voltage of the device has almost no change; it exhibits excellent light stability, which corresponds to the weak photo-generated current characteristics in Table 4.
  • test results of this embodiment show that the present invention can effectively control the carrier concentration of the material and improve the light stability by doping a certain amount of terbium oxide and ytterbium oxide into the indium gallium zirconium oxide matrix material.
  • a group of thin film transistors adopts a self-aligned structure.
  • the schematic diagram of the structure is shown in Figure 2, and is provided with: a substrate 01, a buffer layer 02, a channel layer 03, an insulating layer 04 located on the channel layer 03, and a gate 05.
  • a spacer layer 06 covering the upper surface of the channel layer 03 and the gate electrode 05, a source electrode 07-1 and a drain electrode 07-2 on the spacer layer 06 and electrically connected to both ends of the channel layer 03.
  • the substrate 01 is a hard glass substrate.
  • the buffer layer 02 is silicon oxide prepared by plasma enhanced chemical vapor deposition.
  • the material of the channel layer 03 is the cerium oxide and europium oxide co-doped indium zinc oxide semiconductor material of Example 5, and the thickness is 20 nm.
  • the insulating layer 04 is silicon oxide with a thickness of 300 nm; the gate 05 is a molybdenum/copper/molybdenum (Mo/Cu/Mo) laminated structure prepared by magnetron sputtering with a thickness of 20/400/50 nm.
  • Mo/Cu/Mo molybdenum/copper/molybdenum
  • the spacer layer 06 is a silicon oxide film prepared by plasma enhanced chemical vapor deposition, and the thickness is 300 nm.
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a molybdenum/copper/molybdenum (Mo/Cu/Mo) laminated structure prepared by magnetron sputtering, with a thickness of 20/400/50 nm.
  • the thin film transistor of this embodiment may be a closed structure including only the substrate 01, the channel layer 03, the insulating layer 04, the gate electrode 05, the spacer layer 06, the source electrode 07-1 and the drain electrode 07-2, or may further include a passivation It can also integrate with other devices and so on.
  • the patterning of the thin film is performed by photolithography combined with wet or dry etching.
  • the specific parameters in this example and the performance of the prepared thin film transistor device are shown in Table 5.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source to illuminate the channel layer 03 of the thin film transistor device.
  • the variation of the threshold voltage of the device is extracted to evaluate its strength; the threshold voltage varies greatly, indicating that its photo-generated current characteristics are strong, and vice versa.
  • the photogenerated current characteristics of the device were significantly suppressed after doping a certain amount of ceria.
  • the characteristics such as the mobility of the device are further degraded, and the photogenerated current characteristics are further improved.
  • the device prepared in this example was tested for the corresponding photo-generated current characteristics, as shown in Figures 8(b) and 8(c), the corresponding n values were all 0.05, and the m values were 0 and 0.05, respectively.
  • the threshold voltage of the device has almost no change; it exhibits excellent light stability, which corresponds to the weak photo-generated current characteristics in Table 5.
  • test results of this embodiment show that the present invention can effectively control the carrier concentration of the material and improve the light stability by doping a certain amount of cerium oxide and europium oxide in the indium zinc oxide matrix material.
  • a group of thin film transistors adopts an etch stop type structure.
  • the schematic diagram of the structure is shown in FIG. 3 , and is provided with: a substrate 01 , a gate 05 located on the substrate 01 , and an insulating layer 04 located on the substrate 01 and the gate 05 .
  • the channel layer 03 covering the upper surface of the insulating layer 04 and corresponding to the gate electrode 05
  • the etching barrier layer 08 the source electrode 07-1 and the drain electrode 07 which are spaced apart from each other and electrically connected to both ends of the channel layer 03 -2, and the spacer layer 06.
  • the substrate 01 is a glass substrate covered with a buffer layer 02 of silicon oxide.
  • the material of the gate 05 is a molybdenum-aluminum-molybdenum (Mo/Al/Mo) metal stack structure prepared by magnetron sputtering, with a thickness of 50/300/50 nm.
  • Mo/Al/Mo molybdenum-aluminum-molybdenum
  • the insulating layer 04 is a stack of silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) prepared by chemical vapor deposition, with a thickness of 250/50 nm; wherein the silicon nitride is in contact with the gate 05 in the lower layer, and the silicon oxide The upper layer is in contact with the channel layer 03 .
  • the material of the channel layer 03 is the dysprosium oxide and ytterbium oxide co-doped indium zinc tantalum oxide semiconductor material of Example 6, using indium zinc tantalum oxide (InZnTaO), ytterbium oxide doped Hetero indium zinc tantalum oxide (Yb:InZnTaO), and dysprosium oxide, ytterbium oxide co-doped indium zinc tantalum oxide (Dy-Yb:InZnTaO) three ceramic targets, using a single target or two co-sputtering methods , by adjusting the sputtering power of the two targets to achieve the preparation of thin films with different composition ratios.
  • indium zinc tantalum oxide InZnTaO
  • Yb:InZnTaO ytterbium oxide doped Hetero indium zinc tantalum oxide
  • Dy-Yb:InZnTaO dysprosium oxide, ytterbium oxide co-doped indium zinc tanta
  • the materials of the etch stop layer 08 and the spacer layer 06 are silicon oxide (SiO 2 ) thin films prepared by chemical vapor deposition, with a thickness of 300 nm and a deposition temperature of 300°C.
  • the material of the source electrode 07-1 and the drain electrode 07-2 is a metal molybdenum aluminum molybdenum (Mo/Al/Mo) laminated structure with a thickness of 50/300/50 nm.
  • the thin film transistor of this embodiment may be a thin film transistor including only a substrate 01, a gate electrode 05, an insulating layer 04, a channel layer 03, an etch stop layer 08, a source electrode 07-1 and a drain electrode 07-2, and a passivation layer.
  • the closed structure may further include a flat layer, a reflective electrode, a pixel definition layer, etc., and may also be integrated with other devices.
  • the patterning process of the thin film is performed by a photolithography process combined with a wet or dry etching method.
  • the photo-generated current characteristic is characterized by using a commercial white LED light source to illuminate the channel layer 03 of the TFT device, and evaluating the illumination and no illumination conditions Under the transfer characteristics of the device, the change of the threshold voltage of the device is extracted to evaluate its strength; a large change in the threshold voltage indicates that its photo-generated current characteristics are strong, and vice versa.
  • the photogenerated current characteristics of the device were significantly suppressed after doping a certain amount of dysprosium oxide.
  • the characteristics of the device such as mobility are further degraded, and the photogenerated current characteristics are further improved.
  • the device prepared in this example was tested for the corresponding photo-generated current characteristics, as shown in Figures 9(b) and 9(c), the corresponding n values were both 0.05, and the m values were 0 and 0.05, respectively.
  • the threshold voltage of the device has almost no change; it exhibits excellent light stability, which corresponds to the weak photo-generated current characteristics in Table 6.
  • test results of this embodiment show that the present invention can effectively control the carrier concentration of the material and improve the light stability by doping a certain amount of dysprosium oxide and ytterbium oxide into the indium zinc oxide tantalum matrix material.
  • a display panel includes the thin film transistors in the above-mentioned embodiments 13-18, and the thin film transistors are used to drive display units in the display panel.
  • a detector includes the thin film transistors in the above-mentioned embodiments 13-18, and the thin film transistors are used to drive the detection unit of the detector.
  • the substrate in the present invention is not particularly limited, and a substrate 01 known in the art can be used.
  • a substrate 01 known in the art can be used.
  • the material of the gate 05 in the present invention is not particularly limited, and can be arbitrarily selected from materials known in the art. Such as: transparent conductive oxides (ITO, AZO, GZO, IZO, ITZO, FTO, etc.), metals (Mo, Al, Cu, Ag, Ti, Au, Ta, Cr, Ni, etc.) and their alloys, as well as metals and oxides composite conductive films formed by metal and metal stacking (Mo/Al/Mo, Ti/Al/Ti, etc.)
  • the preparation method of the gate 05 film can be sputtering, electroplating, thermal evaporation and other deposition methods, and the sputtering deposition method is preferred, because the film prepared by this method has good adhesion to the substrate 01, excellent uniformity, and can be large. area preparation.
  • a transparent electrode needs to be used in a transparent display, which can be a single layer of ITO as a gate electrode or ITO/Ag/ITO as a gate electrode. electrode.
  • a transparent display which can be a single layer of ITO as a gate electrode or ITO/Ag/ITO as a gate electrode. electrode.
  • high-temperature processes are required for applications in special fields, and the gate electrode can be selected from a metal alloy film that can withstand high temperatures.
  • the material of the insulating layer 04 in the present invention is not particularly limited, and can be arbitrarily selected from materials known in the art. Such as: silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, and polymer organic film layers.
  • the composition of these insulating films can be inconsistent with the theoretical stoichiometric ratio.
  • the insulating layer 04 can be formed by stacking various insulating films, which can form better insulating properties on the one hand, and improve the interface properties between the channel layer 03 and the insulating layer 04 on the other hand.
  • the insulating layer 04 can be prepared in various ways, and can be prepared by physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser deposition, anodization, or solution method.
  • the etching solution used in wet etching includes: a mixed solution of phosphoric acid, nitric acid and glacial acetic acid or a mixed solution based on hydrogen peroxide.
  • the etching rate of the metal oxide semiconductor material in the hydrogen peroxide-based etching solution is less than 1 nm/min.
  • a plasma etching process can be selected, and the etching gas includes chlorine-based or fluorine-based gas.
  • single-target sputtering or multi-target co-sputtering can be selected, preferably single-target sputtering.
  • single-target sputtering can provide more repeatable and stable films, and the microstructure of the film is more controllable; unlike co-sputtered films, the sputtered particles are subject to more factors in the process of recombination interference.
  • the power source can be selected from radio frequency (RF) sputtering, direct current (DC) sputtering or alternating current (AC) sputtering, preferably AC sputtering commonly used in the industry.
  • RF radio frequency
  • DC direct current
  • AC alternating current
  • the sputtering gas pressure is optional to be 0.1Pa to 10Pa, preferably 0.3Pa to 0.7Pa.
  • the oxygen partial pressure is optionally 0-1 Pa, preferably 0.001-0.5 Pa, more preferably 0.01-0.1 Pa.
  • the oxygen partial pressure has a direct effect on the carrier concentration of the film, and some defects related to oxygen vacancies will be introduced. Too low oxygen content may cause serious oxygen mismatch in the film and increase the carrier concentration; while too high oxygen vacancies will cause more weak bonds and reduce the reliability of the device.
  • the substrate temperature is preferably 200-300°C.
  • a certain substrate temperature can effectively improve the bonding mode of the sputtered particles after they reach the substrate 01, reduce the probability of the existence of weak bonding bonds, and improve the stability of the device.
  • this effect can also be achieved by subsequent processes such as annealing treatment.
  • the thickness of the channel layer 03 is optional to be 2-100 nm, preferably 5-50 nm, and more preferably 20-40 nm.
  • the source-drain electrode material in the present invention is not particularly limited, and can be arbitrarily selected from materials known in the art on the premise of not affecting the realization of various required structural devices.
  • materials known in the art on the premise of not affecting the realization of various required structural devices.
  • transparent conductive oxides ITO, AZO, GZO, IZO, ITZO, FTO, etc.
  • metals Mo, Al, Cu, Ag, Ti, Au, Ta, Cr, Ni, etc.
  • metals and oxides composite conductive films formed by metal and metal stacking Mo/Al/Mo, Ti/Al/Ti, etc.
  • the preparation method of the source-drain electrode film can be sputtering, thermal evaporation and other deposition methods, and the sputtering deposition method is preferred, because the film prepared in this way has good adhesion to the substrate 01, excellent uniformity, and can be prepared in a large area. .
  • the etching solution for wet etching in the embodiment of the present invention is an etching solution based on conventional metals in the industry (eg, hydrogen peroxide-based etching solution), mainly because a metal oxide semiconductor material of the present invention can effectively resist wet
  • the etching of hydrogen peroxide-based etching solution has a high etching selectivity ratio with metals (such as molybdenum, molybdenum alloy, molybdenum/aluminum/molybdenum, etc.), and the metal oxide semiconductor layer is basically not affected by the etching solution.
  • the prepared device has excellent performance and good stability.
  • the dry etching in the embodiments of the present invention is based on conventional etching gases in the industry (such as chlorine-based gas, fluorine-based gas, etc.), which has little effect on the oxide semiconductor layer of the present invention, and the prepared device performance Excellent and stable.
  • the material of the passivation layer in the present invention is not particularly limited, and can be arbitrarily selected from materials known in the art. Such as: silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, and polymer organic film layers.
  • the composition of these insulating films can be inconsistent with the theoretical stoichiometric ratio.
  • the insulating layer 04 can be formed by stacking multiple insulating films, which can form better insulating properties on the one hand, and improve the interface properties between the channel layer 03 and the passivation layer on the other hand.
  • the passivation layer can be prepared in various ways, and can be prepared by physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser deposition or solution method.
  • the film deposited by sputtering generally has a faster rate of deposition; the film does not have enough time to perform the relaxation process during the deposition process, which will cause a certain proportion of dislocation and stress. remains in the film. This requires a later thermal annealing treatment to continue to achieve the desired relative steady state and improve the properties of the film.
  • the annealing treatment is mostly set after the deposition of the channel layer 03 and the deposition of the passivation layer.
  • performing annealing treatment after the deposition of the channel layer 03 can effectively improve the in-situ defects in the channel layer 03 and improve the ability of the channel layer 03 to resist possible damage in subsequent processes.
  • this may require an "activation" process to further eliminate effects such as interface states and some donor doping.
  • the treatment method may not only be heat treatment, but may include plasma treatment of interfaces (eg, insulating layer 04/semiconductor interface, channel layer 03/passivation layer interface, etc.).
  • interfaces eg, insulating layer 04/semiconductor interface, channel layer 03/passivation layer interface, etc.
  • the performance of the device can be effectively improved and the stability of the device can be improved by the above-mentioned treatment process.

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Abstract

本发明公开了一种金属氧化物半导体，其为：在含铟的金属氧化物半导体中分别掺入至少两种的稀土元素R和R'的氧化物，形成In xM yR nR' mO z半导体。本发明通过利用稀土元素R的氧化物中极高的氧断键能，有效控制半导体内的载流子浓度，利用稀土离子半径和铟离子半径相当的特性，能形成电荷转换中心，提高其电学稳定性。本发明还提供基于该金属氧化物半导体的薄膜晶体管与应用。

Description

一种金属氧化物半导体及薄膜晶体管与应用 技术领域
本发明涉及半导体制造领域，尤其涉及平板显示和探测器应用中的金属氧化物半导体薄膜晶体管背板制作所用的材料和器件结构，具体涉及金属氧化物半导体及薄膜晶体管与应用。
背景技术
对于现有的金属氧化物半导体体系中，铟离子(In 3+)由于具有相对较大的离子半径，使得在多元金属氧化物中更高几率的轨道交叠而确保了其高效的载流子传输通道，其5s轨道是主要的电子输运通道。但是，一方面，由于铟与氧成键后In-O的断键能较低，所以在单纯的氧化铟(In 2O 3)薄膜中存在大量的氧空位缺陷。而氧空位是导致金属氧化物薄膜晶体管稳定性劣化的主要原因。另一方面，常规溅射成膜的氧化铟中存在较多的晶格失配，使得薄膜的载流子迁移率较低，限制了其在高性能薄膜晶体管中的应用。通常，需要掺杂与In 3+离子数量相当的Ga 3+离子对氧空位进行调控。同时，为了保证半导体器件的性能均匀性，需要金属氧化物半导体薄膜保持非晶薄膜结构。
由于ZnO的晶体结构与In 2O 3和Ga 2O 3两种材料的晶体结构差异较大，所以在薄膜中掺入与In离子数量相当Zn离子，可以抑制材料结晶，保持薄膜的非晶结构。因此，在目前的金属氧化物半导体材料中应用最为广泛的就是IGZO(In:Ga:Zn＝1:1:1mol)。
但是，IGZO亦存在一些问题：Ga 3+和Zn 2+离子的大量加入，大大稀释了In 3+的浓度，进而减少了5s轨道的交叠程度，降低了电子迁移率。
另外，IGZO等材料在靠近价带处存在大量的陷阱态。这导致了即使在光照 能量低于禁带宽度时，亦会产生光生载流子，导致当前的金属氧化物半导体存在光稳定性差的问题。
发明内容
为了克服现有技术的不足，本发明提供一种迁移率相对较高、光稳定性强的金属氧化物半导体，其为一种新的共掺杂策略，利用稀土氧化物特殊的4f电子轨道特点，能在高In比的氧化物薄膜中，实现较高迁移率的同时，控制载流子浓度，并获得光稳定性强的金属氧化物半导体。
本发明的新的共掺杂策略是在含铟的金属氧化物中，同时引入两种作用不同的稀土元素R的氧化物材料和稀土元素R’的氧化物材料，其中，稀土元素R的氧化物为载流子浓度控制剂，稀土元素R’的氧化物为光稳定剂，即稀土元素R’的氧化物为电荷转换中心，其作用原理如下：
载流子浓度控制剂是利用了稀土元素R的氧化物的氧化镱和氧化铕中Yb 2+离子和Eu 2+离子分别具有全满和半满的4f电子轨道。因此，稀土元素R的氧化物中的二价离子相比于三价离子在氧化物中具有更低能量。在氧化物半导体中，对于In 3+离子进行替代为掺杂时，可以明显减少载流子浓度。同时，由于Yb-O和Eu-O的断键焓变(ΔHf298)分别为715.1kJ/mol和557.0kJ/mol，均远大于In-O的断键能(360.0kJ/mol)，进而能有效控制氧空位浓度。综上所述，结合以上两个特点，稀土元素R的氧化物的引入可以有效地在高In体系下控制氧化物半导体薄膜的氧空位，其中，由于Yb 2+的离子半径相比于Eu 2+更小，更有利于减小氧化物半导体内In-In的距离，因此也更能保持其较好的高迁移率特性。
光稳定剂是利用稀土元素R’的氧化物中氧化镨、氧化铽、氧化铈、氧化镝等材料的稀土离子半径和氧化铟中的铟离子半径相当的特性，以及稀土离子中4f轨道电子结构和铟离子的5s轨道能形成高效的电荷转换中心，以提高其电学 稳定性，特别是光照下的稳定性。
本发明的目的之二在于提供包含该金属氧化物半导体的薄膜晶体管。
本发明的目的之三在于提供该薄膜晶体管的应用。
本发明采用如下技术方案实现：
一种金属氧化物半导体，该金属氧化物半导体为：在含铟的金属氧化物MO-In 2O 3半导体中，分别掺入至少两种的稀土元素R的氧化物和稀土元素R’的氧化物，形成In xM yR n R’ mO z半导体材料，其中，x+y+m+n＝1，0.4≤x＜0.9999，0≤y＜0.5，0.0001≤(m+n)≤0.2，m＞0，n＞0，z＞0。
即本发明提供的金属氧化物半导体是基于氧化铟的复合半导体，通过共掺杂的手段，引入了两类功能不同，但是作用互补的稀土氧化物。其中稀土元素R的氧化物可选的材料为氧化镱、氧化铕，其作为载流子浓度控制剂，利用了氧化镱和氧化铕中Yb 2+离子和Eu 2+离子，分别具有全满和半满的4f电子轨道。因此，稀土元素R的氧化物中的二价离子相比于三价离子在氧化物中具有更低能量。在氧化物半导体中，对于In 3+离子进行替代为掺杂时，可以明显减少载流子浓度。同时，由于Yb-O和Eu-O的断键焓变(ΔHf298)分别为715.1kJ/mol和557.0kJ/mol，均远大于In-O的断键能(360.0kJ/mol)，进而能有效控制氧空位浓度。结合以上两个特点，稀土元素R的氧化物的引入可以有效的在高In体系下控制氧化物半导体薄膜的氧空位。其中由于Yb 2+的离子半径相比于Eu 2+更小，更有利于减小氧化物半导体内In-In的距离，因此也更能保持其较好的高迁移率特性。
同时，稀土元素R’的氧化物可选材料为氧化镨、氧化铽、氧化铈、氧化镝。该材料选择是利用了稀土离子中4f轨道电子结构特点，其和铟离子的5s轨道能 形成高效的电荷转换中心。在正偏压下，稀土离子处于稳定的低能态，由于费米能级的调制作用使得薄膜中具有较高的载流子浓度，可以有效屏蔽该转换中心造成的载流子散射效应，从而对器件的电性特性等未有明显的影响。在负偏压下，稀土元素4f中的电子轨道的和铟的5s轨道发生耦合，稀土离子处于不稳定的活化状态。一方面，其造成了器件关态电流的增加，而且其对载流子的散射作用增强，使得器件的亚阈值摆幅稍有增大；另一方面，当有合适的光激发出光生载流子后，光生电子会被该活化的转换中心快速“俘获”，并通过其耦合轨道以非辐射跃迁的形式使该光生载流子和离化的氧空位复合，同时该活化中心重新恢复活化状态。因此，该转换中心，在能提供光生载流子的快速复合通道，避免其对I-V特性以及稳定性的影响。大幅提高金属氧化物半导体器件在光照下的稳定性。
进一步地，所述稀土元素R的氧化物为载流子浓度控制剂；所述稀土元素R的氧化物为氧化镱、氧化铕中的一种或两种材料组合。
进一步地，所述稀土元素R’的氧化物为光稳定剂；所述稀土元素R’的氧化物为氧化镨、氧化铽、氧化铈、氧化镝中的一种或任意两种以上材料组合。
进一步地，所述MO中，M为Zn、Ga、Sn、Ge、Sb、Al、Mg、Ti、Zr、Hf、Ta、W中的一种或任意两种以上材料组合。
进一步地，所述金属氧化物半导体通过采用物理气相沉积工艺、化学气相沉积工艺、原子层沉积工艺、激光沉积工艺、反应离子沉积工艺、溶液法工艺中的任意一种工艺的方法制备成膜。
本发明的目的之二采用如下技术方案实现：
一种薄膜晶体管，该薄膜晶体管包括栅极、有源层、位于所述栅极和有源层之间的绝缘层、分别电性连接在所述有源层两端的源极和漏极、以及间隔层， 其特征在于，所述有源层为上述所述的金属氧化物半导体。
即本发明还提供基于该金属氧化物半导体制得的有源层形成的薄膜晶体管，该金属氧化物半导体通过向含铟的金属氧化物中同时引入两种作用不同的稀土元素R的氧化物和稀土元素R’的氧化物，其中，稀土元素R的氧化物作为载流子浓度控制剂，稀土元素R’的氧化物作为光稳定剂，以使其能保持较好的高迁移率特性，并且能提高其电学稳定性，特别是光照下的稳定性。
进一步地，所述间隔层为采用等离子增强化学气相沉积方式制备的氧化硅、氮化硅、氮氧化硅薄膜中的一种结构或者任意两种以上组成的叠层结构。
本发明的目的之三采用如下技术方案实现：
所述的薄膜晶体管在显示面板或探测器中的应用。
相比现有技术，本发明的有益效果在于：
本发明通过一种新的共掺杂策略，在基于铟的金属氧化物中，通过引入两种功能不同的稀土氧化物材料，同时实现载流子浓度控制，以及达到良好器件光稳定性的效果，为未来高性能金属氧化物半导体材料的实现提供了崭新的思路。
本发明通过在含铟的金属氧化物中引入至少两种的稀土元素R的氧化物和稀土元素R’的氧化物，以形成的金属氧化物半导体，稀土元素R的氧化物作为载流子控制，稀土元素R’的氧化物作为光稳定性增强的作用，其目的是通过利用稀土元素R的氧化物中极高的氧断键能，进而有效控制氧化物半导体内的载流子浓度。同时，利用稀土离子半径和氧化铟中的铟离子半径相当的特性，而且稀土元素R’离子中4f轨道电子结构和铟离子的5s轨道能形成高效的电荷转换中心，以提高其电学稳定性，特别是光照下的稳定性。
附图说明
图1为实施例13、实施例14的薄膜晶体管结构示意图；
图2为实施例15、实施例16和实施例17的薄膜晶体管结构示意图；
图3为实施例18的薄膜晶体管结构示意图；
图4为实施例13的器件转移特性及光生电流特性图；
图5为实施例14的器件转移特性及光生电流特性图；
图6为实施例15的器件转移特性及光生电流特性图；
图7为实施例16的器件转移特性及光生电流特性图；
图8为实施例17的器件转移特性及光生电流特性图；
图9为实施例18的器件转移特性及光生电流特性图。
图中，各附图标记：01、基板；02、缓冲层；03、沟道层；04、绝缘层；05、栅极；06、间隔层；07-1、源极；07-2、漏极；08、刻蚀阻挡层。
具体实施方式
下面，结合附图和具体实施方式，对本发明做进一步描述，需要说明的是，在不相冲突的前提下，以下描述的各实施例之间或各技术特征之间可以任意组合形成新的实施例。
以下是本发明具体的实施例，在下述实施例中所采用的原材料、设备等除特殊限定外均可以通过购买方式获得。
实施例1：氧化镨、氧化铕掺杂氧化铟锡锌半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟锡锌(InSnZnO)中掺入氧化镨作为电荷转换中心，掺入氧化铕作为载流子控制剂，形成氧化镨、氧化铕共掺杂氧化铟锡锌(Pr-Eu:InSnZnO)的半导体材料。
其中，MO为氧化锡锌，In：Sn:Zn＝3:1:1mol，标记为In(3)Sn(1)Zn(1)；In x(SnZn) yEu nPr mO z中，其中x＝0.5，y＝0.3333，m＝0.05，n＝0.1167。但不限于上述的比例，在其他一些实施例中，x＝0.53，y＝0.353，m＝0.05，n＝0.067，或者，x＝0.56，y＝0.373，m＝0.05，n＝0.017，或者，x＝0.58，y＝0.387，m＝0.03，n＝0.003，在此不再赘述。
实施例2：氧化镨、氧化镱共掺杂氧化铟锌钛半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟锌钛(InZnTiO)中掺入氧化镨作为电荷转换中心，掺入氧化镱作为载流子控制剂，形成氧化镨、氧化镱共掺杂氧化铟锌钛(Pr-Yb:InZnTiO)的半导体材料。
其中，MO为氧化锌钛，In：Zn：Ti＝4:1:0.05mol，标记为In(4)Zn(1)Ti(0.05)；In x(ZnTi) yYb nPr mO z中，其中x＝0.75，y＝0.1969，m＝0.0031，n＝0.05。但不限于上述的比例，在其他一些实施例中，x＝0.7，y＝0.1838，m＝0.0662，n＝0.05，或者，x＝0.65，y＝0.17，m＝0.13，n＝0.05，在此不再赘述。
实施例3：氧化铽、氧化铕共掺杂氧化铟镓锌半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟镓锌(InGaZnO)中掺入氧化铽作为电荷转换中心，掺入氧化铕作为载流子控制剂，形成氧化铽、氧化铕共掺杂氧化铟镓锌(Tb-Eu:InGaZnO)的半导体材料。
其中，MO为氧化镓锌，In：Ga:Zn＝4:0.5:1mol，标记为In(4)Ga(0.5)Zn(1)；In x(GaZn) yEu nTb mO z中，其中x＝0.65，y＝0.2438，m＝0.05，n＝0.0562。但不限于上述的比例，在其他一些实施例中，x＝0.55，y＝0.2053，m＝0.05，n＝0.1937，或者，x＝0.58，y＝0.2175，m＝0.05，n＝0.1525，或者，x＝0.6，y＝0.225，m＝0.05，n＝0.125，在此不再赘述。
实施例4：氧化铽、氧化镱共掺杂氧化铟镓锆半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟镓锆(InGaZrO)中掺入氧化铽作为电荷转换中心，掺入氧化镱作为载流子控制剂，形成氧化铽、氧化镱共掺杂氧化铟镓锆(Tb-Yb:InGaZrO)的半导体材料。
其中，MO为氧化镓锆，In：Ga:Zr＝5:1:0.05mol，标记为In(5)Ga(1)Zr(0.05)；In x(GaZr) yYb nTb mO z中，其中x＝0.7，y＝0.147，m＝0.103，n＝0.05。但不限于上述的比例，在其他一些实施例中，x＝0.65，y＝0.1365，m＝0.1635，n＝0.05，或者，x＝0.63，y＝0.1323，m＝0.1877，n＝0.05，或者，x＝0.74，y＝0.1554，m＝0.0546，n＝0.05，在此不再赘述。
实施例5：氧化铈、氧化铕共掺杂氧化铟锌半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟锌(InZnO)中掺入氧化铈作为电荷转换中心，掺入氧化铕作为载流子控制剂，形成氧化铈、氧化铕共掺杂氧化铟锌(Ce-Eu:InZnO)的半导体材料。
其中，MO为氧化锌，In：Zn＝9:1mol，标记为In(9)Zn(1)；In xZn yEu nCe mO z中，其中x＝0.68，y＝0.0756，m＝0.1944，n＝0.05。但不限于上述的比例，在其他一些实施例中，x＝0.7，y＝0.0778，m＝0.1722，n＝0.05，或者，x＝0.75，y＝0.0833，m＝0.1167，n＝0.05，或者，x＝0.8，y＝0.0889，m＝0.0611，n＝0.05，在此不再赘述。
实施例6：氧化镝、氧化镱共掺杂氧化铟锌钽半导体材料
一组金属氧化物半导体材料，该组金属氧化物半导体材料为：在氧化铟锌钽(InZnTaO)中掺入氧化镝作为电荷转换中心，掺入氧化镱作为载流子控制剂，形成氧化镝、氧化镱共掺杂氧化铟锌钽(Dy-Yb:InZnTaO)的半导体材料。
其中，MO为氧化锌钽，In：Zn:Ta＝3:1:0.1mol，标记为In(3)Zn(1)Ta(0.1)；In x(ZnTa) yYb nDy mO z中，其中x＝0.58，y＝0.2127，m＝0.1573，n＝0.05。但不限 于上述的比例，在其他一些实施例中，x＝0.6，y＝0.22，m＝0.13，n＝0.05，或者，x＝0.65，y＝0.2383，m＝0.0617，n＝0.05，或者，x＝0.68，y＝0.2493，m＝0.0207，n＝0.05，在此不再赘述。
实施例7：氧化镨、氧化铕共掺杂氧化铟锡锌薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例1的 氧 化镨、氧化铕共掺杂氧化铟锡锌半导体材料经磁控溅射而成。
实施例8：氧化镨、氧化镱共掺杂氧化铟锌钛薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例2的 氧 化镨、氧化镱共掺杂氧化铟锌钛半导体材料经磁控溅射而成。
实施例9：氧化铽、氧化铕共掺杂氧化铟镓锌薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例3的 氧 化铽、氧化铕共掺杂氧化铟镓锌半导体材料采用磁控溅射制备而成。
实施例10：氧化铽、氧化镱共掺杂氧化铟镓锆薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例4的 氧 化铽、氧化镱共掺杂氧化铟镓锆半导体材料采用磁控溅射制备而成。
实施例11：氧化铈、氧化铕共掺杂氧化铟锌薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例5的 氧 化铈、氧化铕共掺杂氧化铟锌半导体材料经溶液法制备而成。
实施例12：氧化镝、氧化镱共掺杂氧化铟锌钽薄膜
一组金属氧化物半导体薄膜，该组金属氧化物半导体薄膜由实施例6的 氧 化镝、氧化镱共掺杂氧化铟锌钽半导体材料采用磁控溅射的方式制备而成。
实施例13：薄膜晶体管
一组薄膜晶体管，采用背沟道刻蚀型结构，其结构示意图如图1所示，设置有：基板01、位于基板01之上的栅极05、位于基板01和栅极05之上的绝缘层04、覆盖在绝缘层04上表面并与栅极05对应的沟道层03、相互间隔并与沟道层03的两端电性相连的源极07-1和漏极07-2、以及间隔层06。
其中，基板01为硬质无碱玻璃衬底，其上覆盖有缓冲层02氧化硅。
栅极05的材料为磁控溅射方式制备的金属钼/铜(Mo/Cu)叠层结构，厚度为20/400nm。
绝缘层04为化学气相沉积方式制备的氮化硅(Si 3N 4)和氧化硅(SiO 2)的叠层，厚度为250/50nm，其中氮化硅在下层和栅极05接触，氧化硅在上层和沟道层03接触。
为测试不同氧化镨含量对器件性能的影响，沟道层03的材料为实施例1的氧化镨、氧化铕共掺杂氧化铟锡锌半导体材料，利用氧化铟锡锌(InSnZnO)、氧化铕掺杂氧化铟锡锌(Eu:InSnZnO)，以及氧化镨、氧化铕共掺杂的氧化铟锡锌(Pr-Eu:InSnZnO)三个陶瓷靶材，采用单个靶材或两个共溅射的方式、通过调整两个靶材的溅射功率从而实现不同成分比例的薄膜制备而成。
源极07-1以及漏极07-2的材料为金属钼/铜(Mo/Cu)叠层结构，厚度为20/400nm，其采用商用的双氧水基刻蚀液进行图案化，其对沟道层03的损伤较小，而且无明显的刻蚀残余。
间隔层06的材料为化学气相沉积方式制备的氧化硅(SiO 2)，厚度为300nm，沉积温度为250℃。
本实施例的薄膜晶体管可以为仅包括基板01、栅极05、绝缘层04、沟道层03、源极07-1和漏极07-2、间隔层06的封闭结构，也可以进一步包括平坦层、反射电极、像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化工序采用光刻工艺、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表1所示，其中，光生电流特性的表征方式为采用商用白色LED光源(光强设置为10000nits)照射薄膜晶体管器件的沟道层03，通过评估光照和无光照条件下器件的转移特性，提取器件阈值电压和亚阈值摆幅等的变化情况来评估其强弱；阈值电压变化幅度大表明其光生电流特性强，反之则弱。
表1
Figure PCTCN2021096784-appb-000001
由该表1可知，氧化镨和氧化铕的掺入对器件性能有非常明显的影响。首先，如表1的试验1所示，未掺杂氧化镨(m＝0)和氧化铕(n＝0)的氧化铟锡锌制备的器件没有表现出薄膜晶体管的“开关”特性(导通状态)，表明薄膜中的载流子浓度过高。如表1的试验2所示，通过掺入一定量(对应m＝0,n＝0.05)的氧化铕后，器件表现出来“开关”特性，详见图4(a)所示，表明氧化铕的掺入能有效地抑制薄膜中的载流子浓度，对应的薄膜Hall数据见表1所示。进一步的，如表1的试验2～8所示，通过调节共溅射中靶材的溅射功率，可以制 备出一系列不同镨含量的器件。需要指出的是，未掺氧化镨的器件(对应m＝0,n＝0.05)具有相对较高的迁移率，较小的亚阈值摆幅和较负的阈值电压，但是其光生电流特性极强，即在有光照射条件下器件特性发生非常明显的变化(阈值电压负向漂移，亚阈值摆幅退化严重)。但是，在掺入一定量的氧化镨后器件的光生电流特性得到了明显的抑制。当然，随着氧化镨含量的增加，器件的迁移率等特性也进一步退化，光生电流特性进一步改善。当过量的氧化镨掺入后(如m＝0.15，n＝0.05)，器件的迁移率明显退化，虽然器件的光生电流特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光生电流特性测试，如图4(b)和4(c)所示，其对应的m值分别为0和0.05，当有光照射在器件上时，未掺氧化镨的器件(对应m＝0，n＝0.05)阈值电压明显负向偏移，亚阈值摆幅严重退化；而掺入一定量的氧化镨后(对应m＝0.05，n＝0.05)，器件的阈值电压几乎没有变化；表现出了优异的光照稳定性，也即对应表1中的弱光生电流特性。
本实施例的试验结果表明，本发明在氧化铟锡锌基体材料中，掺入一定量的氧化镨和氧化铕能有效控制材料的载流子浓度、提高光稳定性。
实施例14：薄膜晶体管
一组薄膜晶体管，采用背沟道刻蚀型结构，其结构示意图如图1所示，设置有：基板01、位于基板01之上的栅极05、位于基板01和栅极05之上的绝缘层04、覆盖在绝缘层04上表面并与栅极05对应的沟道层03、相互间隔并与沟道层03的两端电性相连的源极07-1和漏极07-2、以及间隔层06。
其中，基板01为硬质无碱玻璃衬底，其上覆盖有缓冲层02氧化硅。
栅极05的材料为磁控溅射方式制备的金属钼/铜(Mo/Cu)叠层结构，厚度为20/400nm。
绝缘层04为化学气相沉积方式制备的氮化硅(Si 3N 4)和氧化硅(SiO 2)的叠层，厚度为250/50nm，其中氮化硅在下层和栅极05接触，氧化硅在上层和沟道层03接触。
为测试不同氧化镱含量对器件性能的影响，沟道层03的材料为实施例2的氧化镨、氧化镱共掺杂氧化铟锌钛半导体材料，利用氧化铟锌钛(InZnTiO)、氧化镨掺杂氧化铟锌钛(Pr:InZnTiO)，以及氧化镨、氧化镱共掺杂的氧化铟锌钛(Pr-Yb:InZnTiO)三个陶瓷靶材，采用单个靶材或两个靶材共溅射的方式、通过调整两个靶材的溅射功率从而实现不同成分比例的薄膜制备而成。
源极07-1以及漏极07-2的材料为金属钼/铜(Mo/Cu)叠层结构，厚度为20/400nm，其采用商用的双氧水基刻蚀液进行图案化，其对沟道层03的损伤较小，而且无明显的刻蚀残余。
间隔层06的材料为化学气相沉积方式制备的氧化硅(SiO 2)，厚度为300nm，沉积温度为250℃。
本实施例的薄膜晶体管可以为仅包括基板01、栅极05、绝缘层04、沟道层03、源极07-1和漏极07-2、间隔层06的封闭结构，也可以进一步包括平坦层、反射电极、像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化工序采用光刻工艺、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表2所示，其中，光生电流特性的表征方式为采用商用白色LED光源(光强设置为10000nits)照射薄膜晶体管器件的沟道层03，通过评估光照和无光照条件下器件的转移特性，提取器件阈值电压和亚阈值摆幅等的变化情况来评估其强弱；阈值电压变化幅 度大表明其光生电流特性强，反之则弱。
表2
Figure PCTCN2021096784-appb-000002
由该表2可知，氧化镨和氧化镱的掺入对器件性能有非常明显的影响。首先，如表2的试验1所示，未掺杂氧化镨(m＝0)和氧化镱(n＝0)的氧化铟锌钛制备的器件没有表现出薄膜晶体管的“开关”特性(导通状态)，表明薄膜中的载流子浓度过高。如表2的试验2所示，通过掺入一定量(对应m＝0.05,n＝0)的氧化镨后，器件依然没有表现出来“开关”特性；进一步的，当继续掺入一定量的氧化镱后(对应m＝0.05,n＝0.0001)，器件表现出来“开关”特性；表明氧化镨对薄膜中的载流子浓度的抑制效果不如氧化镱效果明显，对应的薄膜Hall数据见表2所示。为了进一步研究氧化镱的影响，如表2的试验2～8所示，通过调节共溅射中靶材的溅射功率，可以制备出一系列不同镱含量的器件。具体的，掺杂少量氧化镱的器件(对应m＝0.05,n＝0.0001)具有相对较高的迁移率和较负的阈值电压。随着氧化镱含量的增加，器件阈值电压正向偏移，迁移率递减；说明氧化镱能有效调控器件的阈值电压，也即有效调控薄膜中的载流子浓 度，可以从表2中的Hall数据进一步认证。当然，过量的氧化镱掺入后(如m＝0.05，n＝0.15)，器件的迁移率明显退化，这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光生电流特性测试，如图5(b)和5(c)所示，其对应的m值均为0.05，n值分别为0.001和0.05，当有光照射在器件上时，掺杂少量氧化镱的器件(对应m＝0.05，n＝0.001)阈值电压未有明显偏移，亚阈值摆幅稍有退化；另外，掺入一定量的氧化镱后(对应m＝0.05，n＝0.05)，器件的阈值电压亦几乎没有变化，表现出了优异的光照稳定性，也即对应表2中的弱光生电流特性。需要指出的是，不同镱含量下(m＝0.05，n＝0～0.15)的器件光生电流特性都较弱，表明氧化镨的掺入能有效提高器件的光稳定性。
本实施例的试验结果表明，本发明在氧化铟锌钛基体材料中，掺入一定量的氧化镨和氧化镱能有效控制材料的载流子浓度、提高光稳定性。
实施例15：薄膜晶体管
一组薄膜晶体管，采用顶栅自对准型结构，其结构示意图如图2所示，设置有：基板01、缓冲层02、沟道层03、位于沟道层03之上的绝缘层04以及栅极05、覆盖在沟道层03和栅极上表面的间隔层06、在间隔层06之上并与沟道层03的两端电性相连的源极07-1和漏极07-2。
其中，基板01为硬质玻璃衬底。
缓冲层02为等离子增强化学气相沉积方式制备的氧化硅。
沟道层03的材料为实施例3的氧化铽、氧化铕共掺杂氧化铟镓锌半导体材料，厚度为30nm。
绝缘层04为氧化硅，厚度为300nm；栅极05为磁控溅射方式制备的钛/铜 (Ti/Cu)叠层结构，厚度为20/400nm。
间隔层06为的氧化硅，厚度为300nm。
源极07-1以及漏极07-2的材料为磁控溅射方式制备的钛/铜(Ti/Cu)叠层结构，厚度为20/400nm。
为测试不同铕含量对器件性能的影响，沟道层03的材料为实施例3的氧化铽、氧化铕共掺杂氧化铟镓锌半导体材料，利用氧化铟镓锌(InGaZnO)、氧化铽掺杂氧化铟镓锌(Tb:InGaZnO)，以及氧化铽、氧化铕共掺杂的氧化铟镓锌(Tb-Eu:InGaZnO)三个陶瓷靶材，采用单个靶材或两个靶材共溅射的方式、通过调整两个靶材的溅射功率从而实现不同成分比例的薄膜制备而成。
本实施例的薄膜晶体管可以为仅包括基板01、沟道层03、绝缘层04、栅极05、间隔层06、源极07-1和漏极07-2的封闭结构，也可以进一步包括钝化层、以及像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化采用光刻、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表3所示，其中，光生电流特性的表征方式为采用商用白色LED光源照射薄膜晶体管器件的沟道层，通过表征不同光强条件下器件的转移特性，提取器件阈值电压的变化情况来评估其强弱；阈值电压变化幅度大，表明其光生电流特性强，反之则弱。
表3
Figure PCTCN2021096784-appb-000003
由该表3可知，氧化铽和氧化铕的掺入对器件性能有非常明显的影响。首先，如表3的试验1所示，未掺杂氧化铽(m＝0)和氧化铕(n＝0)的氧化铟镓锌制备的器件没有表现出薄膜晶体管的“开关”特性(导通状态)，表明薄膜中的载流子浓度过高。如表3的试验2所示，通过掺入一定量(对应m＝0.05,n＝0)的氧化铽后，器件依然没有表现出来“开关”特性；进一步的，当继续掺入一定量的氧化铕后(对应m＝0.05,n＝0.0001)，器件表现出了“开关”特性；表明氧化铽对薄膜中载流子浓度的抑制效果不如氧化铕效果明显，对应的薄膜Hall数据见表3所示。为了进一步的研究氧化铕的影响，如表3的试验2～8所示，通过调节共溅射中靶材的溅射功率，可以制备出一系列不同铕含量的器件。具体的，掺杂少量氧化铕的器件(对应m＝0.05,n＝0.0001)具有相对较高的迁移率和较负的阈值电压。随着氧化铕含量的增加，器件阈值电压正向偏移，迁移率递减；说明氧化铕能有效调控器件的阈值电压，也即有效调控薄膜中的载流子浓度，可以从表3中的Hall数据进一步认证。当然，过量的氧化铕掺入后(如 m＝0.05，n＝0.15)，器件的迁移率明显退化，这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。将本实施例中所制备器件进行对应的光生电流特性测试，如图6(b)和6(c)所示，其对应的m值均为0.05，n值分别为0.001和0.05，当有光照射在器件上时，掺有少量氧化铕的器件(对应m＝0.05，n＝0.001)阈值电压未有明显偏移，亚阈值摆幅稍有退化；另外，掺入一定量的氧化铕后(对应m＝0.05，n＝0.05)，器件的阈值电压亦几乎没有变化，表现出了优异的光照稳定性，也即对应表3中的弱光生电流特性。需要指出的是，不同铕含量下(m＝0.05，n＝0～0.15)的器件光生电流特性都较弱，表明氧化铽的掺入能有效提高器件的光稳定性。
本实施例的试验结果表明，本发明在氧化铟镓锌基体材料中，掺入一定量的氧化铽和氧化铕能有效控制材料的载流子浓度、提高光稳定性。
实施例16：薄膜晶体管
一组薄膜晶体管，采用顶栅自对准型结构，其结构示意图如图2所示，设置有：基板01、缓冲层02、沟道层03、位于沟道层03之上的绝缘层04以及栅极05、覆盖在沟道层03和栅极上表面的间隔层06、在间隔层06之上并与沟道层03的两端电性相连的源极07-1和漏极07-2。
其中，基板01为硬质玻璃衬底。
缓冲层02为等离子增强化学气相沉积方式制备的氧化硅。
沟道层03的材料为实施例4的氧化铽、氧化镱共掺杂氧化铟镓锆半导体材料，厚度为30nm。
绝缘层04为氧化硅，厚度为300nm；栅极05为磁控溅射方式制备的钛/铜(Ti/Cu)叠层结构，厚度为20/400nm。
间隔层06为的氧化硅，厚度为300nm。
源极07-1以及漏极07-2的材料为磁控溅射方式制备的钛/铜(Ti/Cu)叠层结构，厚度为20/400nm。
为测试不同铽含量对器件性能的影响，沟道层03的材料为实施例4的氧化铽、氧化镱共掺杂氧化铟镓锆半导体材料，利用氧化铟镓锆(InGaZrO)、氧化铽掺杂氧化铟镓锆(Tb:InGaZrO)，以及氧化铽、氧化镱共掺杂的氧化铟镓锆(Tb-Yb:InGaZrO)三个陶瓷靶材，采用单个靶材或两个靶材共溅射的方式、通过调整两个靶材的溅射功率从而实现不同成分比例的薄膜制备而成。
本实施例的薄膜晶体管可以为仅包括基板01、沟道层03、绝缘层04、栅极05、间隔层06、源极07-1和漏极07-2的封闭结构，也可以进一步包括钝化层、以及像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化采用光刻、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表4所示，其中光生电流特性的表征方式为采用商用白色LED光源照射薄膜晶体管器件的沟道层03，通过表征不同光强条件下器件的转移特性，提取器件阈值电压的变化情况来评估其强弱；阈值电压变化幅度大，表明其光生电流特性强，反之则弱。
表4
Figure PCTCN2021096784-appb-000004
由该表4可知，氧化铽和氧化镱的掺入对器件性能有非常明显的影响。首先，如表4的试验1所示，未掺杂氧化铽(m＝0)和氧化镱(n＝0)的氧化铟镓锆制备的器件没有表现出薄膜晶体管的“开关”特性(导通状态)，表明薄膜中的载流子浓度过高。如表4的试验2所示，通过掺入一定量(对应m＝0,n＝0.05)的氧化镱后，器件表现出来“开关”特性，详见图7(a)所示，表明氧化镱的掺入能有效地抑制薄膜中的载流子浓度，对应的薄膜Hall数据见表4所示。进一步的，如表4的试验2～8所示，通过调节共溅射中靶材的溅射功率，可以制备出一系列不同铽含量的器件。需要指出的是，未掺氧化铽的器件(对应m＝0,n＝0.05)具有相对较高的迁移率，较小的亚阈值摆幅和较负的阈值电压，但是其光生电流特性极强，即在有光照射条件下器件特性发生非常明显的变化(阈值电压负向漂移，亚阈值摆幅退化严重)。但是，在掺入一定量的氧化铽后器件的光生电流特性得到了明显的抑制。当然，随着氧化铽含量的增加，器件的迁移率等特性也进一步退化，光生电流特性进一步改善。当过量的氧化铽掺入后 (如m＝0.15，n＝0.05)，器件的迁移率明显退化，虽然器件的光生电流特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光生电流特性测试，如图7(b)和7(c)所示，其对应的n值均为0.05，m值分别为0和0.05，当有光照射在器件上时，未掺氧化铽的器件(对应m＝0，n＝0.05)阈值电压明显负向偏移，亚阈值摆幅严重退化；而掺入一定量的氧化铽后(对应m＝0.05，n＝0.05)，器件的阈值电压几乎没有变化；表现出了优异的光照稳定性，也即对应表4中的弱光生电流特性。
本实施例的试验结果表明，本发明在氧化铟镓锆基体材料中，掺入一定量的氧化铽和氧化镱能有效控制材料的载流子浓度、提高光稳定性。
实施例17：薄膜晶体管
一组薄膜晶体管，采用自对准型结构，其结构示意图如图2所示，设置有：基板01、缓冲层02、沟道层03、位于沟道层03之上的绝缘层04以及栅极05、覆盖在沟道层03和栅极05上表面的间隔层06、在间隔层06之上并与沟道层03的两端电性相连的源极07-1和漏极07-2。
其中，基板01为硬质玻璃衬底。
缓冲层02为等离子增强化学气相沉积方式制备的氧化硅。
沟道层03的材料为实施例5的氧化铈、氧化铕共掺杂氧化铟锌半导体材料，厚度为20nm。
绝缘层04为氧化硅，厚度为300nm；栅极05为磁控溅射方式制备的钼/铜/钼(Mo/Cu/Mo)叠层结构，厚度为20/400/50nm。
间隔层06为的等离子增强化学气相沉积制备的氧化硅薄膜，厚度为300nm。
源极07-1以及漏极07-2的材料为磁控溅射方式制备的钼/铜/钼(Mo/Cu/Mo)叠层结构，厚度为20/400/50nm。
本实施例的薄膜晶体管可以为仅包括基板01、沟道层03、绝缘层04、栅极05、间隔层06、源极07-1和漏极07-2的封闭结构，也可以进一步包括钝化层、以及像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化采用光刻、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表5所示，其中光生电流特性的表征方式为采用商用白色LED光源照射薄膜晶体管器件的沟道层03，通过表征不同光强条件下器件的转移特性，提取器件阈值电压的变化情况来评估其强弱；阈值电压变化幅度大，表明其光生电流特性强，反之则弱。
表5
Figure PCTCN2021096784-appb-000005
由该表5可知，氧化铈和氧化铕的掺入对器件性能有非常明显的影响。首先，如表5的试验1所示，未掺杂氧化铈(m＝0)和氧化铕(n＝0)的氧化铟锌制备的器件没有表现出薄膜晶体管的“开关”特性(导通状态)，表明薄膜中的载流子浓度过高。如表5的试验2所示，通过掺入一定量(对应m＝0,n＝0.05) 的氧化铕后，器件表现出来“开关”特性，详见图8(a)所示，表明氧化铕的掺入能有效地抑制薄膜中的载流子浓度，对应的薄膜Hall数据见表5所示。进一步的，如表5的试验2～8所示，通过调节所配溶液中的组分，可以制备出一系列不同铈含量的器件。需要指出的是，未掺氧化铈的器件(对应m＝0,n＝0.05)具有相对较高的迁移率，较小的亚阈值摆幅和较负的阈值电压，但是其光生电流特性极强，即在有光照射条件下器件特性发生非常明显的变化(阈值电压负向漂移，亚阈值摆幅退化严重)。但是，在掺入一定量的氧化铈后器件的光生电流特性得到了明显的抑制。当然，随着氧化铈含量的增加，器件的迁移率等特性也进一步退化，光生电流特性进一步改善。当过量的氧化铈掺入后(如m＝0.15，n＝0.05)，器件的迁移率明显退化，虽然器件的光生电流特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光生电流特性测试，如图8(b)和8(c)所示，其对应的n值均为0.05，m值分别为0和0.05，当有光照射在器件上时，未掺氧化铈的器件(对应m＝0，n＝0.05)阈值电压明显负向偏移，亚阈值摆幅严重退化；而掺入一定量的氧化铈后(对应m＝0.05，n＝0.05)，器件的阈值电压几乎没有变化；表现出了优异的光照稳定性，也即对应表5中的弱光生电流特性。
本实施例的试验结果表明，本发明在氧化铟锌基体材料中，掺入一定量的氧化铈和氧化铕能有效控制材料的载流子浓度、提高光稳定性。
实施例18：薄膜晶体管
一组薄膜晶体管，采用刻蚀阻挡型结构，其结构示意图如图3所示，设置有：基板01、位于基板01之上的栅极05、位于基板01和栅极05之上的绝缘 层04、覆盖在绝缘层04上表面并与栅极05对应的沟道层03、刻蚀阻挡层08、相互间隔并与沟道层03的两端电性相连的源极07-1和漏极07-2、以及间隔层06。
其中，基板01为玻璃衬底，其上覆盖有缓冲层02氧化硅。
栅极05的材料为磁控溅射方式制备的钼铝钼(Mo/Al/Mo)金属叠层结构，厚度为50/300/50nm。
绝缘层04为化学气相沉积方式制备的氮化硅(Si 3N 4)和氧化硅(SiO 2)的叠层，厚度为250/50nm；其中氮化硅在下层和栅极05接触，氧化硅在上层和沟道层03接触。
为测试不同氧化镝含量对器件性能的影响，沟道层03的材料为实施例6的氧化镝、氧化镱共掺杂氧化铟锌钽半导体材料，利用氧化铟锌钽(InZnTaO)、氧化镱掺杂氧化铟锌钽(Yb:InZnTaO)，以及氧化镝、氧化镱共掺杂的氧化铟锌钽(Dy-Yb:InZnTaO)三个陶瓷靶材，采用单个靶材或两个共溅射的方式、通过调整两个靶材的溅射功率从而实现不同成分比例的薄膜制备而成。
刻蚀阻挡层08和间隔层06的材料为化学气相沉积方式制备的氧化硅(SiO 2)薄膜，厚度均为300nm，沉积温度为300℃。
源极07-1以及漏极07-2的材料为金属钼铝钼(Mo/Al/Mo)叠层结构，厚度为50/300/50nm。
另外，本实施例的薄膜晶体管可以为仅包括基板01、栅极05、绝缘层04、沟道层03、刻蚀阻挡层08、源极07-1和漏极07-2、钝化层的封闭结构，也可以进一步包括平坦层、反射电极、像素定义层等，还可以与其它器件集成等。
其中薄膜的图案化工序采用光刻工艺、并结合湿法或干法的刻蚀方式进行。
本实施例中的具体参数和制备的薄膜晶体管器件性能如表6所示，其中光 生电流特性的表征方式为采用商用白色LED光源照射薄膜晶体管器件的沟道层03，通过评估光照和无光照条件下器件的转移特性，提取器件阈值电压的变化情况来评估其强弱；阈值电压变化幅度大表明其光生电流特性强，反之则弱。
表6
Figure PCTCN2021096784-appb-000006
由该表6可知，氧化镝和氧化镱的掺入对器件性能有非常明显的影响。首先，如表6的试验1所示，未掺杂氧化镝(m＝0)和氧化镱(n＝0)的氧化铟锌钽制备的器件没有表现出薄膜晶体管的“开关”特性(导通状态)，表明薄膜中的载流子浓度过高。如表6的试验2所示，通过掺入一定量(对应m＝0,n＝0.05)的氧化镱后，器件表现出来“开关”特性，详见图9(a)所示，表明氧化镱的掺入能有效地抑制薄膜中的载流子浓度，对应的薄膜Hall数据见表6所示。进一步的，如表6的试验2～8所示，通过调节对应靶材的溅射功率，可以制备出一系列不同镝含量的器件。需要指出的是，未掺氧化镝的器件(对应m＝0,n＝0.05)具有相对较高的迁移率，较小的亚阈值摆幅和较负的阈值电压，但是其光生电 流特性极强，即在有光照射条件下器件特性发生非常明显的变化(阈值电压负向漂移，亚阈值摆幅退化严重)。但是，在掺入一定量的氧化镝后器件的光生电流特性得到了明显的抑制。当然，随着氧化镝含量的增加，器件的迁移率等特性也进一步退化，光生电流特性进一步改善。当过量的氧化镝掺入后(如m＝0.15，n＝0.05)，器件的迁移率明显退化，虽然器件的光生电流特性极弱，但是这极大地限制了其应用的领域。因此，在实际应用中需要权衡二者的关系，选择适当的掺入量。
将本实施例中所制备器件进行对应的光生电流特性测试，如图9(b)和9(c)所示，其对应的n值均为0.05，m值分别为0和0.05，当有光照射在器件上时，未掺氧化镝的器件(对应m＝0，n＝0.05)阈值电压明显负向偏移，亚阈值摆幅严重退化；而掺入一定量的氧化镝后(对应m＝0.05，n＝0.05)，器件的阈值电压几乎没有变化；表现出了优异的光照稳定性，也即对应表6中的弱光生电流特性。
本实施例的试验结果表明，本发明在氧化铟锌钽基体材料中，掺入一定量的氧化镝和氧化镱能有效控制材料的载流子浓度、提高光稳定性。
实施例19：显示面板
一种显示面板，包括上述实施例13-18中的薄膜晶体管，薄膜晶体管用于驱动显示面板中的显示单元。
实施例20：探测器
一种探测器，包括上述实施例13-18中的薄膜晶体管，薄膜晶体管用于驱动探测器的探测单元。
下面，对本发明实施的薄膜晶体管的各功能层做进一步的说明。
本发明中的基板没有特别限制，可以使用本领域中公知的基板01。如：硬 质的碱玻璃、无碱玻璃、石英玻璃、硅基板等；亦可为可弯曲的聚酰亚胺(PI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚苯乙烯(PS)、聚矾醚(PES)或者金属薄片等。
本发明中的栅极05材料没有特别限定，其可在本领域公知的材料中任意选取。如：透明导电氧化物(ITO、AZO、GZO、IZO、ITZO、FTO等)，金属(Mo、Al、Cu、Ag、Ti、Au、Ta、Cr、Ni等)及其合金、以及金属和氧化物(ITO/Ag/ITO、IZO/Ag/IZO等)、金属和金属叠设(Mo/Al/Mo、Ti/Al/Ti等)形成的复合导电薄膜。
栅极05薄膜的制备方法可以是溅射法、电镀、热蒸发和其他的沉积方式，优选溅射沉积方式，因为该方式制备的薄膜和基板01的粘附性好、均匀性优异、可以大面积制备。
这里，具体用哪种结构的栅电极需要根据所需要达到的技术参数而定，如透明显示中需要用到透明电极，其可由单层的ITO作为栅电极，亦可由ITO/Ag/ITO作为栅电极。另外，特殊领域的应用中需要有高温工艺，那栅电极可以选择可以抵抗高温的金属合金薄膜。
本发明中的绝缘层04材料没有特别限定，其可在本领域公知的材料中任意选取。如：氧化硅、氮化硅、氧化铝、氧化钽、氧化铪、氧化钇、以及高分子有机膜层等。
需要指出的是，这些绝缘薄膜的组分可以与理论上的化学计量比不一致。另外，绝缘层04可以是多种绝缘膜叠设而成，一方面形成更好的绝缘特性，另一方面可以改善沟道层03和绝缘层04的界面特性。而且，该绝缘层04的制备方式多样，可以是物理气相沉积、化学气相沉积、原子层沉积、激光沉积、阳极氧化或溶液法等方式制备。
湿法刻蚀采用的刻蚀液包括：磷酸、硝酸和冰醋酸的混合液或者基于双氧水的混合液。金属氧化物半导体材料在双氧水基的刻蚀液中的刻蚀速率小于1nm/min。干法刻蚀示例性的，可以选择等离子刻蚀工艺，刻蚀气体包括氯基或氟基气体。
金属氧化物半导体材料采用真空磁控溅射工艺过程中，可选单靶材溅射或多靶材共溅射，优选为单靶材溅射。
因为单靶材溅射可以提供重复性更好、更稳定的薄膜，而且薄膜的微观结构更易控制；而不至于像共溅射薄膜中，溅射粒子在重新组合的过程中会受到更多因素的干扰。
真空溅射沉积过程中，电源可以选取射频(RF)溅射、直流(DC)溅射或交流(AC)溅射，优选工业中常用的交流溅射。
溅射沉积过程中，溅射气压为0.1Pa～10Pa可选，优选为0.3Pa～0.7Pa。
溅射气压太低时，无法维持稳定的辉光溅射；溅射气压太高时，溅射粒子在向基板01沉积的过程中受到的散射明显增加，能量损耗增加，到达基板01后动能降低，形成的薄膜缺陷增加，从而严重影响器件的性能。
溅射沉积过程中，氧分压为0～1Pa可选，优选为0.001～0.5Pa，更优选为0.01～0.1Pa。
通常而言，溅射制备氧化物半导体的过程中，氧分压对薄膜的载流子浓度有着直接的影响，而且会引入一些氧空位相关的缺陷。过低的氧含量，可能会造成薄膜中氧严重失配，载流子浓度增加；而过高的氧空位会引起较多的弱结合键，降低器件的可靠性。
溅射沉积过程中，衬底温度优选为200～300℃。
沟道层薄膜沉积的过程中，一定的衬底温度可以有效改善溅射粒子到达基 板01后的结合方式，降低弱结合键的存在几率，提升器件的稳定性。当然，这一效果亦可以通过后续的退火处理等工艺来实现同样的功效。
沟道层03的厚度为2～100nm可选，优选为5～50nm，更优选为20～40nm。
本发明中的源漏电极材料没有特别限定，在不影响实现各种所需结构器件的前提下其可在本领域公知的材料中任意选取。如：透明导电氧化物(ITO、AZO、GZO、IZO、ITZO、FTO等)，金属(Mo、Al、Cu、Ag、Ti、Au、Ta、Cr、Ni等)及其合金、以及金属和氧化物(ITO/Ag/ITO、IZO/Ag/IZO等)、金属和金属叠设(Mo/Al/Mo、Ti/Al/Ti等)形成的复合导电薄膜。
源漏电极薄膜的制备方法可以是溅射法、热蒸发和其他的沉积方式，优选溅射沉积方式，因为该方式制备的薄膜和基板01的粘附性好、均匀性优异、可以大面积制备。
这里，需要特别说明的是，在制备背沟道刻蚀型结构的器件中，源漏电极和沟道层03需要有合适的刻蚀选择比，否则无法实现器件的制备。本发明实施例中湿法刻蚀的刻蚀液是基于工业界常规金属的刻蚀液(如：双氧水基刻蚀液)，主要是因为本发明的一种金属氧化物半导体材料能有效抵抗湿法双氧水基刻蚀液的刻蚀，其和金属(如钼、钼合金、钼/铝/钼等)具有很高的刻蚀选择比，该金属氧化物半导体层基本不受刻蚀液的影响，所制备的器件性能优异，稳定性好。另外，本发明实施例中的干法刻蚀是基于工业界常规的刻蚀气体(如氯基气体，氟基气体等)，其对本发明的氧化物半导体层影响甚微，所制备的器件性能优异，稳定性好。
本发明中的钝化层材料没有特别限定，其可在本领域公知的材料中任意选取。如：氧化硅、氮化硅、氧化铝、氧化钽、氧化铪、氧化钇、以及高分子有机膜层等。
需要指出的是，这些绝缘薄膜的组分可以与理论上的化学计量比不一致。另外，绝缘层04可以是多种绝缘膜叠设而成，一方面形成更好的绝缘特性，另一方面可以改善沟道层03和钝化层的界面特性。而且，该钝化层的制备方式多样，可以是物理气相沉积、化学气相沉积、原子层沉积、激光沉积或溶液法等方式制备。
下面，进一步对本发明实施的薄膜晶体管制备过程中的处理工艺进行说明。
相对而言，溅射制备的薄膜由于有高能等离子体的参与，所沉积薄膜的速率一般也较快；薄膜在沉积过程中没有足够的时间执行弛豫过程，这会造成一定比例的错位和应力残留于薄膜中。这需要后期的加热退火处理，而继续达到所需的相对稳态，改善薄膜的性能。
在本发明的实施中，退火处理大都设置在沟道层03沉积后，以及钝化层沉积后。一方面在沟道层03沉积后进行退火处理，可以有效改善沟道层03中的原位缺陷，提高沟道层03抵抗后续工艺中可能的损伤的能力。另一方面，在后续的钝化层沉积过程中，由于等离子体的参与和活性基团的改性作用，这可能需要一个“激活”的过程，进一步消除界面态和一些施主掺杂等效应。
另外，在本发明的实施中，处理的方式可以不仅仅是加热处理，可以包括等离子体处理界面(如绝缘层04/半导体界面，沟道层03/钝化层界面等)。
通过上述的处理工艺可以有效改善器件的性能，提高器件的稳定性。
上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受上述实施例的限制，其它的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。

Claims (10)

  1. 一种金属氧化物半导体，其特征在于，该金属氧化物半导体为：在含铟的金属氧化物MO-In 2O 3半导体中，分别掺入至少两种的稀土元素R的氧化物和稀土元素R’的氧化物，形成In xM yR nR’ mO z半导体材料，其中，x+y+m+n＝1，0.4≤x＜0.9999，0≤y＜0.5，0.0001≤(m+n)≤0.2，m＞0，n＞0，z＞0。
  2. 根据权利要求1所述的金属氧化物半导体，其特征在于，所述稀土元素R的氧化物为载流子浓度控制剂。
  3. 根据权利要求1所述的金属氧化物半导体，其特征在于，所述稀土元素R的氧化物为氧化镱、氧化铕中的一种或两种材料组合。
  4. 根据权利要求1所述的金属氧化物半导体，其特征在于，所述稀土元素R’的氧化物为光稳定剂。
  5. 根据权利要求1所述的金属氧化物半导体，其特征在于，所述稀土元素R’的氧化物为氧化镨、氧化铽、氧化铈、氧化镝中的一种或任意两种以上材料组合。
  6. 根据权利要求1所述的金属氧化物半导体，其特征在于，所述MO中，M为Zn、Ga、Sn、Ge、Sb、Al、Mg、Ti、Zr、Hf、Ta、W中的一种或任意两种以上材料组合。
  7. 根据权利要求1所述的金属氧化物半导体，其特征在于，所述金属氧化物半导体通过采用物理气相沉积工艺、化学气相沉积工艺、原子层沉积工艺、激光沉积工艺、反应离子沉积工艺、溶液法工艺中的任意一种工艺的方法制备成膜。
  8. 一种薄膜晶体管，该薄膜晶体管包括栅极、有源层、位于所述栅极和有源层之间的绝缘层、分别电性连接在所述有源层两端的源极和漏极、以及间隔层，其特征在于，所述有源层为权利要求1所述的金属氧化物半导体。
  9. 根据权利要求8所述的薄膜晶体管，其特征在于，所述间隔层为采用等离子增强化学气相沉积方式制备的氧化硅、氮化硅、氮氧化硅薄膜中的一种结构或者任意两种以上组成的叠层结构。
  10. 如权利要求8所述的薄膜晶体管在显示面板或探测器中的应用。
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