WO2020131395A1 - Multiplexed signal development in a memory device - Google Patents

Multiplexed signal development in a memory device Download PDF

Info

Publication number
WO2020131395A1
WO2020131395A1 PCT/US2019/064597 US2019064597W WO2020131395A1 WO 2020131395 A1 WO2020131395 A1 WO 2020131395A1 US 2019064597 W US2019064597 W US 2019064597W WO 2020131395 A1 WO2020131395 A1 WO 2020131395A1
Authority
WO
WIPO (PCT)
Prior art keywords
component
signal development
signal
memory cell
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2019/064597
Other languages
English (en)
French (fr)
Inventor
Dmitri A. YUDANOV
Shanky Kumar JAIN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to EP19900061.3A priority Critical patent/EP3899944A4/en
Priority to JP2021533432A priority patent/JP2022511972A/ja
Priority to CN201980082612.0A priority patent/CN113243031B/zh
Priority to CN202410511570.0A priority patent/CN118430606B/zh
Publication of WO2020131395A1 publication Critical patent/WO2020131395A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G11C11/2257—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2259—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2297—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0035—Evaluating degradation, retention or wearout, e.g. by counting writing cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G06F2212/1036—Life time enhancement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/608—Details relating to cache mapping
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2236—Copy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects

Definitions

  • FIGs. 5A and 5B illustrate examples of write operations that support multiplexed signal development in accordance with examples as disclosed herein.
  • FIG. 6 illustrates an example of a signal development component that supports multiplexed signal development in accordance with examples as disclosed herein.
  • FIG. 11 shows a block diagram of a memory controller that supports multiplexed signal development in accordance with examples as disclosed herein.
  • FIG. 12 shows a diagram of a system including a device that supports multiplexed signal development in accordance with examples as disclosed herein.
  • the throughput of the memory device may therefore be limited by the latency or cycle duration associated with the signal development component or signal development operations, which may affect latency- sensitive applications.
  • the method may further include coupling, during a third time interval that follows the first time interval, the first signal development component with a sense amplifier, and coupling, during a fourth time interval that follows one or both of the second time interval or the third time interval, the second signal development component with the sense amplifier.
  • the set of memory cells 105 may be part of a memory section 110 of the memory device 100 (e.g., including an array of memory cells 105), where in some examples a memory section 110 may refer to a contiguous tile of memory cells 105 (e.g., a contiguous set of elements of a semiconductor chip). In some examples, a memory section 110 may refer to the smallest set of memory cells 105 that may be biased in an access operation, or a smallest set of memory cells 105 that share a common node (e.g., a common plate line, a set of plate lines that are biased to a common voltage).
  • a common node e.g., a common plate line, a set of plate lines that are biased to a common voltage
  • an electrode may be coupled with (e.g., between) a memory cell 105 and an access line 120, or with (e.g., between) a memory cell 105 and an access line 130.
  • the term electrode may refer to an electrical conductor, or other electrical interface between components, and in some cases, may be employed as an electrical contact to a memory cell 105.
  • An electrode may include a trace, wire, conductive line, conductive layer, conductive pad, or the like, that provides a conductive path between elements or components of memory device 100.
  • a memory cell 105 may be set or written or refreshed by activating the relevant first access line 120, second access line 130, and/or third access line 140 (e.g., via a memory controller 170).
  • a logic state may be stored in the memory cell 105 (e.g., via a cell access signal, via a cell write signal).
  • Row component 125, column component 135, or plate component 145 may accept data, for example, via input/output component 160, to be written to the memory cells 105.
  • a write operation may be performed at least in part by a sense component 150, or a write operation may be configured to bypass a sense component 150.
  • the sense component 150-a may include a sense amplifier 290 (e.g., an amplifier component, an input/output amplifier, a“latch”), which may include a first node 291 and a second node 292.
  • the first node 291 and the second node 292 may be coupled with different access lines of a circuit (e.g., a signal line 285 and a reference line 275 of the circuit 200, respectively), or may be coupled with a common access line of a different circuit (not shown).
  • the first node 291 may be referred to as a signal node
  • the second node 292 may be referred to as a reference node.
  • Operation of the memory cell 105-a by varying the voltage of the cell plate 221 may be referred to as“moving the cell plate.” Biasing the plate line 215 and/or the digit line 210 may result in a voltage difference (e.g., the voltage of the digit line 210 minus the voltage of the plate line 215) across the capacitor 220.
  • the voltage difference may accompany a change in the stored charge on capacitor 220, where the magnitude of the change in stored charge may depend on the initial state of the capacitor 220 (e.g., whether the initial logic state stored a logic 1 or a logic 0).
  • the sense component 150-a may include a selection component 280 (e.g., a signal development component selection component, a multiplexer, a transistor network, a transistor array, a switching network, a switching array) coupled with or between a set of signal development components 250 (e.g., with or between a set of signal development lines 255) and the sense amplifier 290.
  • the selection component 280 may be configured to selectively couple or decouple any of the set of signal development components 250 or signal development lines 255 with the sense amplifier 290.
  • the selection component 280 may be associated with an access line, such as the signal line 285, for conveying signals (e.g., voltage, charge, current) between the selection component 280 and the sense amplifier 290.
  • the reference component 270 may be omitted and a reference voltage may be provided, for example, by accessing the memory cell 105-a or the digit line 210 to generate the reference voltage (e.g., in a self-referencing access operation). Other operations may be used to support selecting and/or sensing the memory cell 105-a.
  • the read signal development portion 410 may be associated with a relatively high latency or long duration (e.g., in comparison with a latch signal generation portion 420).
  • the latency associated with the operations of the read signal development portion 410 may be approximately 50 nanoseconds.
  • performing multiple read operations 400 may require integer multiples of the duration tAi - tAo (e.g., at least 2 * (tAi - tAo) to read two memory cells 105-b).
  • multiplexing signal development components 250-a e.g., via the selection component 280-a may reduce the amount of time required for the sense amplifier 290-a to read multiple memory cells 105-b.
  • Read signal development portion 410-a-4, latch signal generation portion 420-a-4, and rewrite signal development portion 430-a-4 may refer to, for example, a read operation of a memory cell 105-b-411 (e.g., of a domain 310-a-4, not shown, which may be associated with a signal development component 250-a-4).
  • Each of the signal development components 250-a-l, 250-a-2, 250-a-3, and 250-a-4 may be selectively coupled with the same sense amplifier 290-a via a selection component 280-a (e.g., based on a logical selection signal SDCM).
  • such a periodicity where domains 310-a are not independently controllable may be longer than the periodicity illustrated by time tA2 - tAo.
  • the advantages provided by the described signal development multiplexing e.g., a reduced latency when accessing multiple memory cells 105-b in parallel
  • the advantages by the described signal development multiplexing may also depend on whether domains 310-a are configured to be independently controllable, or are controlled via common access lines or common logical signals.
  • each digit line 210 of a domain 310-c may be mapped or routed to an array of integrator capacitors 610.
  • an arrangement could include a multiplexer (e.g., a selection component 280), and an array of capacitors 610 may be divided to isolate transfers and overlap transfers to or from FeRAM memory cells.
  • Such an arrangement may support charge transfer to or from the sense amplifier 290-c via a subset of the array of integrator capacitors 610 that are not involved in a current transfer with FeRAM memory cells 105.
  • the example of component arrangement 900 may address a problem of charge sharing across sockets (vertical metal wires that connect to multiple decks), which in some examples may be shared among decks or layers.
  • a user may interact with the device 1205 via the I/O component 1235 or via hardware components controlled by the I/O component 1235.
  • the I/O component 1235 may support accessing the memory cells 1220, including receiving information associated with the sensed logic state of one or more of the memory cells 1220, or providing information associated with writing a logic state of one or more of the memory cells 1220.
  • the output 1250 may represent a device or signal external to the device 1205 configured to receive output from the device 1205 or any of its components. Examples of the output 1250 may include a display, audio speakers, a printing device, another processor or printed circuit board, or other devices. In some cases, the output 1250 may be a peripheral element that interfaces with the device 1205 via the peripheral component s) 1240. In some cases, the output 1250 may be managed by the I/O component 1235.
  • the memory device may couple, during a second time interval subsequent to the first time interval and based on determining to access the second memory cell, a second signal development component with the amplifier component.
  • FIG. 15 shows a flowchart illustrating a method 1500 that supports multiplexed signal development in accordance with examples as disclosed herein.
  • the operations of the method 1500 may be performed to fabricate examples of the circuitry and apparatuses described with reference to FIGs. 1 through 12.
  • the method 1500 may be performed according to component arrangement 900 described with reference to FIG. 9A, or component arrangement 950 described with reference to FIG. 9B.
  • the plurality of memory cells may be distributed across one or more layers, and the signal storage elements of the plurality of signal development components may be distributed across one or more different layers.
  • the apparatus may be configured to generate a signal at a signal development component of the plurality of signal development components based at least in part on selectively coupling the signal development component with the amplifier
  • isolated refers to a relationship between components in which electrons are not presently capable of flowing between them; components are isolated from each other if there is an open circuit between them. For example, two components physically coupled by a switch may be isolated from each other when the switch is open.
  • a transistor or transistors discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate.
  • the terminals may be connected to other electronic elements through conductive materials, such as metals.
  • the source and drain may be conductive and may comprise a heavily-doped, or degenerate semiconductor region. The source and drain may be separated by a lightly-doped

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Human Computer Interaction (AREA)
  • Software Systems (AREA)
  • Databases & Information Systems (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Read Only Memory (AREA)
PCT/US2019/064597 2018-12-21 2019-12-05 Multiplexed signal development in a memory device Ceased WO2020131395A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP19900061.3A EP3899944A4 (en) 2018-12-21 2019-12-05 MULTIPLEX SIGNAL DEVELOPMENT IN A STORAGE DEVICE
JP2021533432A JP2022511972A (ja) 2018-12-21 2019-12-05 メモリデバイスにおける多重化信号展開
CN201980082612.0A CN113243031B (zh) 2018-12-21 2019-12-05 存储器装置中的多路复用信号开发
CN202410511570.0A CN118430606B (zh) 2018-12-21 2019-12-05 存储器装置中的多路复用信号开发

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862783388P 2018-12-21 2018-12-21
US62/783,388 2018-12-21
US16/700,983 2019-12-02
US16/700,983 US11360704B2 (en) 2018-12-21 2019-12-02 Multiplexed signal development in a memory device

Publications (1)

Publication Number Publication Date
WO2020131395A1 true WO2020131395A1 (en) 2020-06-25

Family

ID=71097667

Family Applications (7)

Application Number Title Priority Date Filing Date
PCT/US2019/064597 Ceased WO2020131395A1 (en) 2018-12-21 2019-12-05 Multiplexed signal development in a memory device
PCT/US2019/067844 Ceased WO2020132438A1 (en) 2018-12-21 2019-12-20 Write broadcast operations associated with a memory device
PCT/US2019/067838 Ceased WO2020132434A1 (en) 2018-12-21 2019-12-20 Signal development caching in a memory device
PCT/US2019/067832 Ceased WO2020132430A1 (en) 2018-12-21 2019-12-20 Page policies for signal development caching in a memory device
PCT/US2019/067834 Ceased WO2020132432A1 (en) 2018-12-21 2019-12-20 Content-addressable memory for signal development caching in a memory device
PCT/US2019/067829 Ceased WO2020132428A1 (en) 2018-12-21 2019-12-20 Signal development caching in a memory device
PCT/US2019/067840 Ceased WO2020132435A1 (en) 2018-12-21 2019-12-20 Read broadcast operations associated with a memory device

Family Applications After (6)

Application Number Title Priority Date Filing Date
PCT/US2019/067844 Ceased WO2020132438A1 (en) 2018-12-21 2019-12-20 Write broadcast operations associated with a memory device
PCT/US2019/067838 Ceased WO2020132434A1 (en) 2018-12-21 2019-12-20 Signal development caching in a memory device
PCT/US2019/067832 Ceased WO2020132430A1 (en) 2018-12-21 2019-12-20 Page policies for signal development caching in a memory device
PCT/US2019/067834 Ceased WO2020132432A1 (en) 2018-12-21 2019-12-20 Content-addressable memory for signal development caching in a memory device
PCT/US2019/067829 Ceased WO2020132428A1 (en) 2018-12-21 2019-12-20 Signal development caching in a memory device
PCT/US2019/067840 Ceased WO2020132435A1 (en) 2018-12-21 2019-12-20 Read broadcast operations associated with a memory device

Country Status (6)

Country Link
US (19) US11360704B2 (https=)
EP (7) EP3899944A4 (https=)
JP (9) JP2022511972A (https=)
CN (11) CN113243031B (https=)
TW (2) TW202230141A (https=)
WO (7) WO2020131395A1 (https=)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10235176B2 (en) 2015-12-17 2019-03-19 The Charles Stark Draper Laboratory, Inc. Techniques for metadata processing
TW201937393A (zh) 2018-02-02 2019-09-16 美商多佛微系統公司 用於安全初始化的策略編輯之系統和方法
SG11202007272QA (en) 2018-02-02 2020-08-28 Charles Stark Draper Laboratory Inc Systems and methods for policy execution processing
EP3746922B1 (en) 2018-02-02 2024-06-05 Dover Microsystems, Inc. Systems and methods for transforming instructions for metadata processing
EP3788488A1 (en) 2018-04-30 2021-03-10 Dover Microsystems, Inc. Systems and methods for checking safety properties
EP3877874A1 (en) 2018-11-06 2021-09-15 Dover Microsystems, Inc. Systems and methods for stalling host processor
EP3881190A1 (en) 2018-11-12 2021-09-22 Dover Microsystems, Inc. Systems and methods for metadata encoding
WO2020132012A1 (en) 2018-12-18 2020-06-25 Dover Microsystems, Inc. Systems and methods for data lifecycle protection
US11360704B2 (en) 2018-12-21 2022-06-14 Micron Technology, Inc. Multiplexed signal development in a memory device
EP3912061A1 (en) 2019-01-18 2021-11-24 Dover Microsystems, Inc. Systems and methods for metadata classification
US11062763B2 (en) * 2019-04-09 2021-07-13 Micron Technology, Inc. Memory array with multiplexed digit lines
US11176065B2 (en) * 2019-08-12 2021-11-16 Micron Technology, Inc. Extended memory interface
US11842169B1 (en) 2019-09-25 2023-12-12 Amazon Technologies, Inc. Systolic multiply delayed accumulate processor architecture
WO2021076871A1 (en) 2019-10-18 2021-04-22 Dover Microsystems, Inc. Systems and methods for updating metadata
US11816446B2 (en) 2019-11-27 2023-11-14 Amazon Technologies, Inc. Systolic array component combining multiple integer and floating-point data types
US11467806B2 (en) 2019-11-27 2022-10-11 Amazon Technologies, Inc. Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
US12253944B2 (en) 2020-03-03 2025-03-18 Dover Microsystems, Inc. Systems and methods for caching metadata
JP2021140842A (ja) * 2020-03-04 2021-09-16 キオクシア株式会社 メモリ回路、情報処理回路、及び情報処理装置
US11308027B1 (en) 2020-06-29 2022-04-19 Amazon Technologies, Inc. Multiple accumulate busses in a systolic array
US11232062B1 (en) 2020-06-29 2022-01-25 Amazon Technologies, Inc. Parallelism within a systolic array using multiple accumulate busses
US11113233B1 (en) * 2020-06-29 2021-09-07 Amazon Technologies, Inc. Multiple busses in a grouped systolic array
US11422773B1 (en) 2020-06-29 2022-08-23 Amazon Technologies, Inc. Multiple busses within a systolic array processing element
KR102342994B1 (ko) * 2020-07-21 2021-12-24 고려대학교 산학협력단 산술 연산을 지원하는 인메모리 컴퓨팅
WO2022064315A1 (ja) * 2020-09-25 2022-03-31 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
US12124576B2 (en) 2020-12-23 2024-10-22 Dover Microsystems, Inc. Systems and methods for policy violation processing
US11907556B2 (en) * 2021-02-18 2024-02-20 Micron Technology, Inc. Data relocation operation techniques
US12423058B2 (en) 2021-06-30 2025-09-23 Amazon Technologies, Inc. Systolic array with input reduction to multiple reduced inputs
US11880682B2 (en) 2021-06-30 2024-01-23 Amazon Technologies, Inc. Systolic array with efficient input reduction and extended array performance
US11727981B2 (en) * 2021-07-07 2023-08-15 Micron Technology, Inc. Sense amplifier with digit line multiplexing
US11837269B2 (en) * 2021-08-31 2023-12-05 Micron Technology, Inc. Deck-level signal development cascodes
CN113641626B (zh) * 2021-10-18 2022-02-18 睿思芯科(深圳)技术有限公司 一种sram读写控制方法及行缓冲控制器
US20230214323A1 (en) * 2021-12-30 2023-07-06 Micron Technology, Inc. Selectable cache writing policies for cache management
CN116417027A (zh) * 2021-12-31 2023-07-11 长鑫存储技术有限公司 一种控制放大方法及电路、灵敏放大器和半导体存储器
US12142342B2 (en) 2022-02-21 2024-11-12 Industrial Technology Research Institute Memory circuit with sense amplifier calibration mechanism
US12517700B1 (en) 2022-03-30 2026-01-06 Amazon Technologies, Inc. Systolic array with output rounding for multiple source/destination data type pairs
US11967396B2 (en) 2022-04-27 2024-04-23 Nvidia Corp. Multi-rank receiver
US11973501B2 (en) 2022-04-27 2024-04-30 Nvidia Corp. Digitally controlled unified receiver for multi-rank system
US11881255B2 (en) * 2022-04-27 2024-01-23 Nvidia Corp. Look ahead switching circuit for a multi-rank system
US12354642B2 (en) 2022-04-27 2025-07-08 Nvidia Corp. Training and configuration of reference voltage generators in a multi-rank circuit system
US11978496B2 (en) 2022-04-27 2024-05-07 Nvidia Corp. Distributed global and local reference voltage generation
US12236125B2 (en) * 2022-04-28 2025-02-25 Micron Technology, Inc. Performance monitoring for a memory system
US12216917B2 (en) * 2022-05-31 2025-02-04 Changxin Memory Technologies, Inc. Data processing circuit and method, and semiconductor memory
JP2024002003A (ja) * 2022-06-23 2024-01-11 キオクシア株式会社 メモリデバイス及びメモリシステム
US12204789B2 (en) * 2022-08-29 2025-01-21 Micron Technology, Inc. Memory phase monitoring and scheduling system using memory usage statistics
WO2024054448A1 (en) * 2022-09-10 2024-03-14 Rambus Inc. Split-entry dram cache
KR20240050918A (ko) * 2022-10-12 2024-04-19 삼성전자주식회사 비휘발성 메모리 장치, 저장 장치, 스토리지 컨트롤러의 동작 방법, 및 저장 장치의 동작 방법
US12608316B2 (en) * 2023-01-31 2026-04-21 Micron Technology, Inc. Sense amplifiers as static random access memory cache
CN116149572B (zh) 2023-02-24 2025-08-15 合肥兆芯电子有限公司 映射表更新方法、存储器存储装置及存储器控制电路单元
US20240338150A1 (en) * 2023-04-05 2024-10-10 Mobileye Vision Technologies Ltd. Apparatus, system, and method of data array transformation
TWI859088B (zh) * 2024-03-12 2024-10-11 世界先進積體電路股份有限公司 故障防護電路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060056264A1 (en) * 2004-09-16 2006-03-16 Worley James L Variable boost voltage row driver circuit and method and memory device and system including same
US20070097768A1 (en) * 2005-10-31 2007-05-03 International Business Machines Corporation System and method for capacitive mis-match bit-line sensing
US20170133096A1 (en) * 2015-11-05 2017-05-11 Pil Seon YOO Nonvolatile memory device and method of operating the same
WO2017136203A1 (en) * 2016-02-01 2017-08-10 Micron Technology, Inc. Cell-based reference voltage generation
US20180358078A1 (en) * 2016-03-11 2018-12-13 Micron Technology, Inc. Memory cell sensing with storage component isolation

Family Cites Families (125)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493026A (en) 1982-05-26 1985-01-08 International Business Machines Corporation Set associative sector cache
JPH0793031B2 (ja) * 1987-02-12 1995-10-09 株式会社日立製作所 アクセス制御システム
JPH01166850A (ja) 1987-12-24 1989-06-30 Mitsubishi Heavy Ind Ltd 銅又はアルミニウム合金鋳物の製造法
JPH0315958A (ja) 1989-06-14 1991-01-24 Hitachi Ltd キャッシュメモリシステム
JP2938511B2 (ja) 1990-03-30 1999-08-23 三菱電機株式会社 半導体記憶装置
JP2951786B2 (ja) 1992-02-03 1999-09-20 三菱電機株式会社 半導体記憶装置
US5341501A (en) 1991-10-04 1994-08-23 Bull Hn Information Systems Inc. Processor bus access
US5377154A (en) 1992-01-31 1994-12-27 Oki Electric Industry Co., Ltd. Multiple serial-access memory
JP3672940B2 (ja) 1994-01-06 2005-07-20 沖電気工業株式会社 半導体記憶装置
US5596521A (en) 1994-01-06 1997-01-21 Oki Electric Industry Co., Ltd. Semiconductor memory with built-in cache
JP3085843B2 (ja) 1994-01-11 2000-09-11 沖電気工業株式会社 半導体記憶回路
US6320778B1 (en) * 1994-01-06 2001-11-20 Oki Electric Industry Co., Ltd. Semiconductor memory with built-in cache
JP3181479B2 (ja) 1994-12-15 2001-07-03 沖電気工業株式会社 半導体記憶装置
US5787267A (en) 1995-06-07 1998-07-28 Monolithic System Technology, Inc. Caching method and circuit for a memory system with circuit module architecture
JP3352577B2 (ja) 1995-12-21 2002-12-03 インターナショナル・ビジネス・マシーンズ・コーポレーション 記憶装置
JP4008072B2 (ja) * 1997-08-21 2007-11-14 富士通株式会社 半導体記憶装置
JPH1173763A (ja) * 1997-08-28 1999-03-16 Toshiba Corp 半導体集積回路装置
JP3161384B2 (ja) 1997-09-16 2001-04-25 日本電気株式会社 半導体記憶装置とそのアクセス方法
US6205076B1 (en) 1998-03-27 2001-03-20 Fujitsu Limited Destructive read type memory circuit, restoring circuit for the same and sense amplifier
JPH11339466A (ja) 1998-03-27 1999-12-10 Fujitsu Ltd 破壊読出型メモリ回路、リストア用アドレス記憶・制御回路及びセンスアンプ
JP2954178B1 (ja) 1998-06-26 1999-09-27 甲府日本電気株式会社 可変式キャッシュ方式
JP2001006379A (ja) 1999-06-16 2001-01-12 Fujitsu Ltd 複写、移動機能を有するフラッシュメモリ
JP2001005725A (ja) 1999-06-21 2001-01-12 Hitachi Ltd キャッシュ記憶装置
KR100373849B1 (ko) 2000-03-13 2003-02-26 삼성전자주식회사 어소시어티브 캐시 메모리
US6587384B2 (en) 2001-04-21 2003-07-01 Hewlett-Packard Development Company, L.P. Multi-function serial I/O circuit
US6829682B2 (en) 2001-04-26 2004-12-07 International Business Machines Corporation Destructive read architecture for dynamic random access memories
US6552944B2 (en) 2001-05-31 2003-04-22 International Business Machines Corporation Single bitline direct sensing architecture for high speed memory device
KR100387529B1 (ko) 2001-06-11 2003-06-18 삼성전자주식회사 랜덤 억세스 가능한 메모리 셀 어레이를 갖는 불휘발성반도체 메모리 장치
US6480424B1 (en) * 2001-07-12 2002-11-12 Broadcom Corporation Compact analog-multiplexed global sense amplifier for RAMS
US6614691B2 (en) 2001-12-12 2003-09-02 Micron Technology, Inc. Flash memory having separate read and write paths
US20040230288A1 (en) 2002-04-17 2004-11-18 Rosenthal Arthur L. Medical devices adapted for controlled in vivo structural change after implantation
CN1480950A (zh) 2002-09-05 2004-03-10 力旺电子股份有限公司 即时多路复用且可快速复制数据的闪速存储器装置
US6940753B2 (en) 2002-09-24 2005-09-06 Sandisk Corporation Highly compact non-volatile memory and method therefor with space-efficient data registers
JP4439838B2 (ja) 2003-05-26 2010-03-24 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及びその制御方法
US6999370B2 (en) 2003-08-06 2006-02-14 International Business Machines Corporation Low power circuits with small voltage swing transmission, voltage regeneration, and wide bandwidth architecture
JP4107269B2 (ja) 2004-02-23 2008-06-25 ソニー株式会社 固体撮像装置
US7009880B1 (en) * 2004-08-17 2006-03-07 Programmable Microelectronics Corporation Non-volatile memory architecture to improve read performance
JP4956922B2 (ja) 2004-10-27 2012-06-20 ソニー株式会社 記憶装置
KR100640594B1 (ko) 2004-10-27 2006-11-01 삼성전자주식회사 데이터 스트로브 신호를 모니터링하여 적응적으로 데이터입출력 신호를 래치하는 인터페이스 회로 및 이를구비하는 메모리 시스템
US7216272B2 (en) 2005-02-23 2007-05-08 Texas Instruments Incorporated Method for reducing SRAM test time by applying power-up state knowledge
JP5005179B2 (ja) 2005-03-23 2012-08-22 ソニー株式会社 固体撮像装置
US7206230B2 (en) 2005-04-01 2007-04-17 Sandisk Corporation Use of data latches in cache operations of non-volatile memories
JP4756581B2 (ja) 2005-07-21 2011-08-24 ルネサスエレクトロニクス株式会社 半導体記憶装置
US20070083783A1 (en) 2005-08-05 2007-04-12 Toru Ishihara Reducing power consumption at a cache
JP2007080325A (ja) * 2005-09-12 2007-03-29 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR20070066185A (ko) 2005-12-21 2007-06-27 삼성전자주식회사 데이터 라인을 공유하는 반도체 메모리 장치의 병렬 비트테스트 회로
US7647536B2 (en) * 2005-12-30 2010-01-12 Intel Corporation Repair bits for a low voltage cache
US7516275B2 (en) * 2006-04-25 2009-04-07 International Business Machines Corporation Pseudo-LRU virtual counter for a locking cache
JP4299848B2 (ja) 2006-08-09 2009-07-22 エルピーダメモリ株式会社 半導体記憶装置
US20080080266A1 (en) 2006-09-27 2008-04-03 Khellah Muhammad M Memory driver circuits with embedded level shifters
CN101558391B (zh) * 2006-12-15 2013-10-16 密克罗奇普技术公司 用于微处理器的可配置高速缓冲存储器
JP2008257773A (ja) 2007-04-02 2008-10-23 Toshiba Corp 不揮発性半導体記憶装置、不揮発性半導体記憶装置の制御方法、不揮発性半導体記憶システム、及びメモリカード
US7613060B2 (en) 2007-05-21 2009-11-03 Micron Technology, Inc. Methods, circuits, and systems to select memory regions
WO2009034603A1 (ja) 2007-09-14 2009-03-19 Fujitsu Microelectronics Limited 半導体メモリ
JP2009123298A (ja) * 2007-11-16 2009-06-04 Renesas Technology Corp 半導体集積回路装置
US8090999B2 (en) 2008-06-10 2012-01-03 Micron Technology, Inc. Memory media characterization for development of signal processors
US20140325129A1 (en) 2008-12-31 2014-10-30 Micron Technology, Inc. Method and apparatus for active range mapping for a nonvolatile memory device
KR20100113389A (ko) 2009-04-13 2010-10-21 주식회사 하이닉스반도체 라이트 동작을 제어하는 반도체 집적 회로
US8495299B2 (en) 2009-11-16 2013-07-23 Microsoft Corporation Non-blocking data transfer via memory cache manipulation
US20110149667A1 (en) 2009-12-23 2011-06-23 Fatih Hamzaoglu Reduced area memory array by using sense amplifier as write driver
JP5374412B2 (ja) 2010-02-24 2013-12-25 ラピスセミコンダクタ株式会社 半導体記憶回路
KR20110097438A (ko) * 2010-02-25 2011-08-31 삼성전자주식회사 메모리 시스템, 그리고 그것의 동작 방법
KR20110124992A (ko) 2010-05-12 2011-11-18 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 시스템
US8760953B2 (en) 2010-10-01 2014-06-24 Qualcomm Incorporated Sense amplifier with selectively powered inverter
KR101189011B1 (ko) * 2010-10-26 2012-10-08 에스케이하이닉스 주식회사 반도체 메모리 장치
US8385140B2 (en) 2010-11-18 2013-02-26 Advanced Micro Devices, Inc. Memory elements having shared selection signals
US20120151232A1 (en) 2010-12-12 2012-06-14 Fish Iii Russell Hamilton CPU in Memory Cache Architecture
US8570827B2 (en) 2010-12-20 2013-10-29 Apple Inc. Physical organization of memory to reduce power consumption
JP5443420B2 (ja) * 2011-03-23 2014-03-19 株式会社東芝 半導体記憶装置
JP2012203938A (ja) * 2011-03-24 2012-10-22 Toshiba Corp 半導体記憶装置
US8743630B2 (en) * 2011-05-23 2014-06-03 Infineon Technologies Ag Current sense amplifier with replica bias scheme
US8645752B2 (en) 2011-11-08 2014-02-04 Micron Technology, Inc. Apparatuses and methods for operating a memory device
US20130145097A1 (en) * 2011-12-05 2013-06-06 Qualcomm Incorporated Selective Access of a Store Buffer Based on Cache State
US8873329B1 (en) 2012-01-17 2014-10-28 Rambus Inc. Patterned memory page activation
JP2013196717A (ja) * 2012-03-16 2013-09-30 Toshiba Corp 半導体記憶装置およびその駆動方法
JP5978771B2 (ja) 2012-05-31 2016-08-24 ソニー株式会社 信号処理装置および方法、撮像素子、並びに、撮像装置
US9257154B2 (en) 2012-11-29 2016-02-09 Micron Technology, Inc. Methods and apparatuses for compensating for source voltage
US9013930B2 (en) 2012-12-20 2015-04-21 Winbond Electronics Corp. Memory device with interleaved high-speed reading function and method thereof
KR20140080216A (ko) * 2012-12-20 2014-06-30 에스케이하이닉스 주식회사 반도체 메모리 시스템 및 그의 동작 방법
US9509317B2 (en) * 2013-01-31 2016-11-29 Oracle International Corporation Rotational synchronizer circuit for metastablity resolution
US9093175B2 (en) 2013-03-27 2015-07-28 International Business Machines Corporation Signal margin centering for single-ended eDRAM sense amplifier
US9443602B2 (en) 2013-08-23 2016-09-13 Kabushiki Kaisha Toshiba Storage device and data latch timing adjustment method
CN110233978B (zh) 2014-02-07 2022-03-11 拉姆伯斯公司 馈通补偿图像传感器
US9384830B2 (en) 2014-05-06 2016-07-05 Micron Technology, Inc. Apparatuses and methods for performing multiple memory operations
US9535844B1 (en) 2014-06-30 2017-01-03 EMC IP Holding Company LLC Prioritization for cache systems
KR102309471B1 (ko) 2014-12-19 2021-10-07 에스케이하이닉스 주식회사 데이터 처리 시스템 및 데이터 처리 시스템의 동작 방법
CN107408405B (zh) 2015-02-06 2021-03-05 美光科技公司 用于并行写入到多个存储器装置位置的设备及方法
US9785211B2 (en) 2015-02-13 2017-10-10 Qualcomm Incorporated Independent power collapse methodology
KR101994952B1 (ko) 2015-03-27 2019-07-01 후아웨이 테크놀러지 컴퍼니 리미티드 데이터 처리 방법, 메모리 관리 유닛, 및 메모리 제어 장치
US9582430B2 (en) 2015-03-27 2017-02-28 Intel Corporation Asymmetric set combined cache
US9728243B2 (en) * 2015-05-11 2017-08-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device or electronic component including the same
US10073786B2 (en) * 2015-05-28 2018-09-11 Micron Technology, Inc. Apparatuses and methods for compute enabled cache
US9627016B2 (en) 2015-09-10 2017-04-18 Cypress Semiconductor Corporation Systems, methods, and devices for parallel read and write operations
US10303372B2 (en) 2015-12-01 2019-05-28 Samsung Electronics Co., Ltd. Nonvolatile memory device and operation method thereof
US9934837B2 (en) 2016-03-01 2018-04-03 Micron Technology, Inc. Ground reference scheme for a memory cell
US9997232B2 (en) * 2016-03-10 2018-06-12 Micron Technology, Inc. Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations
US9552864B1 (en) * 2016-03-11 2017-01-24 Micron Technology, Inc. Offset compensation for ferroelectric memory cell sensing
US9761312B1 (en) * 2016-03-16 2017-09-12 Micron Technology, Inc. FeRAM-DRAM hybrid memory
US9997250B2 (en) 2016-03-17 2018-06-12 SK Hynix Inc. Non-volatile memory device with a plurality of cache latches and switches and method for operating non-volatile memory device
US10474581B2 (en) 2016-03-25 2019-11-12 Micron Technology, Inc. Apparatuses and methods for cache operations
US9542980B1 (en) 2016-03-29 2017-01-10 Nanya Technology Corp. Sense amplifier with mini-gap architecture and parallel interconnect
US10192606B2 (en) * 2016-04-05 2019-01-29 Micron Technology, Inc. Charge extraction from ferroelectric memory cell using sense capacitors
KR102514045B1 (ko) * 2016-04-21 2023-03-24 삼성전자주식회사 저항성 메모리 장치 및 이를 포함하는 메모리 시스템
US10082964B2 (en) 2016-04-27 2018-09-25 Micron Technology, Inc Data caching for ferroelectric memory
CN108701077B (zh) 2016-05-03 2023-11-10 拉姆伯斯公司 具有高效写入操作的存储器组件
TWI734781B (zh) * 2016-05-20 2021-08-01 日商半導體能源研究所股份有限公司 半導體裝置、電子構件及電子裝置
US10090027B2 (en) 2016-05-25 2018-10-02 Ememory Technology Inc. Memory system with low read power
US10372566B2 (en) 2016-09-16 2019-08-06 Micron Technology, Inc. Storing memory array operational information in nonvolatile subarrays
KR102662026B1 (ko) * 2016-09-30 2024-05-03 삼성전자주식회사 트립 전압의 변화를 보상하는 메모리 장치 및 그것의 읽기 방법
US10249351B2 (en) 2016-11-06 2019-04-02 Intel Corporation Memory device with flexible internal data write control circuitry
US10503649B2 (en) * 2016-11-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit and address mapping method for cache memory
US10490239B2 (en) 2016-12-27 2019-11-26 Intel Corporation Programmable data pattern for repeated writes to memory
US10290341B2 (en) * 2017-02-24 2019-05-14 Micron Technology, Inc. Self-reference for ferroelectric memory
WO2018163252A1 (ja) 2017-03-06 2018-09-13 ゼンテルジャパン株式会社 半導体記憶システム
JP6943600B2 (ja) * 2017-04-18 2021-10-06 ラピスセミコンダクタ株式会社 半導体記憶装置および半導体記憶装置の読み出し方法
US10650899B2 (en) 2017-04-27 2020-05-12 Everspin Technologies, Inc. Delayed write-back in memory with calibration support
US10789175B2 (en) 2017-06-01 2020-09-29 Mellanox Technologies Ltd. Caching policy in a multicore system on a chip (SOC)
US10153020B1 (en) * 2017-06-09 2018-12-11 Micron Technology, Inc. Dual mode ferroelectric memory cell operation
US10153022B1 (en) * 2017-06-09 2018-12-11 Micron Technology, Inc Time-based access of a memory cell
US10510383B2 (en) 2017-10-03 2019-12-17 Sandisk Technologies Llc State dependent sense circuits and pre-charge operations for storage devices
US10667621B2 (en) * 2018-04-19 2020-06-02 Micron Technology, Inc. Multi-stage memory sensing
US10395710B1 (en) * 2018-05-21 2019-08-27 Avalanche Technology, Inc. Magnetic memory emulating dynamic random access memory (DRAM)
KR102695482B1 (ko) * 2018-08-03 2024-08-14 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
US11360704B2 (en) 2018-12-21 2022-06-14 Micron Technology, Inc. Multiplexed signal development in a memory device
JP2021197099A (ja) 2020-06-18 2021-12-27 富士フイルムビジネスイノベーション株式会社 情報処理装置及びプログラム

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060056264A1 (en) * 2004-09-16 2006-03-16 Worley James L Variable boost voltage row driver circuit and method and memory device and system including same
US20070097768A1 (en) * 2005-10-31 2007-05-03 International Business Machines Corporation System and method for capacitive mis-match bit-line sensing
US20170133096A1 (en) * 2015-11-05 2017-05-11 Pil Seon YOO Nonvolatile memory device and method of operating the same
WO2017136203A1 (en) * 2016-02-01 2017-08-10 Micron Technology, Inc. Cell-based reference voltage generation
US20180358078A1 (en) * 2016-03-11 2018-12-13 Micron Technology, Inc. Memory cell sensing with storage component isolation

Also Published As

Publication number Publication date
US20220044713A1 (en) 2022-02-10
US11372595B2 (en) 2022-06-28
EP3899940A4 (en) 2022-10-12
EP3899734A4 (en) 2022-10-26
EP3899733A4 (en) 2022-10-19
EP3899734A1 (en) 2021-10-27
US20230066051A1 (en) 2023-03-02
CN113196247A (zh) 2021-07-30
WO2020132435A1 (en) 2020-06-25
CN113196246A (zh) 2021-07-30
JP2022183340A (ja) 2022-12-08
EP3899941A1 (en) 2021-10-27
CN113228175B (zh) 2025-08-05
CN113243031A (zh) 2021-08-10
TWI762840B (zh) 2022-05-01
WO2020132432A1 (en) 2020-06-25
US20220076733A1 (en) 2022-03-10
JP7175398B2 (ja) 2022-11-18
JP7105376B2 (ja) 2022-07-22
JP2022514602A (ja) 2022-02-14
US20240329885A1 (en) 2024-10-03
US20220050776A1 (en) 2022-02-17
JP2022510492A (ja) 2022-01-26
CN113196248B (zh) 2024-09-10
US12481461B2 (en) 2025-11-25
CN113228174B (zh) 2023-03-31
CN113243031B (zh) 2024-05-14
CN113196247B (zh) 2024-04-23
US20200201781A1 (en) 2020-06-25
US20200202907A1 (en) 2020-06-25
CN120581049A (zh) 2025-09-02
EP3899733A1 (en) 2021-10-27
US20220020424A1 (en) 2022-01-20
US20220020414A1 (en) 2022-01-20
JP2022514345A (ja) 2022-02-10
US11669278B2 (en) 2023-06-06
CN113196394A (zh) 2021-07-30
CN120877798A (zh) 2025-10-31
US11520529B2 (en) 2022-12-06
CN113228175A (zh) 2021-08-06
US11360704B2 (en) 2022-06-14
US20220391144A1 (en) 2022-12-08
US20220044723A1 (en) 2022-02-10
US11221797B2 (en) 2022-01-11
EP3899732A4 (en) 2022-10-19
US11726714B2 (en) 2023-08-15
EP3899941A4 (en) 2022-10-12
US11693599B2 (en) 2023-07-04
US20250372143A1 (en) 2025-12-04
WO2020132438A1 (en) 2020-06-25
JP7165269B2 (ja) 2022-11-02
CN113196394B (zh) 2025-06-24
US11709634B2 (en) 2023-07-25
EP3899732A1 (en) 2021-10-27
JP2022511972A (ja) 2022-02-01
WO2020132430A1 (en) 2020-06-25
TW202230141A (zh) 2022-08-01
CN113228174A (zh) 2021-08-06
EP3899942A4 (en) 2022-10-12
TW202044045A (zh) 2020-12-01
US12353762B2 (en) 2025-07-08
US20220261191A1 (en) 2022-08-18
US11934703B2 (en) 2024-03-19
CN118430606A (zh) 2024-08-02
US11340833B2 (en) 2022-05-24
JP2022511949A (ja) 2022-02-01
CN113196248A (zh) 2021-07-30
CN118295934A (zh) 2024-07-05
EP3899944A1 (en) 2021-10-27
CN118430606B (zh) 2026-01-23
EP3899942A1 (en) 2021-10-27
CN113196246B (zh) 2024-05-14
WO2020132428A1 (en) 2020-06-25
JP2022514073A (ja) 2022-02-09
WO2020132434A1 (en) 2020-06-25
US20220300210A1 (en) 2022-09-22
US20220206718A1 (en) 2022-06-30
US12189988B2 (en) 2025-01-07
JP2022168310A (ja) 2022-11-04
US20250173093A1 (en) 2025-05-29
US11989450B2 (en) 2024-05-21
US20240281171A1 (en) 2024-08-22
US20200201576A1 (en) 2020-06-25
JP2022514341A (ja) 2022-02-10
US12411637B2 (en) 2025-09-09
EP3899940A1 (en) 2021-10-27
US20260056683A1 (en) 2026-02-26
US11656801B2 (en) 2023-05-23
EP3899944A4 (en) 2022-09-28

Similar Documents

Publication Publication Date Title
US11709634B2 (en) Multiplexed signal development in a memory device
US10930324B2 (en) Self-referencing sensing schemes with coupling capacitance
CN112740330B (zh) 用于存储器装置中的基于区段的数据保护的存取方案
US10937487B2 (en) Differential amplifier schemes for sensing memory cells

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19900061

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021533432

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019900061

Country of ref document: EP

Effective date: 20210721