WO2020003420A1 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- WO2020003420A1 WO2020003420A1 PCT/JP2018/024426 JP2018024426W WO2020003420A1 WO 2020003420 A1 WO2020003420 A1 WO 2020003420A1 JP 2018024426 W JP2018024426 W JP 2018024426W WO 2020003420 A1 WO2020003420 A1 WO 2020003420A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 238000000034 method Methods 0.000 title claims description 29
- 239000000463 material Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000010408 film Substances 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 27
- 239000010409 thin film Substances 0.000 claims description 9
- 238000004132 cross linking Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000004380 ashing Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000000052 comparative effect Effects 0.000 description 8
- 238000000059 patterning Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Definitions
- the present invention relates to a method for manufacturing a semiconductor device.
- the resist for forming the recess and the resist for forming the gate electrode were separately patterned.
- misalignment occurs in the first and second patterning, so that the position of the gate electrode in the recess varies. Therefore, the characteristics fluctuate, and the product yield decreases. Further, since two patterning operations are required, the number of steps is increased and the manufacturing cost is increased.
- a method has been proposed in which a recess is formed using a resist having two openings, large and small, and the smaller opening is closed with an insulating film to form a gate electrode in the recess through the larger opening (for example, see Patent Document 1).
- the insulating film is dry-etched, the semiconductor immediately below the gate electrode is damaged. Accordingly, the number of carriers decreases, and the number of defects and traps increases.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the yield and reliability of products and reducing the manufacturing cost.
- a step of applying a resist on a semiconductor substrate to form a first opening and a second opening narrower than the first opening in the resist Forming a continuous recess under the first and second openings by wet-etching the semiconductor substrate using a mask as a mask; and, after forming the recess, a crosslinking reaction of a shrink material with the resist. Closing the second opening without closing the first opening, and forming a gate electrode in the recess via the first opening after closing the second opening. And a step.
- the semiconductor substrate is wet-etched to form one continuous recess under the first and second openings of the resist.
- a cross-linking reaction of the shrink material with the resist is performed, and the resist is putter-shrinked so that the wide first opening is not closed and the narrow second opening is completely closed.
- a gate electrode is formed in the recess in the formation region of the first opening.
- FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.
- FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.
- FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.
- FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.
- FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a comparative example.
- FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a comparative example.
- FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a comparative example.
- FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a comparative example.
- FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device
- FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a comparative example.
- FIG. 13 is a plan view showing a first opening and a second opening of the resist according to the second embodiment.
- FIG. 12 is a cross-sectional view along I-II in FIG. 9.
- FIG. 3 is a plan view showing a first opening and a second opening of the resist according to the first embodiment.
- FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment.
- FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment.
- FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment.
- FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment.
- FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment.
- FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.
- FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.
- FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.
- FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.
- FIG. 1 to 4 are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment.
- a source electrode 2 and a drain electrode 3 are formed on a semiconductor substrate 1.
- the semiconductor substrate 1 is made of GaAs or the like.
- the source electrode 2 and the drain electrode 3 are made of Ti / Pt / Au or the like.
- a resist 4 is applied on the semiconductor substrate 1, the source electrode 2, and the drain electrode 3.
- the resist 4 is, for example, Sumitomo Chemical's Sumiresist.
- a first opening 5 and a second opening 6 narrower than the first opening 5 are formed in the resist 4 by photolithography or the like.
- the first opening 5 is formed on the source electrode 2 side
- the second opening 6 is formed on the drain electrode 3 side.
- the width of the first opening 5 is 0.2 to 0.6 ⁇ m.
- the width of the second opening 6 is 0.1 to 0.5 ⁇ m.
- the distance between the first opening 5 and the second opening 6 is 0.1 to 0.2 ⁇ m.
- the semiconductor substrate 1 is dipped in phosphoric acid or citric acid for several seconds to several minutes and wet-etched to form one continuous recess 7 under the first opening 5 and the second opening 6. I do.
- the recess 7 is formed not only below the first opening 5 and the second opening 6 but also below the resist 4 therebetween, and is continuous.
- a shrink material 8 is applied to the resist 4.
- the shrink material 8 is RELACS or the like manufactured by AZ Electronic Materials.
- the resist 4 is putter-shrinked by heating the shrink material 8 to an appropriate temperature to cause a crosslinking reaction with the resist 4. Thereby, the wide first opening 5 is not closed, and the narrow second opening 6 is completely closed.
- a metal film 9 is formed on the entire surface by sputtering or vacuum evaporation.
- the metal film 9 is formed not only on the upper surfaces of the resist 4 and the shrink material 8 but also reaches the bottom surface of the recess 7 through the first opening 5.
- a resist 10 is formed on the metal film 9.
- the resist 10 is left over the first opening 5 with a wider width than the first opening 5 by photolithography or the like, and the other resist 10 is removed.
- the metal film 9 is patterned by dry etching using the resist 10 as a mask. After that, the resists 4 and 10 and the shrink material 8 are removed. As a result, as shown in FIG.
- a T-shaped gate electrode 11 is formed in the recess 7 in the portion where the first opening 5 is formed. Dry etching is, for example, ion milling using Ar gas or the like for several seconds to several tens of minutes. Note that the gate electrode 11 may be formed by a lift-off process.
- FIG. 5 to 8 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a comparative example.
- the semiconductor substrate 1 is wet-etched using the resist 12 as a mask to form a recess 7 below the opening 13.
- the resist 12 is removed.
- a resist 14 is formed on the entire surface, and an opening 15 is formed in the resist 14 in the recess 7.
- the gate electrode 11 is formed in the recess 7 at the portion where the opening 15 is formed. After that, the resist 14 is removed.
- the semiconductor substrate 1 is wet-etched to form one continuous recess 7 below the first opening 5 and the second opening 6 of the resist 4.
- the shrink material 8 is cross-linked with the resist 4 to cause a putter shrink of the resist 4 so that the first opening 5 having a large width is not closed and the second opening 6 having a small width is completely closed.
- a gate electrode 11 is formed in the recess 7 in a region where the first opening 5 is formed.
- the position of the gate electrode 11 in the recess 7 does not vary, so that the product yield is improved.
- the number of steps for patterning the resist is reduced, and the manufacturing cost can be reduced.
- the semiconductor directly under the gate electrode 11 is not damaged, so that the reliability is improved.
- the first opening 5 is formed on the source electrode 2 side, and the second opening 6 is formed on the drain electrode 3 side.
- FIG. 9 is a plan view showing a first opening and a second opening of the resist according to the second embodiment.
- FIG. 10 is a sectional view taken along the line I-II in FIG.
- the second opening 6 has a plurality of openings 6a, 6b, 6c spaced apart from each other. There are portions 4a, 4b that do not open between the plurality of openings 6a, 6b, 6c.
- FIG. 11 is a plan view showing a first opening and a second opening of the resist according to the first embodiment.
- the second opening 6 is one elongated opening. For this reason, if the distance between the first opening 5 and the second opening 6 is small, the resist 4 between them may collapse.
- the resist 4 can be reinforced because there are portions 4a and 4b which do not open between the plurality of openings 6a, 6b and 6c. As a result, a stable pattern can be formed, and the yield of products is improved.
- Other configurations and effects are the same as those of the first embodiment.
- FIG. 12 to 15 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the third embodiment.
- the steps from the formation of the recess 7 to the crosslinking reaction of the shrink material 8 with the resist 4 are the same as in the first embodiment.
- a thin Pt film 16 is formed on the bottom surface of the recess 7 through the first opening 5 by sputtering or vapor deposition.
- the opening width of the first opening 5 is slightly widened by ashing.
- a metal film 9 reaching the bottom surface of the recess 7 through the first opening 5 having an increased opening width is formed by sputtering or vapor deposition.
- the metal film 9 is patterned by dry etching using the resist 10 as a mask.
- the metal film 9 is made of a metal different from the Pt film 16. After that, the resist 4 and the shrink material 8 are removed.
- the semiconductor substrate 1 and the Pt film 16 are reacted by heat treatment, so that the Pt film 16 sinks into the semiconductor substrate 1.
- the gate electrode 11 has a Pt film 16 sunk into the semiconductor substrate 1 and a metal film 9 made of a metal different from the Pt film 16 and having a wider width than the Pt film 16 and overlapping the Pt film 16.
- the metal film 9 is formed through the first opening 5 whose opening width has been increased by ashing, and the Pt film 16 is formed on the semiconductor substrate 1 by heat treatment. Submerge. Thereby, the gate electrode 11 having a stepped lower end can be easily formed.
- FIG. 16 and 19 are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.
- the steps up to the formation of the recess 7 are the same as in the first embodiment.
- a pattern shrink is performed until the shrink material 8 reaches the bottom surface of the recess 7 by causing a crosslinking reaction of the shrink material 8 with the resist 4.
- the bottom of the recess 7 is etched using the resist 4 and the shrink material 8 as a mask to form a first concave portion 17a below the first opening 5 and a second concave portion 17a.
- a second recess 17b is formed below the opening 6.
- the shrink material 8 since the shrink material 8 has reached the bottom surface of the recess 7, only the first opening 5 and the second opening 6 are etched. Since the etching rate depends on the opening dimension of the pattern, the depth of the first concave portion 17a is deeper than the depth of the second concave portion 17b.
- a metal film 9 is formed on the entire surface by sputtering or vacuum evaporation.
- the metal film 9 is formed not only on the upper surfaces of the resist 4 and the shrink material 8 but also reaches the first concave portion 17a and the second concave portion 17b via the first opening 5 and the second opening 6, respectively.
- the metal film 9 is patterned by dry etching using the resist 12 as a mask. After that, the resists 4 and 10 and the shrink material 8 are removed.
- a T-shaped first gate electrode 11a is formed in the first recess 17a through the first opening 5, and the second recess is formed through the second opening 6.
- a T-shaped second gate electrode 11b is formed on 17b. Note that the first gate electrode 11a and the second gate electrode 11b may be formed by a lift-off process.
- the first gate electrode 11a formed in the first recess 17a and the second gate 17a formed in the second recess 17b have different threshold values. Therefore, transistors having different threshold voltages can be formed in the same recess. Since the positions of the first gate electrode 11a and the second gate electrode 11b in the recess 7 do not vary as in the first embodiment, the product yield is improved. Further, the number of steps for patterning the resist is reduced, and the manufacturing cost can be reduced.
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Abstract
Description
図1から図4は、実施の形態1に係る半導体装置の製造方法を示す断面図である。まず、図1に示すように、半導体基板1の上にソース電極2及びドレイン電極3を形成する。半導体基板1はGaAs等からなる。ソース電極2及びドレイン電極3はTi/Pt/Au等からなる。
図9は、実施の形態2に係るレジストの第1の開口と第2の開口を示す平面図である。図10は図9のI-IIに沿った断面図である。第2の開口6は互いに離間した複数の開口6a,6b,6cを有する。複数の開口6a,6b,6cの間に開口しない箇所4a,4bが存在する。
図12から図15は、実施の形態3に係る半導体装置の製造方法を示す断面図である。リセス7を形成し、シュリンク材8をレジスト4と架橋反応させるまでの工程は実施の形態1と同様である。次に、図12に示すように、第1の開口5を介してリセス7の底面に薄いPt膜16をスパッタ又は蒸着により形成する。次に、図13に示すように、アッシングで第1の開口5の開口幅を僅かに広げる。
図16及び図19は、実施の形態4に係る半導体装置の製造方法を示す断面図である。リセス7を形成するまでの工程は実施の形態1と同様である。次に、図16に示すように、シュリンク材8をレジスト4と架橋反応させてシュリンク材8がリセス7の底面に達するまでパターンシュリンクを行なう。
Claims (6)
- 半導体基板の上にレジストを塗布し、前記レジストに第1の開口と前記第1の開口より幅が細い第2の開口を形成する工程と、
前記レジストをマスクとして用いて前記半導体基板をウェットエッチングして前記第1及び第2の開口の下に連続した1つのリセスを形成する工程と、
前記リセスを形成した後、シュリンク材を前記レジストと架橋反応させて前記第1の開口を閉塞させずに前記第2の開口を閉塞させる工程と、
前記第2の開口を閉塞させた後、前記第1の開口を介して前記リセスにゲート電極を形成する工程とを備えることを特徴とする半導体装置の製造方法。 - 前記半導体基板の上にソース電極及びドレイン電極を形成する工程を更に備え、
前記第1の開口を前記ソース電極の側に形成し、前記第2の開口を前記ドレイン電極の側に形成することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記ゲート電極を形成した後に前記レジストと前記シュリンク材を除去する工程を更に備えることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記第2の開口は互いに離間した複数の開口を有することを特徴とする請求項1~3の何れか1項に記載の半導体装置の製造方法。
- 前記ゲート電極は、前記半導体基板に沈み込んだ金属薄膜と、前記金属薄膜とは異なる金属からなり前記金属薄膜よりも幅が広く前記金属薄膜の上にオーバーラップした金属膜とを有し、
前記ゲート電極の下端部が階段状になっていることを特徴とする請求項1~4の何れか1項に記載の半導体装置の製造方法。 - 前記第2の開口を閉塞させた後、前記第1の開口を介して前記リセスの底面に前記金属薄膜を形成する工程と、
前記金属薄膜を形成した後に、アッシングで前記第1の開口の開口幅を広げる工程と、
開口幅を広げた前記第1の開口を介して前記リセスの底面に達する前記金属膜を形成する工程と、
熱処理により前記半導体基板と前記金属薄膜を反応させて前記金属薄膜を前記半導体基板に沈み込ませる工程とを備えることを特徴とする請求項5に記載の半導体装置の製造方法。
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