JP6750455B2 - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 67
- 238000004519 manufacturing process Methods 0.000 title description 9
- 239000000758 substrate Substances 0.000 claims description 37
- 238000000231 atomic layer deposition Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 description 15
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 8
- 238000009832 plasma treatment Methods 0.000 description 8
- 230000008595 infiltration Effects 0.000 description 7
- 238000001764 infiltration Methods 0.000 description 7
- 239000010410 layer Substances 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 239000002356 single layer Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004140 HfO Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
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Description
図1は、本発明の実施の形態1に係る半導体装置を示す断面図である。この半導体装置は、MES−FET又はHEMTなどの電界効果トランジスタである。
図5は、本発明の実施の形態2に係る半導体装置を示す断面図である。本実施の形態では、半導体基板1及びゲート電極2等の上にTa2O5膜6をALD法により形成する。転写工程とエッチング工程によりTa2O5膜6の不要部分をエッチング除去する。半導体基板1にN2プラズマ処理を行った直後に半導体基板1及びTa2O5膜6の全面にSiN膜5をプラズマCVD法により形成する。SiN膜5は半導体基板1に直接的に接して両者の界面が形成されている。その他の構成は実施の形態1と同様である。
図6は、本発明の実施の形態3に係る半導体装置を示す平面図である。図7は図6のI−IIに沿った断面図である。本実施の形態では、転写工程とエッチング工程によりSiN膜5はTa2O5膜6の外周部のみ残して不要部分をエッチング除去する。ドライエッチングを用いることで、ゲート電極2上のTa2O5膜6を残しつつ、SiN膜5のみを選択的に除去することができる。その他の構成は実施の形態2と同様である。
図8は、本発明の実施の形態4に係る半導体装置を示す断面図である。実施の形態1〜3ではTa2O5などの酸化膜を用いたが、本実施の形態ではALD法により形成したSiN膜7だけを保護膜として用いる。
図9は、本発明の実施の形態5に係る半導体装置のゲート電極の周辺を示す断面図である。ゲート電極2は、TaO膜8,9の間にTaO膜8,9よりも誘電率が低いSiO膜10を挿入した積層膜で覆われている。これらの層はALD法により形成されている。また、ここでは3層構造の例を示すが、それ以上の多層膜としてもよい。その他の構成は実施の形態1〜3と同様である。
Claims (1)
- 半導体基板と、
前記半導体基板上に形成されたソース電極及びドレイン電極と、
前記ソース電極と前記ドレイン電極の間において前記半導体基板上に形成されたゲート電極と、
前記半導体基板及び前記ゲート電極上に形成されたSiN膜と、
前記SiN膜上に形成された酸化膜とを備え、
前記酸化膜は原子層が交互に積層された原子層堆積膜であり、第1及び第2のTaO膜の間に前記第1及び第2のTaO膜よりも誘電率が低い膜を挿入した積層膜であり、前記ソース電極及び前記ドレイン電極の前記ゲート電極に対向していない側面に隣接した部分でのみ前記半導体基板に直接形成されていることを特徴とする半導体装置。
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JP2016211651A JP6750455B2 (ja) | 2016-10-28 | 2016-10-28 | 半導体装置及びその製造方法 |
US15/660,996 US10388585B2 (en) | 2016-10-28 | 2017-07-27 | Semiconductor device and method of manufacturing the same |
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JP2018085414A (ja) * | 2016-11-22 | 2018-05-31 | 富士通株式会社 | 化合物半導体装置 |
US11387332B2 (en) * | 2018-06-27 | 2022-07-12 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |
JP7367440B2 (ja) * | 2019-10-04 | 2023-10-24 | 住友電気工業株式会社 | 高電子移動度トランジスタの製造方法及び高電子移動度トランジスタ |
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JPH05335345A (ja) | 1992-05-29 | 1993-12-17 | Sharp Corp | 半導体素子の表面保護膜 |
JPH0661271A (ja) * | 1992-08-11 | 1994-03-04 | Hitachi Ltd | 半導体集積回路装置 |
US6660660B2 (en) * | 2000-10-10 | 2003-12-09 | Asm International, Nv. | Methods for making a dielectric stack in an integrated circuit |
JP4620333B2 (ja) * | 2003-05-09 | 2011-01-26 | 三菱電機株式会社 | 半導体装置の製造方法 |
US20110180757A1 (en) * | 2009-12-08 | 2011-07-28 | Nemanja Vockic | Luminescent materials that emit light in the visible range or the near infrared range and methods of forming thereof |
US20090018920A1 (en) * | 2006-07-21 | 2009-01-15 | Videoegg, Inc. | Interaction Prompt for Interactive Advertising |
EP2065925B1 (en) * | 2006-09-20 | 2016-04-20 | Fujitsu Limited | Field-effect transistor |
US7767589B2 (en) * | 2007-02-07 | 2010-08-03 | Raytheon Company | Passivation layer for a circuit device and method of manufacture |
US20090014026A1 (en) * | 2007-07-10 | 2009-01-15 | Rory Powell Blake | Thin Film Interdental Cleaning Device with Flexible Folds |
JP5386829B2 (ja) * | 2008-01-30 | 2014-01-15 | 富士通株式会社 | 半導体装置 |
US8994073B2 (en) * | 2012-10-04 | 2015-03-31 | Cree, Inc. | Hydrogen mitigation schemes in the passivation of advanced devices |
US9082722B2 (en) * | 2013-03-25 | 2015-07-14 | Raytheon Company | Monolithic integrated circuit (MMIC) structure and method for forming such structure |
JP2015213100A (ja) * | 2014-05-01 | 2015-11-26 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US9478652B1 (en) * | 2015-04-10 | 2016-10-25 | Raytheon Company | Monolithic integrated circuit (MMIC) structure having composite etch stop layer and method for forming such structure |
JP2016103646A (ja) * | 2015-12-14 | 2016-06-02 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
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