WO2019184985A1 - 栅极驱动电路及其驱动方法、显示装置 - Google Patents

栅极驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2019184985A1
WO2019184985A1 PCT/CN2019/080118 CN2019080118W WO2019184985A1 WO 2019184985 A1 WO2019184985 A1 WO 2019184985A1 CN 2019080118 W CN2019080118 W CN 2019080118W WO 2019184985 A1 WO2019184985 A1 WO 2019184985A1
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Prior art keywords
data
output
decoder
scan
mode
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PCT/CN2019/080118
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English (en)
French (fr)
Inventor
陆政华
何宗泽
李硕
陈宇轩
陈秀云
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US16/646,760 priority Critical patent/US11087669B2/en
Publication of WO2019184985A1 publication Critical patent/WO2019184985A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • Embodiments of the present disclosure relate to a gate driving circuit, a driving method thereof, and a display device.
  • the array substrate typically includes a plurality of rows of gate lines and a plurality of columns of data lines that intersect each other.
  • the driving of the gate lines can be realized by an attached integrated driving circuit.
  • the gate drive circuit can be directly integrated on the thin film transistor array substrate to form a gate driver integrated GOA (Gate driver On Array) on the array substrate to drive the gate line. .
  • GOA Gate driver On Array
  • the GOA technology can not only save the circuit board carrying the gate driving chip, realize the symmetrical design of the display panel, but also eliminate the chip bonding area and the wiring area at the edge of the display panel (for example, Fan-out area), which facilitates the realization of a narrow bezel design.
  • At least embodiments of the present disclosure provide a gate drive circuit including: a plurality of scan outputs and a decoder circuit.
  • the decoder circuit includes a plurality of input terminals and a plurality of output terminals, a plurality of output ends of the decoder circuit are in one-to-one correspondence with the plurality of scan output terminals; and a plurality of inputs of the decoder circuit The end is configured to receive parallel data frames; the decoder circuit is configured to output at an output of the decoder circuit corresponding to the parallel data frame upon receiving the parallel data frame A trigger signal for generating a scan signal to cause the scan signal to be output at a scan output corresponding to the parallel data frame.
  • the gate driving circuit further includes: a serial to parallel conversion circuit and a latch circuit connected to the serial to parallel conversion circuit.
  • the serial to parallel conversion circuit is configured to receive a serial data frame and convert the serial data frame into the parallel data frame;
  • the latch circuit is configured to receive and store the parallel data frame And outputting the parallel data frame when the data frame reception is completed;
  • the decoder circuit is coupled to the latch circuit to receive the parallel data frame output by the latch circuit The decoder circuit is configured to output the data for outputting the data frame output by the latch circuit at an output of the decoder circuit corresponding to the parallel data frame Generating a trigger signal for the scan signal.
  • the decoder circuit includes an address decoder, the parallel data frame includes parallel address data; the address decoder includes a plurality of inputs And a plurality of outputs; each of the plurality of inputs of the address decoder being configured to receive one of the parallel address data; the address decoder being configured to receive the parallel After the address data, the trigger signal for generating the scan signal is output via an output of the address decoder corresponding to the parallel address data.
  • the address decoder is a mn decoder; and the m is equal to the number of inputs of the address decoder, the n being equal to the The number of outputs of the address decoder.
  • the m-n decoder includes at least one two-four decoder.
  • the decoder circuit further includes a mode decoder;
  • the parallel data frame further includes parallel mode data, the parallel mode data and the Parallel address data are juxtaposed to each other in the parallel data frame;
  • the mode decoder is configured to cause all outputs of the decoder when the parallel mode data corresponds to a full-off mode The trigger signal for generating the scan signal is not output or the trigger signal for generating the scan signal is output.
  • the mode decoder includes a full-off decoder; the full-close decoder is configured to correspond to a full-off mode in the parallel mode data At the time, an enable signal is provided to the enable terminal of the address decoder such that none of the outputs of the decoder output the trigger signal for generating the scan signal.
  • the full-close decoder includes a first AND gate; the parallel mode data includes first bit data and second bit data; a first input of the gate is configured to receive data inverted from the first bit of data; a second input of the first AND gate is configured to receive the second bit of data; the first AND gate The output is configured to be coupled to the enable of the address decoder.
  • the mode decoder includes a fully open decoder; the fully open decoder is configured to correspond to a full open mode in the parallel mode data At the time, all of the output outputs of the decoder are caused to output the trigger signal for generating the scan signal.
  • the fully open decoder includes a second AND gate and a plurality of OR gates;
  • the parallel mode data includes first bit data and second bit data; a first input of the second AND gate is configured to receive the first bit data; a second input of the second AND gate is configured to receive the second bit data; the second AND gate An output is configured to be coupled to a first input of each of the plurality of OR gates; a second input of the plurality of OR gates and a plurality of outputs of the address decoder, respectively Connected.
  • the gate drive circuit further includes a level shift circuit.
  • the level shifting circuit is configured to receive the trigger signal for generating a scan signal, convert the trigger signal for generating a scan signal into the scan signal, and cause the scan signal to be in parallel with the scan signal
  • the data frame corresponds to the output of the scan output.
  • the gate drive circuit further includes a serial data interface.
  • the serial to parallel conversion circuit is coupled to the serial data interface to receive the serial data frame via the serial data interface.
  • the serial data interface includes a serial data line and a serial clock signal line; the serial data line and the serial clock signal line are both The serial to parallel conversion circuit is connected; the serial to parallel conversion circuit is configured to read one bit of data on the serial data line each time an electrical signal on the serial clock signal line satisfies a trigger condition.
  • the serial to parallel conversion circuit includes at least two stages of flip-flops; the trigger input ends of the at least two stages of flip-flops are all connected to the serial clock signal line, Each stage of the flip-flop outputs one bit of data of the parallel data frame; and an input end of the flip-flop of the first stage is connected to the serial data line, and the trigger is triggered at any level other than the first stage
  • the input of the device is connected to the output of the flip-flop of the previous stage.
  • each of the at least two stages of flip flops is a D flip flop.
  • the serial data interface further includes a receive enable signal line electrically coupled to the latch circuit, the latch circuit for The parallel data frames are output when the electrical signal on the receive enable signal line transitions from the active level to the inactive level.
  • the latch circuit includes at least two edge flip flops; a trigger input terminal of the at least two edge flip flops and the receive enable signal line Electrically connected, an input of each of the edge triggers receives one bit of data of the parallel data frame, and an output of each of the edge triggers outputs one bit of data of the parallel data frame.
  • each of the at least two edge flip flops is a D flip flop.
  • an inverter is further included, the inverter includes an input end and an output end; an input end of the inverter is connected to the receiving enable signal line Receiving an electrical signal on the receive enable signal line; the inverter being configured to invert an electrical signal on the received receive enable signal line from an output of the inverter An output; and an output of the inverter is coupled to a trigger input of each of the at least two edge flip flops.
  • the serial data interface is a serial bus interface of a serial peripheral interface SPI
  • the data frame includes address data and mode data
  • the decoder circuit It includes an address decoder, a mode decoder and several level shifters.
  • the address decoder uses a 24th decoder as a minimum constituent unit for receiving address data in the data frame when receiving the address data in the data frame output by the latch circuit.
  • Corresponding level shifters output trigger signals; each of said level shifters is coupled to one of said scan outputs for use in receiving said trigger signal output by said address decoder Outputting the scan signal at a scan output of each of the level shifter connections;
  • the mode decoder is configured to receive the mode data in a data frame output by the latch circuit and When the mode of operation corresponding to the mode data is the full-on mode, the plurality of scan outputs output a gate active level voltage, so that the plurality of scan outputs output the scan signal; and the mode a decoder, configured to: when the mode data in the data frame output by the latch circuit is received and the mode of operation corresponding to the mode data is a full-off mode, causing the plurality of scan outputs to output Invalid level voltage electrode, such that said plurality of scan output the scan signals are not output.
  • the data frame includes address data; and the decoder circuit is configured to output at the decoder circuit corresponding to the address data
  • the trigger signal for generating the scan signal is output at the end.
  • the data frame further includes mode data; the decoder circuit is configured to, when receiving the parallel data frame, according to the data frame The mode data determines a current mode of operation, the current mode of operation including a general mode; and when the current mode of operation is a normal mode, the decoder circuit is configured to be at the decoder circuit
  • the trigger signal for generating the scan signal is output at an output end corresponding to the address data in the data frame.
  • the current operating mode further includes a full-on mode; and when the current operating mode is the fully-on mode, the decoder circuit is configured The gate active level voltage is simultaneously outputted at the plurality of scan outputs such that the scan signals are output by the plurality of scan outputs.
  • the current mode of operation further includes a full off mode; and when the current mode of operation is a fully off mode, the decoder circuit is configured to The gate inactive level voltage is simultaneously outputted at the plurality of scan outputs such that the scan signals are not output by the plurality of scan outputs.
  • At least one embodiment of the present disclosure also provides a display device including the gate driving circuit provided by any one of the embodiments of the present disclosure.
  • the display device further includes a controller.
  • the controller is configured to receive a display image, obtain a difference between the display image and a previous frame display image, and generate at least one data frame based on the difference.
  • the controller is further configured to cause each of the at least one data frame to be a serial data frame.
  • At least another embodiment of the present disclosure further provides a driving method for driving a gate driving circuit provided by any one of the embodiments of the present disclosure.
  • the driving method includes: when receiving the display data of the first frame, sequentially transmitting a data frame including address data of each of the scan output ends to the gate driving circuit; and receiving the first frame
  • the refresh scan output is determined by comparing the display data of the current frame with the display data of the previous frame, and will be included at the time corresponding to each of the refresh scan outputs, respectively.
  • refreshing, by the refresh scan output end refreshing the display screen corresponding to the display data of the previous frame to the display of the current frame, and transmitting the data frame of the address data of the scan output to the gate drive circuit.
  • a scan output end of the scan signal is required to be outputted from the plurality of scan outputs.
  • FIG. 1 is a block diagram showing an exemplary structure of a gate driving circuit provided by some embodiments of the present disclosure
  • FIG. 2 is a circuit configuration diagram of a gate driving circuit provided by some embodiments of the present disclosure
  • FIG. 3 is a circuit timing diagram of a gate drive circuit provided by some embodiments of the present disclosure.
  • FIG. 4 is an exemplary structural block diagram of a portion of an address decoder in a gate drive circuit provided by some embodiments of the present disclosure
  • FIG. 5 is a circuit structural diagram of a two-four decoder according to some embodiments of the present disclosure.
  • FIG. 6 is a schematic flow chart of a driving method of a gate driving circuit in some embodiments of the present disclosure
  • FIG. 7 is a diagram showing a data transmission state change of a serial data interface in some embodiments of the present disclosure.
  • FIG. 8 is an exemplary block diagram of a display device provided by some embodiments of the present disclosure.
  • the gate drive circuit (GOA) circuit in the related design can only realize row-by-row opening of all pixel rows (or specific partial pixel rows) of the array substrate to realize progressive data refresh. It is not possible to open only the pixels of the specified line, and thus it is not possible to flexibly select the pixel row for data refresh.
  • the gate drive circuit includes a plurality of scan outputs and a decoder circuit.
  • the decoder circuit includes a plurality of inputs and a plurality of outputs, and the plurality of outputs of the decoder circuit are in one-to-one correspondence with the plurality of scan outputs; the plurality of inputs of the decoder circuit are configured to receive the parallel data a decoder circuit configured to output a trigger signal for generating a scan signal at an output of the decoder circuit corresponding to the parallel data frame when the parallel data frame is received, so as to be parallel with the data frame A scan signal is output at the corresponding scan output.
  • the gate driving circuit when the gate driving circuit receives a data frame, one of the plurality of scan output terminals of the gate driving circuit outputs a scan signal (a valid signal), and thus, the gate The pole drive circuit can provide a valid signal to one (single) gate line and can only open a row of pixels connected to one (single) gate line of the above, whereby some examples of the present disclosure provide a gate
  • the pole drive circuit can implement partial scanning of the array substrate (or display panel). For example, when the gate driving circuit is used to refresh a frame display screen of the display panel, the gate driving circuit can receive only a few (for example, 3 or 10) data frames.
  • the gate driving circuit only needs to Providing valid signals to several gate lines (for example, 3 or 10) of the display panel to perform data refresh for several rows of display pixels (for example, 3 rows or 10 rows) of the display panel, thereby avoiding row-by-row opening
  • the display pixels of the display panel can further reduce the power consumption of the display panel and the display device using the gate driving circuit, and improve the refresh speed, endurance and user experience of the display panel and the display device using the gate driving circuit.
  • the gate drive circuit can also include a serial to parallel conversion circuit and a latch circuit.
  • the gate drive circuit can be connected to a serial data interface and can receive data frames originating from a system side (eg, a controller) via a serial data interface, thereby reducing The number of buses (and/or the number of circuit interfaces) of the gate drive circuit improves the versatility of the gate drive circuit.
  • the gate drive circuit may not be provided with a serial-to-parallel conversion circuit and a latch circuit without considering the number of bus lines (or the number of circuit interfaces) and versatility of the gate driving circuit.
  • the gate electrode The driver circuit can receive the parallel data frames via the parallel data interface and provide the parallel data frames to the decoder, the decoder can be based on the parallel data frames, at the scan output corresponding to the parallel data frames The scan signal is output.
  • the gate drive circuit may not be provided with a serial data interface.
  • the decoder may include a mode decoder by which the gate drive circuit may (simultaneously) align the array substrate (or display) via a plurality of scan outputs G1, G2, . . . , Gn All of the gate lines of the panel) provide an invalid signal or a valid signal, whereby all display pixels of the array substrate (or display panel) can be turned off or on (eg, simultaneously turned off or on). It should be noted that, in the case that it is not necessary to provide an invalid signal or a valid signal to all the gate lines of the array substrate (or the display panel), the decoder may not include the mode decoder. In this case, The decoder may only include an address decoder.
  • the related functions of the gate driving circuit can be implemented by gate circuits and transistors, and the gate circuit can be implemented by a combination of transistors and capacitors that can be fabricated on the array substrate (also can be implemented by a field programmable gate array FPGA).
  • the implementation of the gate driving circuit in some examples of the present disclosure may be based on the fabrication process of the array substrate. In this case, the array substrate and the display panel using the gate driving circuit in some examples of the present disclosure need not be pasted. A chip or an external circuit is attached, whereby the fabrication cost of the array substrate and the display panel using the gate driving circuit in some examples of the present disclosure can be reduced.
  • the gate driving circuit is not required to be implemented as a GOA, part of the functions of the gate driving circuit may be implemented by circuits other than the gate circuit to further improve the performance of the gate driving circuit.
  • the scan output output scan signal refers to the scan output output valid signal, and the scan output output scan signal does not mean that the scan output outputs an invalid signal.
  • an effective signal refers to a signal for turning on a switching element of an associated display pixel electrically connected to the gate driving circuit
  • an invalid signal refers to the signal used to turn off the associated display pixels electrically connected to the gate drive circuit
  • the gate driving circuit provided by the embodiment of the present disclosure will be described below by way of a few examples. As described below, different features in these specific examples may be combined with each other without conflicting with each other, thereby obtaining a new one. By way of example, these new examples are also within the scope of the present disclosure.
  • the gate driving circuit includes: a plurality of scanning output terminals G1, G2, ..., Gn; a serial data interface 11; a serial to parallel conversion circuit 12 connected to the serial data interface 11, and a serial to parallel conversion circuit 12 Connected latch circuits 13, respectively, are coupled to the latch circuit 13 and the decoder circuit 14 connected to each of the scan outputs.
  • the serial to parallel conversion circuit 12 is configured to receive serial data frames through the serial data interface 11 and convert the serial data frames into parallel data frames;
  • the latch circuit 13 is configured to receive and store parallel data frames, and The parallel data frame is output when the data frame reception is completed;
  • the decoder circuit 14 is connected to the latch circuit 13 to receive the parallel data frame output by the latch circuit 13, and the decoder circuit 14 For outputting a parallel data frame output by the latch circuit 13, outputting a trigger signal for generating a scan signal at an output of the decoder circuit 14 corresponding to the parallel data frame, such that The scan signal is output at the scan output corresponding to the data frame.
  • the latch circuit 13 is configured to store and output the parallel data frames corresponding to any one of the data frames described above after the reception of any of the data frames is completed.
  • some embodiments of the present disclosure are capable of passing serial data based on serial data interfaces and serial to parallel conversion circuits, latch circuits, and decoder circuits each capable of being implemented in the form of logic circuits on an array substrate
  • the interface receives the data frame and selects the corresponding scan output end to output the scan signal according to the data frame. Therefore, the gate drive circuit formed on the array substrate can be configured to have the function of flexibly selecting the pixel row for data refresh.
  • serial communication can also be used to reduce the number of circuit interfaces, which helps to simplify the internal structure of related products and improve the versatility and endurance of related products.
  • n is a positive integer
  • the serial data interface 11 includes a serial data line SD, a serial clock signal line SCLK, and a reception enable signal line SCS (for example, for providing an enable signal).
  • the serial data interface 11 may be a serial bus interface of the serial peripheral interface SPI, and the serial bus interface transmits data according to a serial communication protocol corresponding to the serial peripheral interface SPI.
  • the gate drive circuit includes 256 scan output terminals G1, G2, ..., G255, G256.
  • the structure of the data frame received by the gate driving circuit may be as shown in the signal timing on the serial data line SD in FIG. 3, that is, the data frame received by the gate driving circuit may include 16-bit binary data, here, Two binary data bits of M1 and M0 are used to carry mode data; eight binary data bits of A0, A1, A2, A3, A4, A5, A6, A7 are used to carry address data; PC is parity for parity check.
  • Check digit (for example, whether the number of "1"s in the data frame is odd or even to verify whether a transmission error occurs); a total of five binary data bits of A8, A9 and three DMY are temporarily unused data bits, for example
  • the address data may be carried by the above-mentioned temporarily unused data bits (for example, two additional data is used) when the number of scan outputs is increased (for example, 1024).
  • the parity bit can also be used to carry address data without considering the transmission error.
  • the serial-to-parallel conversion circuit 12 includes ten upper-edge D flip-flops, and ten upper-edge D flip-flops are connected in stages to form a shift register circuit, so that the serial data line SD, as shown in FIG. 3, can be matched.
  • the signal on the serial clock signal line SCLK enables reception of serial data frames and serial-to-parallel conversion.
  • the input of the upper edge D flip-flop of the first stage (the end marked with "D" in FIG. 2) is connected to the serial data line SD, and the input of the upper edge D flip-flop at any level other than the first stage.
  • the end is connected to the output of the upper edge D flip-flop (the end marked with "Q” in Figure 2), and the trigger input of the 10 upper edge D flip-flops (the end marked by the triangle in Figure 2)
  • the serial clock signal line SCLK is connected such that each rising edge of the serial clock signal line SCLK triggers a shift operation - every time a rising edge occurs on the serial clock signal line SCLK, 10 upper edge D flip-flops Each of them sets the level at the output to the same level as the input, thereby completing a shift operation at the output of the 10 upper edge D flip-flops, such as the first to eighth stages.
  • the output of the upper edge D flip-flop is "1011100000" before the rising edge of the serial clock signal line SCLK, and the level on the serial data line SD when the rising edge on the serial clock signal line SCLK arrives. “0” will replace the output of the first-stage upper edge D flip-flop Level, at the same time the level at the output of the upper edge of the D flip-flop of each stage replaces the level at the output of the upper edge of the next stage D flip-flop, the output of the output of the last stage of the upper edge D flip-flop The flat will disappear and become "0101110000", that is, all data bits are shifted to the right by one. It should be understood that the serial-to-parallel conversion circuit 12 includes ten upper edge D flip-flops.
  • A0, A1, A2, A3, A4, A5, A6, A7, M0, M1 are also used to describe and show the respective outputs included in the latch circuit 13.
  • the above-described serial-to-parallel conversion circuit 12 function can be implemented by at least n-level D flip-flops.
  • the trigger input terminals of the n-level D flip-flops are connected to the serial clock signal line, and the input end of the first-stage D flip-flop is connected to the serial data line, and any level D trigger other than the first stage
  • the input end of the device is connected to the output terminal of the upper stage D flip-flop, so that the construction of the above shift register circuit can be realized.
  • the upper edge can be used as the electrical signal (that is, the clock signal) on the serial clock signal line
  • the lower edge, the high level, or the low level can be used as the trigger condition.
  • the trigger condition of the electrical signal on the serial clock signal line may not be limited to the examples listed above. It can be seen that the serial-to-parallel conversion circuit can read one bit of data on the serial data line each time the electrical signal on the serial clock signal line satisfies the trigger condition; of course, other serial signals can be converted into The circuit structure of the function of the parallel signal implements the serial to parallel conversion circuit of the embodiment of the present disclosure.
  • the latch circuit 13 includes a plurality of upper edge D flip-flops, and the number of upper edge D flip-flops included in the latch circuit 13 is equal to the number of upper edge D flip-flops included in the serial to parallel conversion circuit 12, latched
  • the input of the plurality of upper edge D flip-flops included in the circuit 13 is respectively coupled to a plurality of upper edge D flip-flops included in the serial to parallel conversion circuit 12 to respectively receive and store one bit of data of the parallel data frame.
  • the latch circuit 13 includes ten upper edge D flip-flops, and the trigger inputs of the ten upper edge D flip-flops Both are connected to the receive enable signal line SCS via an inverter, so that the 10 upper edge D flip-flops will trigger the latch circuit 13 to include a plurality of upper edges D under the trigger of the falling edge of the receive enable signal line SCS.
  • the level at the output of the device is set to the same level as the level at the input, that is, each bit of binary data is output.
  • the latch circuit 13 can output the parallel data frames from the serial to parallel conversion circuit 12 when the active level is changed to the inactive level on the reception enable signal line SCS.
  • the active level and the inactive level in some embodiments of the present disclosure refer to two different pre-configured voltage ranges (both based on the common terminal voltage) for a particular circuit node, respectively.
  • the active levels of all circuit nodes are high.
  • the active levels of all circuit nodes are low.
  • the active level means that data frame transmission is or will be in progress
  • the active level transition to the inactive level means that the transmission of one data frame ends.
  • the above latch circuit 13 functions can be implemented by at least n edge D flip-flops.
  • the trigger inputs of the at least n edge D flip-flops are all connected to the receive enable signal line (and may pass through one or more inverters), and the input of each of the edge D flip-flops receives One bit of data of the parallel data frame, the output of each of the edge D flip-flops outputs one bit of data of the parallel data frame.
  • the above latch circuit 13 functions can also be implemented using 10 lower edge D flip-flops using the removal of the settings of the inverter of FIG.
  • serial-to-parallel conversion circuit 12 and the latch circuit 13 are not limited to include D flip-flops, and the serial-to-parallel conversion circuit 12 and the latch circuit 13 may also adopt other suitable flip-flops according to actual application requirements.
  • the decoder circuit includes an address decoder, the parallel data frames include parallel address data; the address decoder includes a plurality of inputs and a plurality of outputs; each of the plurality of inputs of the address decoder is configured To receive one bit of the parallel address data; the address decoder is configured to output, after receiving the parallel address data, an output output corresponding to the parallel address data via the address decoder for generating a scan signal Trigger signal.
  • the address decoder is an m-n decoder (e.g., an 8-input 256-output decoder); m is equal to the number of inputs to the address decoder, and n is equal to the number of outputs of the address decoder.
  • the m-n decoder includes at least one two-four decoder.
  • the decoder circuit further includes a mode decoder; the parallel data frames include parallel mode data, the parallel mode data and the parallel address data are juxtaposed to each other in parallel data frames; the mode decoder is configured to be in parallel
  • the mode data corresponds to the full-off mode such that all of the outputs of the decoder do not output a trigger signal for generating a scan signal or a trigger signal for generating a scan signal.
  • the mode decoder includes a full-close decoder; the full-close decoder is configured to provide an invalid signal to the enable end of the address decoder when the parallel mode data corresponds to the fully-off mode, such that decoding The trigger signal for generating the scan signal is not output at all outputs of the device.
  • the omni-directional decoder includes a first AND gate (eg, an AND gate located above the mode decoder 142 in FIG. 2); the parallel mode data includes first bit data (eg, M0) and second bit data (eg, M1); the first input of the first AND gate is configured to receive data inverted from the first bit data; the second input of the first AND gate is configured to receive the second bit data; The output of the gate is configured to be coupled to the enable of the address decoder.
  • a first AND gate eg, an AND gate located above the mode decoder 142 in FIG. 2
  • the parallel mode data includes first bit data (eg, M0) and second bit data (eg, M1); the first input of the first AND gate is configured to receive data inverted from the first bit data; the second input of the first AND gate is configured to receive the second bit data;
  • the output of the gate is configured to be coupled to the enable of the address decoder.
  • the mode decoder includes a fully open decoder; the fully open decoder is configured to cause all of the decoder when the parallel mode data corresponds to the fully open mode
  • the output of the output outputs a trigger signal for generating a scan signal.
  • the fully open decoder includes a second AND gate (eg, an AND gate located below the mode decoder 142 in FIG. 2) and a plurality of OR gates (eg, a map) 2 or more gates included in the level shifter 143;
  • the parallel mode data includes first bit data and second bit data;
  • the first input of the second AND gate is configured to receive the first bit data;
  • a second input of the AND gate is configured to receive second bit data;
  • an output of the second AND gate is configured to be coupled to a first input of each of the plurality of OR gates; a second of the plurality of OR gates
  • the inputs are respectively connected to a plurality of outputs of the address decoder.
  • the gate drive circuit further includes a plurality of level shift circuits (not shown in FIG. 2).
  • Each of the plurality of level shifting circuits is configured to receive a trigger signal for generating a scan signal, convert a trigger signal for generating the scan signal into a scan signal, and cause the scan signal to pass through a scan output corresponding to the parallel data frame End output.
  • the absolute value of the level of the trigger signal is about 0.1-0.6 volts, for example, the absolute value of the level of the scan signal is about 10-16 volts.
  • each of the plurality of level shifting circuits may be implemented as a transistor (eg, a complementary metal oxide semiconductor transistor).
  • the decoder circuit 14 and the level shifting circuit are exemplarily described below with the example shown in FIG. 2.
  • the decoder circuit 14 includes an address decoder 141, a mode decoder 142, and a number of level shifters 143.
  • the address decoder 141 in the embodiment shown in FIG. 2 is specifically a decoder with 8 input 256 outputs, that is, 256 outputs according to the 8-bit binary data of the input terminals S1, S2, ..., S7, S8.
  • An effective level is output at an output corresponding to the binary data among the terminals D1, D2, D3, D4, ..., D253, D254, D255, and D256.
  • the address data corresponds to the identifier of the scan output end that needs to output the scan signal between several scan output ends, for example, the decimal number of the binary data "01011100” is "92", so the address decoder 141 can be input.
  • the parallel address data is "01011100”
  • the active level is output at the 92nd output terminal D92 so that the connected level shifter 143 receives the active level at the connected 256 scan outputs.
  • the 92nd scan output of the output scan signal It can be seen that the function of the address decoder 141 is mainly to output a trigger signal to the level shifter 143 corresponding to the address data in the data frame upon receiving the address data in the data frame output from the latch circuit 13. (such as the above effective level).
  • the corresponding address decoder should include n inputs and 2 n outputs.
  • the mode decoder 142 shown in Fig. 2 employs the operation mode control shown in the following table.
  • the mode decoder 142 includes two AND gates (for example, two AND gates arranged side by side in the vertical direction), wherein an input terminal of the upper AND gate (for example, An input terminal) is connected to the inverted output of the upper edge D flip-flop corresponding to M0 in the latch circuit 13 (in FIG.
  • the other input of the upper AND gate (for example, the second input) is connected to the output of the upper edge D flip-flop corresponding to M1 in the latch circuit 13, so when M1 is 1, and M0 is 0
  • the AND gate outputs a high level, so that the low-level active enable terminal ENB of the address decoder 141 connected to the output of the AND gate will become a high level, at which time the address decoder 141 will not Work, no matter what input data input terminal is all inactive level, so all scan output terminals do not output scan signals, which can achieve full gate control of the gate driver through mode data with M1 and M0 being 0.
  • the mode decoder 142 includes two input terminals (for example, the first input terminal) of the AND gate below the gate, and is connected to the latch circuit 13 corresponding to M0.
  • the output of the upper edge D flip-flop, the other input of the lower AND gate (for example, the second input) is connected to the output of the upper edge D flip-flop corresponding to M1 in the latch circuit 13, so when M1 is 1.
  • M0 is also 1, the AND gate outputs a high level.
  • each level shifter 143 includes, for example, a level shifting circuit (not shown), the input of the level shifting circuit is connected to the output of the OR gate, so that regardless of the state of the output of the address decoder 141, all the scan outputs are The OR gate is set high. Thereby, the full-open control function of the gate driver can be realized by mode data in which M1 is 1 and M0 is 1.
  • the high level at the output of the level shifter 143 can be, for example, a gate high level voltage VGH (eg, a scan signal), and the low level at the output of the level shifter 143 can be, for example It is the gate low level voltage VGL, which can realize the function of outputting the scan signal at the connected scan output terminal upon receiving the trigger signal output from the address decoder 141.
  • the voltage value of the gate high level voltage VGH is larger than the voltage value of the gate low level voltage VGL.
  • the gate high level voltage VGH has an absolute value of 10-16 volts and the gate low level voltage VGL is zero volts.
  • the absolute values of the gate high level voltage VGH and the gate low level voltage VGL are both 10-16 volts, and the gate low level voltage VGL is a negative value.
  • the process performed by the decoder circuit 14 in the above example is equivalent to determining the current operating mode based on the mode data in the data frame, thereby corresponding to the address data in the data frame when the current operating mode is the normal mode.
  • the scan output signal is outputted at the scan output end, and the gate active level voltage is simultaneously outputted at several scan output ends when the current working mode is the full open mode, and the scan output is in several scan outputs when the current working mode is the full off mode.
  • the gate inactive level voltage is simultaneously output at the terminal.
  • the mode decoder 14 is configured to receive the mode data in the data frame output by the latch circuit 13 and the mode corresponding to the mode data is in the full-on mode, A plurality of scan outputs are turned on to a gate active level voltage (eg, such that a plurality of scan outputs output a gate active level voltage); and/or mode decoder 14 is configured to receive a latch
  • a gate active level voltage eg, such that a plurality of scan outputs output a gate active level voltage
  • mode decoder 14 is configured to receive a latch
  • a plurality of scan outputs are turned on to the gate inactive level voltage (for example, so that several scan outputs are output) Gate inactive level voltage)
  • the gate active level voltage is one of the gate high level voltage VGH and the gate low level voltage VGL
  • the gate inactive level voltage is the gate high level voltage VGH And the other of the gate low level voltage VGL.
  • other suitable circuit structures can also be used to implement the mode decoder of the embodiments of the present disclosure
  • the full-on function of the gate drive circuit can be used to turn on the switching elements in all display pixels of the display panel and discharge the charge to avoid the display device.
  • the afterimage problem For example, after the charge is released, the full-off function of the gate drive circuit can also be used to turn off the switching elements in all of the display pixels of the display panel to prepare for the next use of the display panel.
  • FIG. 4 is a block diagram showing the structure of a portion of an address decoder (ie, a 4-16 decoder) in a gate drive circuit provided by some embodiments of the present disclosure.
  • the 4-16 decoder shown in FIG. 4 includes an enable signal input terminal (for example, the enable signal input terminal EN shown in FIG. 4) and four input terminals (for example, the input terminal shown in FIG. 4).
  • A1, A2, A3, and A4) and 16 outputs for example, the outputs B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14 shown in Figure 4) , B15, B16).
  • the 8-input 256-output decoder shown in Figure 2 can be constructed using 17 4-16 decoders as shown in Figure 4, where a 4-16 decoder acts as the main decoder and the other 16 The 4-16 decoder acts as a slave decoder.
  • the four inputs of the main decoder are configured to receive data of four high data bits in the address data (ie, A4, A5, A6, A7 in FIG. 3), 16 from the decoder.
  • Each of the four input terminals of the decoder receives data of four low data bits in the address data (i.e., A0, A1, A2, A3 in Fig. 3).
  • the enable end of the main decoder is connected to the output of the output of the fully closed decoder (ie, the first AND gate), and the enable ends of the 16 slave decoders are respectively associated with the main decoder. 16 outputs are connected.
  • the 4-16 decoder shown in FIG. 4 will be specifically described below.
  • the 4-16 decoder can be composed of five two-four decoders U0, U1, U2, U3, and U4 (5 two).
  • the four decoders can have the same construction).
  • the two inputs of the two-four decoder U0 ie, the main decoder of the 4-16 decoder
  • the input terminals A3 and A4 of the higher digits, and the four outputs of the quadruple decoder U0 for example, the inputs D1, D2, D3 and D4 shown in FIG.
  • the two-four decoder U0 can decompose the decoding of 4-bit binary data into four sets of 2-bit binary data decoding - according to the data size, the high digits are "11" of four kinds of data, high digits Four kinds of data for "10", four kinds of data with high digits of "01”, and four kinds of data with high digits of "00" are successively decremented, so that the second and fourth decoders U4 can be used when the high digit is "11".
  • FIG. 5 is a circuit structural diagram of a two-four decoder provided by some embodiments of the present disclosure.
  • the function of the 24th decoder is realized by a logic circuit composed of 2 NOT gates and 8 AND gates. Based on this, any combination of address decoders can be used by the combination principle shown in FIG.
  • Each is implemented as a minimum component unit 24th decoder, and each of the 24th decoders can be implemented in the form of a gate circuit.
  • the upper edge D flip-flop described in FIG. 2 can also be implemented in the form of a gate circuit with reference to the related art. Therefore, the gate driving circuit shown in FIG.
  • the gate driving circuit of the present disclosure can also realize the output of the scanning signal at the corresponding scanning output according to the received data frame, and can also be combined with the manufacturing process of the array substrate, thereby being When the chip or the external circuit is attached, the gate driving circuit is realized, so that the gate driving circuit formed on the array substrate can be flexibly selected to perform pixel refreshing, thereby simplifying the internal structure of the related product and improving the correlation.
  • Product versatility since the serial data interface composed of the three lines as shown in FIG.
  • the embodiment of the present disclosure can reduce the circuit by using the serial communication as compared with the prior art.
  • the number of interfaces helps to simplify the internal construction of related products.
  • the gate driving circuit can perform data refreshing in flexible pixel rows, flexible local refresh or single-line refresh can be realized, thereby helping to reduce the power consumption caused by the output scan signal, and contributing to the versatility of related products. And endurance.
  • FIG. 6 is a schematic flow chart of a driving method of a gate driving circuit according to some embodiments of the present disclosure, and the gate driving circuit may be a gate driving circuit of any of the above.
  • the driving method includes:
  • Step 601 When receiving the display data of the first frame, sequentially send a data frame including address data of each of the scan output ends to the gate driving circuit.
  • Step 602 When receiving the display data of any frame after the display data of the first frame, determine the refresh scan output end by comparing the display data of the current frame with the display data of the previous frame, and respectively The data frame including the address data of the refresh scan output is sent to the gate drive circuit at a timing corresponding to the refresh scan output.
  • the refresh scan output end is a scan output end of the plurality of scan output ends that needs to output a scan signal when the display screen corresponding to the display data of the previous frame is refreshed to the display screen corresponding to the display data of the current frame.
  • the scan signal may be sequentially outputted at each scan output end by controlling any one of the above-mentioned gate drive circuits, thereby completing data refresh of an entire display area;
  • the display data of any frame picture is received thereafter, only the part that changes compared to the previous frame can be refreshed - the pixel rows corresponding to the scan output can be determined by comparing the display data.
  • There is a change in the display data so that the output of the gate driver can be suspended during the refresh period corresponding to the scan output terminals other than the scan output terminals, and only corresponding to the scan output terminals of the corresponding pixel rows having the change of the display data.
  • the scan signal is adaptively outputted by the control gate drive circuit during the refresh period. In this way, the refresh process of the pixel rows with no change in the picture data can be omitted, and the overall power consumption can be saved.
  • the data transmission state of the serial data interface can be "idle” and “receive data” as shown in FIG. 7 (acquiring data to be transmitted) ), "cache data", “waiting for data” (waiting for the time to send), “serialization” (converted to serial data), “send data”, "idle” ... in the order of loop execution, so that can be coordinated Any of the above gate drive circuits realizes the effect of data refreshing by flexible pixel rows.
  • Yet another embodiment of the present disclosure provides a display device including at least one of the gate drive circuits of any of the above.
  • the display device may also include a controller.
  • the controller is configured to receive the display image (ie, the current display image), obtain a difference between the display image and the previous frame display image, and generate at least one data frame based on the difference.
  • the black screen may be displayed as the zeroth frame.
  • the controller may acquire the difference between the first frame display image and the black frame, and display the image and the black frame based on the first frame.
  • the difference generates at least one data frame (eg, J data frames).
  • the controller generates J data frames indicating that the current display image is displayed, and the gate driving circuit needs to supply scanning signals (effective signals) to the J gate lines so that the J line pixels of the display panel can be refreshed.
  • the controller is further configured such that each of the at least one data frame is a serial data frame, whereby the gate drive circuit can receive the serial data frame.
  • the controller can include a processor and a memory, such as a central processing unit (CPU) or other form of processing unit having data processing capabilities and/or instruction execution capabilities, for example, the processor can be implemented as general purpose processing And also a single chip microcomputer, a microprocessor, a digital signal processor, a dedicated image processing chip, or a field programmable logic array.
  • the memory may include, for example, volatile memory and/or non-volatile memory, and may include, for example, a read only memory (ROM), a hard disk, a flash memory, or the like.
  • the memory can be implemented as one or more computer program products, which can include various forms of computer readable storage media, on which one or more computer programs can be stored instruction.
  • the processor can execute the program instructions to implement the functions of the control device and/or other desired functions in the embodiments of the present disclosure described below.
  • the memory can also store various other applications and various data, as well as various data used and/or generated by the application, and the like.
  • the display device in the embodiment of the present disclosure may be any product or component having a display function such as a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device can also achieve the same or corresponding beneficial effects based on the beneficial effects that the gate drive circuit can achieve.
  • FIG. 8 is an exemplary block diagram of a display device provided by some embodiments of the present disclosure, and a display device provided by some embodiments of the present disclosure is exemplarily described below with reference to FIG. 8 .
  • the display device 60 includes a display panel 6000, a gate driver 6010, a timing controller 6020, and a data driver 6030.
  • the display panel 6000 includes a plurality of pixel units P defined in accordance with a plurality of scan lines GL and a plurality of data lines DL.
  • the gate driver 6010 includes the gate driving circuit provided in any of the above embodiments, the gate driver 6010 includes a plurality of output terminals, and the plurality of output terminals of the gate driver 6010 are respectively connected to the plurality of scanning lines GL, such that The gate driver 6010 can be used to drive a plurality of scan lines GL.
  • the data driver 6030 is for driving a plurality of data lines DL.
  • the timing controller 6020 is for processing the image data RGB input from the outside of the display device 60, supplying the processed image data RGB to the data driver 6030, and outputting the scan control signal GCS and the data control signal to the gate driver 6010 and the data driver 6030, respectively.
  • the DCS controls the gate driver 6010 and the data driver 6030.
  • the display device may also include a controller, which may be implemented, for example, as the timing controller 6020 or in the timing controller 6020.
  • the timing controller 6020 may be connected to the serial data line SD, the serial clock signal line SCLK, and the reception enable signal line SCS to respectively receive the enable signal line via the serial data line SD, the serial clock signal line SCLK, and the reception enable signal line.
  • the SCS provides a data frame, a clock signal, and an enable signal to the gate driver 6010.

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Abstract

一种栅极驱动电路及其驱动方法、显示装置。该栅极驱动电路包括：若干个扫描输出端(G1-Gn)和译码器电路(14)。译码器电路(14)包括多个输入端和多个输出端，译码器电路(14)的多个输出端与若干个扫描输出端(G1-Gn)一一对应；译码器电路(14)的多个输入端被配置为接收并行的数据帧；译码器电路(14)配置在接收到并行的数据帧时，在译码器电路(14)的、与并行的数据帧对应的输出端处输出用于生成扫描信号的触发信号，以使得与并行的数据帧对应的扫描输出端处输出扫描信号。该栅极驱动电路可以实现阵列基板的局部扫描。

Description

栅极驱动电路及其驱动方法、显示装置
对相关申请的交叉参考
本申请要求于2018年3月30日递交的中国专利申请第201810277584.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种栅极驱动电路及其驱动方法、显示装置。
背景技术
阵列基板通常包括彼此交叉的多行栅线和多列数据线。对栅线的驱动可以通过贴附的集成驱动电路实现。近几年随着非晶硅薄膜工艺的不断提高，也可以将栅极驱动电路直接集成在薄膜晶体管阵列基板上构成阵列基板上的栅驱动集成GOA(Gate driver On Array)来对栅线进行驱动。
GOA技术相较于传统技术而言，不仅能省去承载栅极驱动芯片的电路板、实现显示面板两边对称的设计，还能省去位于显示面板边缘的芯片绑定区域和布线区域(例如，扇出区)，由此有利于窄边框设计的实现。
发明内容
本公开的至少实施例提供一种栅极驱动电路，该栅极驱动电路包括：若干个扫描输出端和译码器电路。所述译码器电路包括多个输入端和多个输出端，所述译码器电路的多个输出端与所述若干个扫描输出端一一对应；所述译码器电路的多个输入端被配置为接收并行的数据帧；所述译码器电路配置在接收到所述并行的数据帧时，在所述译码器电路的、与所述并行的数据帧对应的输出端处输出用于生成扫描信号的触发信号，以使得与所述并行的数据帧对应的扫描输出端处输出所述扫描信号。
例如，在所述栅极驱动电路的至少一个示例中，所述栅极驱动电路还包括：串并转换电路以及与所述串并转换电路相连的锁存器电路。所述串并转 换电路用于接收串行的数据帧，并将所述串行的数据帧转换为所述并行的数据帧；所述锁存器电路用于接收并存储所述并行的数据帧，并在所述数据帧接收完成时将所述并行的数据帧输出；所述译码器电路与所述锁存器电路相连，以接收所述锁存器电路输出的所述并行的数据帧，所述译码器电路用于在接收到所述锁存器电路输出的数据帧时，在所述译码器电路的、与所述并行的数据帧对应的输出端处输出所述用于生成所述扫描信号的触发信号。
例如，在所述栅极驱动电路的至少一个示例中，所述译码器电路包括地址译码器，所述并行的数据帧包括并行的地址数据；所述地址译码器包括多个输入端和多个输出端；所述地址译码器的多个输入端的每个被配置为接收所述并行的地址数据中的一位；所述地址译码器被配置为在接收到所述并行的地址数据之后，经由所述地址译码器的、与所述并行的地址数据相对应的输出端输出所述用于生成所述扫描信号的触发信号。
例如，在所述栅极驱动电路的至少一个示例中，所述地址译码器为m-n译码器；以及所述m等于所述地址译码器的输入端的个数，所述n等于所述地址译码器的输出端的个数。
例如，在所述栅极驱动电路的至少一个示例中，所述m-n译码器包括至少一个二四译码器。
例如，在所述栅极驱动电路的至少一个示例中，所述译码器电路还包括模式译码器；所述并行的数据帧还包括并行的模式数据，所述并行的模式数据与所述并行的地址数据在所述并行的数据帧中彼此并列；所述模式译码器被配置为在所述并行的模式数据对应于全关模式时，使得所述译码器的所有的输出端均不输出所述用于生成所述扫描信号的触发信号或均输出所述用于生成所述扫描信号的触发信号。
例如，在所述栅极驱动电路的至少一个示例中，所述模式译码器包括全关译码器；所述全关译码器被配置为在所述并行的模式数据对应于全关模式时，向所述地址译码器的使能端提供无效信号，以使得所述译码器的所有的输出端均不输出所述用于生成所述扫描信号的触发信号。
例如，在所述栅极驱动电路的至少一个示例中，所述全关译码器包括第一与门；所述并行的模式数据包括第一位数据和第二位数据；所述第一与门的第一输入端被配置为接收与所述第一位数据反相的数据；所述第一与门的 第二输入端被配置为接收所述第二位数据；所述第一与门的输出端被配置为与所述地址译码器的使能端相连。
例如，在所述栅极驱动电路的至少一个示例中，所述模式译码器包括全开译码器；所述全开译码器被配置为在所述并行的模式数据对应于全开模式时，使得所述译码器的所有的输出端输出均输出所述用于生成所述扫描信号的触发信号。
例如，在所述栅极驱动电路的至少一个示例中，所述全开译码器包括第二与门以及多个或门；所述并行的模式数据包括第一位数据和第二位数据；所述第二与门的第一输入端被配置为接收所述第一位数据；所述第二与门的第二输入端被配置为接收所述第二位数据；所述第二与门的输出端被配置为与所述多个或门中的每个或门的第一输入端相连；所述多个或门的第二输入端分别与所述地址译码器的多个输出端相连。
例如，在所述栅极驱动电路的至少一个示例中，所述栅极驱动电路还包括电平转换电路。所述电平转换电路被配置为接收所述用于生成扫描信号的触发信号，将所述用于生成扫描信号的触发信号转换为所述扫描信号，以及使得所述扫描信号经由与所述并行的数据帧对应的扫描输出端输出。
例如，在所述栅极驱动电路的至少一个示例中，所述栅极驱动电路还包括串行数据接口。所述串并转换电路与所述串行数据接口相连，以经由所述串行数据接口接收所述串行的数据帧。
例如，在所述栅极驱动电路的至少一个示例中，所述串行数据接口包括串行数据线和串行时钟信号线；所述串行数据线和所述串行时钟信号线均与所述串并转换电路相连；所述串并转换电路用于在每次所述串行时钟信号线上的电信号满足触发条件时读取所述串行数据线上的一位数据。
例如，在所述栅极驱动电路的至少一个示例中，所述串并转换电路包括至少两级触发器；所述至少两级触发器的触发输入端均与所述串行时钟信号线相连，每级所述触发器输出所述并行的数据帧的一位数据；以及第一级所述触发器的输入端与所述串行数据线相连，除第一级以外的任意一级所述触发器的输入端与上一级所述触发器的输出端相连。
例如，在所述栅极驱动电路的至少一个示例中，所述至少两级触发器的每个为D触发器。
例如，在所述栅极驱动电路的至少一个示例中，所述串行数据接口还包括与所述锁存器电路电连接的接收使能信号线，所述锁存器电路用于在所述接收使能信号线上的电信号由有效电平转为无效电平时将所述并行的数据帧输出。
例如，在所述栅极驱动电路的至少一个示例中，所述锁存器电路包括至少两个边沿触发器；所述至少两个边沿触发器的触发输入端均与所述接收使能信号线电连接，每个所述边沿触发器的输入端接收所述并行的数据帧的一位数据，每个所述边沿触发器的输出端可输出所述并行的数据帧的一位数据。
例如，在所述栅极驱动电路的至少一个示例中，所述至少两个边沿触发器的每个为D触发器。
例如，在所述栅极驱动电路的至少一个示例中，还包括反相器，所述反相器包括输入端和输出端；所述反相器的输入端与所述接收使能信号线相连，以接收所述接收使能信号线上的电信号；所述反相器被配置为将接收到的所述接收使能信号线上的电信号反相后从所述反相器的输出端输出；以及所述反相器的输出端与所述至少两个边沿触发器的每个的触发输入端相连。
例如，在所述栅极驱动电路的至少一个示例中，所述串口数据接口为串行外设接口SPI的串行总线接口，所述数据帧包括地址数据和模式数据，所述译码器电路包括地址译码器、模式译码器和若干个电平转换器。所述地址译码器以二四译码器为最小组成单元，用于在接收到所述锁存器电路输出的数据帧中的所述地址数据时，向与所述数据帧中的地址数据相对应的电平转换器输出触发信号；每个所述电平转换器与一个所述扫描输出端相连，可用于在接收到所述地址译码器输出的所述触发信号时，在与所述每个所述电平转换器连接的扫描输出端处输出所述扫描信号；所述模式译码器用于在接收到所述锁存器电路输出的数据帧中的所述模式数据且所述模式数据所对应的工作模式为全开模式时，使得所述若干个扫描输出端均输出栅极有效电平电压，以使得所述若干个扫描输出端均输出所述扫描信号；以及所述模式译码器用于在接收到所述锁存器电路输出的数据帧中的所述模式数据且所述模式数据所对应的工作模式为全关模式时，使得所述若干个扫描输出端均输出栅极无效电平电压，以使得所述若干个扫描输出端均不输出所述扫描信号。
例如，在所述栅极驱动电路的至少一个示例中，所述数据帧包括地址数 据；以及所述译码器电路被配置为在所述译码器电路的、与所述地址数据对应的输出端处输出所述用于生成所述扫描信号的触发信号。
例如，在所述栅极驱动电路的至少一个示例中，所述数据帧还包括模式数据；所述译码器电路用于在接收到所述并行的数据帧时，根据所述数据帧中的模式数据确定当前的工作模式，所述当前的工作模式包括一般模式；在所述当前的工作模式为一般模式时，所述译码器电路被配置为在所述译码器电路的、与所述数据帧中的地址数据相对应的输出端处输出所述用于生成所述扫描信号的触发信号。
例如，在所述栅极驱动电路的至少一个示例中，所述当前的工作模式还包括全开模式；在所述当前的工作模式为所述全开模式时，所述译码器电路被配置为使得所述若干个扫描输出端处同时输出栅极有效电平电压，以使得所述若干个扫描输出端均输出所述扫描信号。
例如，在所述栅极驱动电路的至少一个示例中，所述当前的工作模式还包括全关模式；以及在所述当前的工作模式为全关模式时，所述译码器电路被配置为使得所述若干个扫描输出端处同时输出栅极无效电平电压，以使得所述若干个扫描输出端均不输出所述扫描信号。
本公开的至少实施例还提供一种显示装置，该显示装置包括本公开任一实施例提供的所述的栅极驱动电路。
例如，在所述显示装置的至少一个示例中，所述显示装置还包括控制器。所述控制器被配置为接收显示图像，获取所述显示图像与前一帧显示图像的差异，并基于所述差异生成至少一个数据帧。
例如，在所述显示装置的至少一个示例中，所述控制器还被配置为使得所述至少一个数据帧的每个为串行的数据帧。
本公开的至少实施例又提供一种用于驱动本公开任一实施例提供的栅极驱动电路的驱动方法。所述驱动方法包括：在接收到第一帧的显示数据时，依次将包括每一所述扫描输出端的地址数据的数据帧发送至所述栅极驱动电路；在接收到所述第一帧的显示数据之后的任一帧的显示数据时，通过比较当前帧的显示数据与上一帧的显示数据确定刷新扫描输出端，并分别在与每个所述刷新扫描输出端对应的时刻将包括该刷新扫描输出端的地址数据的数据帧发送至所述栅极驱动电路，其中，所述刷新扫描输出端是在将所述上一 帧的显示数据所对应的显示画面刷新为所述当前帧的显示数据所对应的显示画面时，所述若干个扫描输出端中需要输出扫描信号的扫描输出端。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1是本公开的一些实施例提供的栅极驱动电路的示例性结构框图；
图2是本公开的一些实施例提供的栅极驱动电路的电路结构图；
图3是本公开的一些实施例提供的栅极驱动电路的电路时序图；
图4是本公开的一些实施例提供的栅极驱动电路中的地址译码器的一部分的示例性结构框图；
图5是本公开的一些实施例提供的一种二四译码器的电路结构图；
图6是本公开的一些实施例中一种栅极驱动电路的驱动方法的流程示意图；
图7是本公开的一些实施例中一种串行数据接口的数据发送状态变化图；以及
图8是本公开的一些实施例提供的显示装置的示例性框图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面 的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的发明人在研究中注意到，相关设计中的栅极驱动电路(GOA)电路只能够实现阵列基板的所有像素行(或者特定部分像素行)的逐行打开，以实现逐行数据刷新，而无法仅打开指定行的像素，由此无法灵活选择像素行进行数据刷新。
本公开的至少实施例提供一种栅极驱动电路、栅极驱动电路的驱动方法以及显示装置。该栅极驱动电路包括若干个扫描输出端和译码器电路。译码器电路包括多个输入端和多个输出端，译码器电路的多个输出端与若干个扫描输出端一一对应；译码器电路的多个输入端被配置为接收并行的数据帧；译码器电路配置在接收到并行的数据帧时，在译码器电路的、与并行的数据帧对应的输出端处输出用于生成扫描信号的触发信号，以使得与并行的数据帧对应的扫描输出端处输出扫描信号。
在一些示例中，通过采用译码器，在栅极驱动电路在接收到一个数据帧时，栅极驱动电路的若干个扫描输出端中的一个输出端输出扫描信号(有效信号)，因此，栅极驱动电路可以向一根(唯一一根)栅线提供有效信号，并可以仅打开与上述一根(唯一一根)栅线连接的一行像素，由此本公开的一些示例提供的栅极驱动电路可以实现阵列基板(或显示面板)的局部扫描。例如，在使用栅极驱动电路刷新显示面板的一帧显示画面时，栅极驱动电路可以仅接收几个(例如，3个或10个)数据帧，此种情况下，栅极驱动电路仅需向显示面板的几根栅线(例如，3根或10根)提供有效信号，以针对显示面板的几行显示像素(例如，3行或10行)进行数据刷新，由此可以避免逐行打开显示面板的显示像素，进而可以降低采用了该栅极驱动电路的显示面板和显示装置的功耗，提升采用了该栅极驱动电路的显示面板和显示装置的刷新速度、续航能力以及用户体验。
在一些示例中，栅极驱动电路还可以包括串并转换电路和锁存器电路。通过采用串并转换电路和锁存器电路，栅极驱动电路可以与串行数据接口连接，并可以经由串行数据接口接收源于系统端(例如，控制器)的数据帧， 由此可以减少栅极驱动电路的总线数量(和/或电路接口数量)，提高栅极驱动电路的通用性。例如，在无需考虑栅极驱动电路的总线数量(或电路接口数量)和通用性的情况下，栅极驱动电路还可以不设置串并转换电路和锁存器电路，此种情况下，栅极驱动电路可以经由并行数据接口接收并行的数据帧，并将该并行的数据帧提供给译码器，该译码器可以基于上述并行的数据帧，在与该并行的数据帧对应的扫描输出端处输出扫描信号。此种情况下，栅极驱动电路还可以不设置串行数据接口。
在一些示例中，译码器可以包括模式译码器，通过设置模式译码器，栅极驱动电路可以经由若干个扫描输出端G1、G2、…、Gn向(同时向)阵列基板(或显示面板)的所有栅线提供无效信号或有效信号，由此可以关闭或打开(例如，同时关闭或打开)阵列基板(或显示面板)的所有显示像素。需要说明的是，在不需要向(同时向)阵列基板(或显示面板)的所有栅线提供无效信号或有效信号的情况下，译码器可以不包括模式译码器，此种情况下，译码器可以仅包括地址译码器。
在一些示例中，栅极驱动电路的相关功能可以全部由门电路和晶体管实现，而门电路可以采用能够制作在阵列基板上晶体管和电容的组合来实现(还可以通过即现场可编程门阵列FPGA来实现)，因此本公开的一些示例中的栅极驱动电路可以基于阵列基板的制作工艺制作，此种情况下，采用本公开的一些示例中的栅极驱动电路的阵列基板和显示面板无需贴附芯片或外接电路，由此可以降低采用本公开的一些示例中的栅极驱动电路的阵列基板和显示面板的制作成本。需要说明的是，在不要求栅极驱动电路实现为GOA的情况下，栅极驱动电路的部分功能还可以采用门电路之外的电路来实现，以进一步地提升栅极驱动电路的性能。
需要说明的是，在一些示例中，扫描输出端输出扫描信号是指扫描输出端输出有效信号，扫描输出端不输出扫描信号是指扫描输出端输出无效信号。
需要说明的是，在本公开的至少一个实施例中，有效信号(例如，有效电平)是指用于开启与栅极驱动电路电连接的相关显示像素的开关元件的信号，无效信号(例如，无效电平)是指用于关闭栅极驱动电路电连接的相关显示像素的信号。
下面通过几个示例对本公开的实施例提供的栅极驱动电路进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例中不同特征 可以相互组合，从而得到新的示例，这些新的示例也都属于本公开保护的范围。
本公开的一些实施例提供了一种栅极驱动电路，该栅极驱动电路可用于驱动阵列基板，例如，向阵列基板的栅线提供有效信号。图1是本公开的一些实施例提供的栅极驱动电路的示例性结构框图。参见图1，该栅极驱动电路包括：若干个扫描输出端G1、G2、…、Gn；串行数据接口11；与串行数据接口11相连的串并转换电路12，与串并转换电路12相连的锁存器电路13，分别与锁存器电路13和每个扫描输出端相连的译码器电路14。串并转换电路12用于通过串行数据接口11接收串行的数据帧，并将串行的数据帧转换为并行的数据帧；锁存器电路13用于接收并存储并行的数据帧，并在所述数据帧接收完成时将所述并行的数据帧输出；译码器电路14与锁存器电路13相连，以接收锁存器电路13输出的并行的数据帧，译码器电路14与用于在接收到锁存器电路13输出的并行的数据帧时，在在译码器电路14的、与并行的数据帧对应的输出端处输出用于生成扫描信号的触发信号，以使得与数据帧对应的扫描输出端处输出扫描信号。
例如，栅极驱动电路接收多个数据帧时，锁存器电路13被配置为在任一个所述数据帧接收完成后，将上述任一个所述数据帧对应的并行的数据帧存储并输出。
在一些示例中，基于串行数据接口以及均能够在阵列基板上以逻辑电路形式实现的、串并转换电路、锁存器电路和译码器电路，本公开的一些实施例能够通过串行数据接口接收数据帧，并按照数据帧选择对应的扫描输出端进行扫描信号的输出，因而可以使能制作在阵列基板上得栅极驱动电路具备能够灵活选择像素行进行数据刷新的功能。例如，还可以利用串行通信减少电路接口数量，有助于简化相关产品的内部构造，并提升相关产品的通用性和续航能力。
应理解的是，当采用二进制数据构成所述数据帧时，每个数据帧的二进制位的数量应当与扫描输出端的数量相匹配。例如，包括n个(n为正整数)可用数据位的数据帧可以最多用于区分包括2 n个扫描输出端的栅极驱动电路的扫描输出端，比如n＝2时，二进制数“00”、“01”、“10”、“11”可以将2 2＝4个扫描输出端区分开。
图2是本公开的一些实施例提供的栅极驱动电路的电路结构图。图3是 该栅极驱动电路的电路时序图。图2所示的栅极驱动电路中，串行数据接口11包括串行数据线SD、串行时钟信号线SCLK和接收使能信号线SCS(例如，用于提供使能信号)。作为一种示例，串口数据接口11可以是串行外设接口SPI的串行总线接口，该串行总线接口按照串行外设接口SPI所对应的串口通信协议传输数据。在图2所示的实施例中，栅极驱动电路包括256个扫描输出端G1、G2、…、G255、G256。
例如，栅极驱动电路接收的数据帧的结构可以如图3中串行数据线SD上的信号时序所示的那样，也即栅极驱动电路接收的数据帧可以包括16位二进制数据，这里，M1和M0两个二进制数据位用来承载模式数据；A0、A1、A2、A3、A4、A5、A6、A7八个二进制数据位用来承载地址数据；PC为用于进行奇偶校验的奇偶校验位(例如根据数据帧中“1”的个数是奇数还是偶数来校验是否出现传输错误)；A8、A9和三个DMY共五个二进制数据位是暂未使用的数据位，例如，可以在扫描输出端的数量增加(例如，1024个)时利用上述暂未使用的数据位(例如，额外使用两个数据为)承载地址数据。例如，图3所示的数据帧的结构最多可用于区分2 13＝8192个扫描输出端。例如，在不考虑传输误差的情况下，还可以将奇偶校验位用于承载地址数据，此种情况下，图3所示的数据帧的结构最多可用于区分2 14＝16384个扫描输出端。因此，图3所示的数据帧的结构使得栅极驱动电路适用于驱动常规的显示面板。
在图2中，串并转换电路12包括10个上边沿D触发器，10个上边沿D触发器逐级连接形成移位寄存器电路，从而可以配合如图3所示的串行数据线SD、串行时钟信号线SCLK上的信号实现串行的数据帧的接收以及串并转换。具体来说，第一级的上边沿D触发器的输入端(图2中以“D”标识的一端)连接串行数据线SD，第一级以外的任意一级上边沿D触发器的输入端与其上一级上边沿D触发器的输出端(图2中以“Q”标识的一端)相连，此外10个上边沿D触发器的触发输入端(图2中以三角形标识的一端)均连接串行时钟信号线SCLK，从而串行时钟信号线SCLK的每个上升沿触发一次移位操作——每当串行时钟信号线SCLK上出现一个上升沿时，10个上边沿D触发器中的每一个都会将输出端处的电平置为与输入端处相同的电平，由此在10个上边沿D触发器的输出端处完成了一次移位操作，例如第一至八级的上边沿D触发器的输出端处在串行时钟信号线SCLK上的上升沿 到来之前为“1011100000”，那么在串行时钟信号线SCLK上的上升沿到来时串行数据线SD上的电平“0”会取代第一级上边沿D触发器的输出端处的电平，同时每一级上边沿D触发器的输出端处的电平取代下一级上边沿D触发器的输出端处的电平，最后一级上边沿D触发器的输出端处的电平将会消失，从而变为“0101110000”，即所有数据位向右移动了一位。应理解的是，在串并转换电路12包括10个上边沿D触发器，对于图3所示的数据帧结构，最开始的三个DMY、A8、A9和PC的共6个数据位会随着移位操作的进行而消失，即在图2所示的栅极驱动电路中没有被利用，在接收使能信号线SCS的下降沿标志的数据帧结束时，10个上边沿D触发器的输出端保留的是该数据帧中A0、A1、A2、A3、A4、A5、A6、A7、M0、M1共十个数据位的数据。当然，也可以在图2所示的串并转换电路12在上述10个上边沿D触发器之后继续按照同样规律设置6个上边沿D触发器，从而实现数据帧中所有数据位的接收。
需要说明的是，为方便描述，在下面的描述中，A0、A1、A2、A3、A4、A5、A6、A7、M0、M1还用于描述和示出锁存器电路13包括的分别输出A0、A1、A2、A3、A4、A5、A6、A7、M0、M1的上边沿D触发器。
例如，对于需要译码的数据包括n(n为正整数)个二进制数据位的数据帧来说，可以由至少n级D触发器实现上述串并转换电路12功能。连接关系上，至少n级D触发器的触发输入端均与串行时钟信号线相连，第一级D触发器的输入端与串行数据线相连，除第一级以外的任意一级D触发器的输入端与上一级D触发器的输出端相连，从而可以实现上述移位寄存器电路的构造。
需要说明的是，除了可以使用上边沿作为串行时钟信号线上的电信号(也即，时钟信号)的触发条件，还可以使用例如下边沿、高电平或者低电平作为该触发条件，串行时钟信号线上的电信号的触发条件可以不仅限于上述列举的示例。可以看出，串并转换电路能够在每次串行时钟信号线上的电信号满足触发条件时读取串行数据线上的一位数据；当然还可以采用其他能够实现将串行信号转换为并行信号的功能的电路结构实现本公开实施例的串并转换电路。
在图2中，锁存器电路13包括多个上边沿D触发器，锁存器电路13包括的上边沿D触发器的数目等于串并转换电路12包括的上边沿D触发器数 目，锁存器电路13包括的多个上边沿D触发器的输入端分别与串并转换电路12包括的多个上边沿D触发器相连，以分别接收并存储并行的数据帧的一位数据。
如图2所示，在串并转换电路12包括10个上边沿D触发器的情况下，锁存器电路13包括10个上边沿D触发器，这10个上边沿D触发器的触发输入端均与接收使能信号线SCS经过一个反相器连接，从而10个上边沿D触发器会在接收使能信号线SCS的下降沿的触发下将锁存器电路13包括多个上边沿D触发器的输出端处的电平置为与输入端处的电平相同的电平，即各自将一位二进制数据进行输出。如此，锁存器电路13可以在接收使能信号线SCS上由有效电平转为无效电平时将来自串并转换电路12的并行的数据帧输出。
需要说明的是，本公开的一些实施例中的有效电平与无效电平分别指的是针对特定电路节点而言的两个不同的预先配置的电压范围(均以公共端电压为基准)。在一个示例中，所有电路节点的有效电平均为高电平。在又一示例中，所有电路节点的有效电平均为低电平。例如，对于接收使能信号线SCS来说，有效电平意味着正在或将要有数据帧传输，而有效电平转为无效电平则意味着一个数据帧的传输结束。
例如，对于来自串并转换电路12的并行的数据帧包括n个二进制数据位的情形来说，可以由至少n个边沿D触发器实现上述锁存器电路13功能。所述至少n个边沿D触发器的触发输入端均与所述接收使能信号线相连(并可以经过一个或多个的反相器)，每个所述边沿D触发器的输入端接收所述并行的数据帧的一位数据，每个所述边沿D触发器的输出端输出所述并行的数据帧的一位数据。在另一个示例中，也可以使用去除图2中反相器的设置而使用10个下边沿D触发器实现上述锁存器电路13功能。
需要说明的是，串并转换电路12和锁存器电路13不限于包括D触发器，根据实际应用需求，串并转换电路12和锁存器电路13还可以采用其它适用的触发器。
例如，译码器电路包括地址译码器，并行的数据帧包括并行的地址数据；地址译码器包括多个输入端和多个输出端；地址译码器的多个输入端的每个被配置为接收并行的地址数据中的一位；地址译码器被配置为在接收到并行的地址数据之后，经由地址译码器的、与并行的地址数据相对应的输出端输 出用于生成扫描信号的触发信号。
例如，地址译码器为m-n译码器(例如，8输入256输出的译码器)；m等于地址译码器的输入端的个数，n等于地址译码器的输出端的个数。例如，m-n译码器包括至少一个二四译码器。
例如，译码器电路还包括模式译码器；并行的数据帧包括并行的模式数据，并行的模式数据与并行的地址数据在并行的数据帧中彼此并列；模式译码器被配置为在并行的模式数据对应于全关模式时，使得译码器的所有的输出端均不输出用于生成扫描信号的触发信号或均输出用于生成扫描信号的触发信号。
例如，模式译码器包括全关译码器；全关译码器被配置为在并行的模式数据对应于全关模式时，向地址译码器的使能端提供无效信号，以使得译码器的所有的输出端均不输出用于生成扫描信号的触发信号。
例如，全关译码器包括第一与门(例如，图2中模式译码器142中位于上方的与门)；并行的模式数据包括第一位数据(例如，M0)和第二位数据(例如，M1)；第一与门的第一输入端被配置为接收与第一位数据反相的数据；第一与门的第二输入端被配置为接收第二位数据；第一与门的输出端被配置为与地址译码器的使能端相连。
例如，在栅极驱动电路的至少一个示例中，模式译码器包括全开译码器；全开译码器被配置为在并行的模式数据对应于全开模式时，使得译码器的所有的输出端输出均输出用于生成扫描信号的触发信号。
例如，在栅极驱动电路的至少一个示例中，全开译码器包括第二与门(例如，图2中模式译码器142中位于下方的与门)以及多个或门(例如，图2中多个电平转换器143包括的或门)；并行的模式数据包括第一位数据和第二位数据；第二与门的第一输入端被配置为接收第一位数据；第二与门的第二输入端被配置为接收第二位数据；第二与门的输出端被配置为多个或门中的每个或门的第一输入端相连；多个或门的第二输入端分别与地址译码器的多个输出端相连。
例如，栅极驱动电路还包括多个电平转换电路(图2中未示出)。多个电平转换电路的每个被配置为接收用于生成扫描信号的触发信号，将用于生成扫描信号的触发信号转换为扫描信号，以及使得扫描信号经由与并行的数 据帧对应的扫描输出端输出。例如，触发信号的电平的绝对值约为0.1-0.6伏，例如，扫描信号的电平的绝对值约为10-16伏。例如，多个电平转换电路的输入端分别与多个或门的输出端相连，多个电平转换电路的输出端分别连接至栅极驱动电路的扫描输出端，以使得扫描信号可经由与并行的数据帧对应的扫描输出端输出。例如，多个电平转换电路的每个可以实现为晶体管(例如，互补金属氧化物半导体晶体管)。
例如，下面以图2所示的示例对译码器电路14和电平转换电路进行示例性说明。
在图2中，译码器电路14包括地址译码器141、模式译码器142和若干个电平转换器143。这里，图2所示的实施例中的地址译码器141具体为8输入256输出的译码器，即可以根据输入端S1、S2、…、S7、S8的八位二进制数据在256个输出端D1、D2、D3、D4、…、D253、D254、D255和D256中与该二进制数据相对应的输出端处输出有效电平。由此可知，地址数据对应于需要输出扫描信号的扫描输出端在若干个扫描输出端之间的标识，比如二进制数据“01011100”的十进制数为“92”，因此地址译码器141可以在输入的并行的地址数据为“01011100”时在第92个输出端D92处输出有效电平，以使其所连接的电平转换器143在接收到该有效电平时在所连接的256个扫描输出端中的第92个扫描输出端输出扫描信号。可以看出，地址译码器141的功能主要是在接收到锁存器电路13输出的数据帧中的地址数据时，向与数据帧中的地址数据相对应的电平转换器143输出触发信号(例如上述有效电平)。一般来说，对于需要译码的数据包括n位二进制数据的情况来说，相应的地址译码器应当包括n个输入端和2 n个输出端。
图2所示的模式译码器142采用了如下表所示的工作模式控制。
表1 译码器电路的工作模式表
Figure PCTCN2019080118-appb-000001
如表1所示，当M1为0时，无论M0是0还是1，译码器电路14的工作模式均为一般模式；当M1为1、M0为0时，译码器电路14的工作模式 均为全关模式；当M1为1、M1也为1时，译码器电路14的工作模式均为全开模式。
关于全关模式：如图2所示，模式译码器142包括两个与门(例如，在竖直方向上并列布置的两个与门)，其中上方与门的一个输入端(例如，第一输入端)连接锁存器电路13中与M0对应的上边沿D触发器的反向输出端(图2中以
Figure PCTCN2019080118-appb-000002
表示)，上方与门的另一个输入端(例如，第二输入端)连接锁存器电路13中与M1对应的上边沿D触发器的输出端，因此当M1为1、M0为0时该与门输出高电平，从而与该与门的输出端相连的地址译码器141的低电平有效的使能端ENB处将变为高电平，此时地址译码器141将不会工作，无论输入端输入什么数据输出端都全部为无效电平，因此所有扫描输出端都不输出扫描信号，由此可以通过M1为1、M0为0的模式数据实现栅极驱动器的全关控制功能。
关于全开模式：如图2所示，模式译码器142包括的两个与门中下方的与门的一个输入端(例如，第一输入端)连接锁存器电路13中与M0对应的上边沿D触发器的输出端，下方的与门的另一个输入端(例如，第二输入端)连接锁存器电路13中与M1对应的上边沿D触发器的输出端，因此当M1为1、M0也为1时该与门输出高电平。而由于该与门的输出连接到每一个若干个电平转换器143的两个输入端中的一个，而且每个电平转换器143包括一个或门，每个电平转换器143例如还包括一个电平转换电路(图中未示出)，电平转换电路的输入端与或门的输出端相连，因此此时无论地址译码器141的输出是什么状态，所有扫描输出端均会被或门置为高电平。由此，可以通过M1为1、M0为1的模式数据实现栅极驱动器的全开控制功能。
关于一般模式：当M1为0时，M0为0或1时，模式译码器142的两个与门均输出低电平，从而地址译码器141处于工作状态，且每个电平转换器143的输出端处的电平与其所连接的地址译码器141的一个输出端处的电平相同。从而，地址译码器141的哪个输出端处为高电平，其所连接的电平转换器143就输出高电平。可以理解的是，电平转换器143的输出端处的高电平可以例如是栅极高电平电压VGH(例如，扫描信号)，电平转换器143的输出端处的低电平可以例如是栅极低电平电压VGL，如此可以实现在接收到地址译码器141输出的触发信号时在所连接的扫描输出端处输出扫描信号的功能。例如，栅极高电平电压VGH的电压值大于栅极低电平电压VGL的 电压值。例如，栅极高电平电压VGH绝对值为10-16伏，栅极低电平电压VGL为零伏。又例如，栅极高电平电压VGH和栅极低电平电压VGL绝对值均为10-16伏，且栅极低电平电压VGL为负值。
例如，上述示例中译码器电路14所执行的过程相当于：根据数据帧中的模式数据确定当前的工作模式，从而在当前的工作模式为一般模式时在与数据帧中的地址数据相对应的扫描输出端处输出扫描信号，在当前的工作模式为全开模式时在若干个扫描输出端处同时输出栅极有效电平电压，在当前的工作模式为全关模式时在若干个扫描输出端处同时输出栅极无效电平电压。
例如，在本公开的一种实现方式中，模式译码器14用于在接收到锁存器电路13输出的数据帧中的模式数据且模式数据所对应的工作模式为全开模式时，将若干个扫描输出端导通至栅极有效电平电压(例如，使得若干个扫描输出端均输出栅极有效电平电压)；和/或，模式译码器14用于在接收到锁存器电路13输出的数据帧中的模式数据且模式数据所对应的工作模式为全关模式时，将若干个扫描输出端导通至栅极无效电平电压(例如，使得若干个扫描输出端均输出栅极无效电平电压)；这里，栅极有效电平电压是栅极高电平电压VGH和栅极低电平电压VGL中的一个，栅极无效电平电压是栅极高电平电压VGH和栅极低电平电压VGL中的另一个。当然，还可以采用其他适用的电路结构实现本公开实施例的模式译码器。
例如，在正常显示结束后(或显示面板的关机阶段)，可以使用栅极驱动电路的全开功能，以将显示面板的所有的显示像素中的开关元件均打开并释放电荷，以避免显示装置的残影问题。例如，在电荷释放完毕后，还可以使用栅极驱动电路的全关功能，以将显示面板的所有的显示像素中的开关元件均关闭，以为显示面板的下次使用做好准备。
图4是本公开的一些实施例提供的栅极驱动电路中的地址译码器的一部分(也即，4-16译码器)的结构框图。可以看出图4所示的4-16译码器包括使能信号输入端(例如，图4示出的使能信号输入端EN)、4个输入端(例如，图4示出的输入端A1、A2、A3和A4)和16个输出端(例如，图4示出的输出端B1、B2、B3、B4、B5、B6、B7、B8、B9、B10、B11、B12、B13、B14、B15、B16)。图2所示的8输入256输出的译码器可以使用17个图4所示的4-16译码器搭建而成，其中，一个4-16译码器作为主译码器，另外16个4-16译码器作为从译码器。例如，主译码器的四个输入端配置为 接收地址数据中的四位高数据位的数据(也即，图3中的A4、A5、A6、A7)，16个从译码器中的每个从译码器的四个输入端接收地址数据中的四位低数据位的数据(也即，图3中的A0、A1、A2、A3)。例如，主译码器的使能端与全关译码器的输出端(也即，第一与门)的输出端相连，16个从译码器的使能端分别与主译码器的16个输出端相连。
下面具体说明图4所示的4-16译码器，如图4所示，4-16译码器可以由5个二四译码器U0、U1、U2、U3、U4构成(5个二四译码器可以具有的同样构造)。其中，二四译码器U0(也即，4-16译码器的主译码器)的两个输入端(例如，图4示出的输入端S1和S2)连接地址译码器的两个高数位的输入端A3和A4，二四译码器U0的四个输出端(例如，图4示出的输入端D1、D2、D3和D4)分别连接后面四个二四译码器(也即，4-16译码器的四个从译码器)的使能端ENB；此外，后面四个二四译码器的输入端均连接地址译码器的两个低数位的输入端A1和A2，且每个二四译码器的输出端各自连接地址译码器的一组输出端(例如，4个输出端)。从而，该二四译码器U0可以把4位的二进制数据的译码分解为4组2位的二进制数据的译码——按照数据大小，高数位为“11”的4种数据、高数位为“10”的4种数据、高数位为“01”的4种数据以及高数位为“00”的4种数据依次递减，因而可以在高数位为“11”时由二四译码器U4来根据两个低数位在“11XX”的范围内寻址，在高数位为“10”时由二四译码器U3来根据两个低数位在“10XX”的范围内寻址，在高数位为“01”时由二四译码器U2来根据两个低数位在“01XX”的范围内寻址，在高数位为“00”时由二四译码器U1来根据两个低数位在“00XX”的范围内寻址。可以看出，通过这样的组合可以通过5个二四译码器构成一个4-16译码器。
同理，也可以继续将这样的5个4-16译码器构成一个8-256译码器，从而用于作为图2中所示的地址译码器141。
图5是本公开的一些实施例提供的一种二四译码器的电路结构图。图5中，以2个非门和8个与门组成的逻辑电路实现了二四译码器的功能，基于此，可以利用图4所示的组合原理将任意一种地址译码器由若干个作为最小组成单元二四译码器实现，而每个二四译码器均可以以门电路的形式实现。此外，图2中所述的上边沿D触发器也可以参照相关技术采用门电路的形式实现。由此，图2所示的栅极驱动电路可以全部由门电路实现，而门电路可 以采用能够制作在阵列基板上晶体管和电容的组合来实现(还可以通过即现场可编程门阵列FPGA来实现)，因此本公开的栅极驱动电路在能够实现根据接收到的数据帧在相应的扫描输出端处输出扫描信号的基础上，还可以与阵列基板的制作工艺相结合，由此可以在不需要贴附芯片或外接电路的情况下实现栅极驱动电路，因而可以使能制作在阵列基板上得栅极驱动电路具备能够灵活选择像素行进行数据刷新的功能，简化相关产品的内部构造，提升相关产品的通用性。而且，由于如图2所示的三条线所组成的串行数据接口就可以涵盖栅极驱动电路所有的输入，因此相比于现有技术而言本公开实施例还能够利用串行通信减少电路接口数量，有助于简化相关产品的内部构造。最后，由于栅极驱动电路能够灵活像素行进行数据刷新，而可以实现灵活的局部刷新或单行刷新，因而有助于降低输出扫描信号所带来的功耗，有助于提升相关产品的通用性和续航能力。
图6是本公开的一些实施例中一种栅极驱动电路的驱动方法的流程示意图，所述栅极驱动电路可以是上述任意一种的栅极驱动电路。参见图6，该驱动方法包括：
步骤601、在接收到第一帧的显示数据时，依次将包括每一所述扫描输出端的地址数据的数据帧发送至所述栅极驱动电路。
步骤602、在接收到第一帧的显示数据之后的任一帧的显示数据时，通过比较当前帧的显示数据与上一帧的显示数据确定刷新扫描输出端，并分别在与每个所述刷新扫描输出端对应的时刻将包括该刷新扫描输出端的地址数据的数据帧发送至所述栅极驱动电路。
所述刷新扫描输出端是在将上一帧的显示数据所对应的显示画面刷新为当前帧的显示数据所对应的显示画面时，所述若干个扫描输出端中需要输出扫描信号的扫描输出端。
在一个示例中，当接收到第一帧画面的显示数据时，可以通过控制上述任意一种栅极驱动电路依次在每个扫描输出端处输出扫描信号，因而完成一整个显示区域的数据刷新；而在此后接收到任一帧画面的显示数据时，则可以仅刷新相比于上一帧而言有变化的部分——可以通过比较显示数据来确定出有哪些扫描输出端所对应的像素行有显示数据的变化，从而可以这些扫描输出端以外的扫描输出端所对应的刷新时段内暂停栅极驱动器的输出，而仅在这些所对应的像素行有显示数据的变化的扫描输出端所对应的刷新时段内 通过控制栅极驱动电路适应性地输出扫描信号。如此，可以省去画面数据没有变化的像素行的刷新过程，节省整体功耗。
图7是本公开的一些实施例中一种串行数据接口的数据发送状态变化图。参见图7，对应于上述栅极驱动电路的工作原理以及电路时序，串行数据接口的数据发送状态可以在如图7所示的那样按照“空闲”、“接收数据”(获取所要发送的数据)、“缓存数据”、“等待数据”(等待到需要发送的时刻)、“序列化”(转换为串行数据)、“发送数据”、“空闲”……的顺序循环执行，如此可以配合上述任意一种栅极驱动电路来实现灵活像素行进行数据刷新的效果。
本公开的又一实施例提供了一种显示装置，该显示装置包括至少一个上述任意一种的栅极驱动电路。
例如，显示装置还可以包括控制器。控制器被配置为接收显示图像(也即，当前显示图像)，获取显示图像与前一帧显示图像的差异，并基于差异生成至少一个数据帧。例如，可以将黑画面作为第零帧显示图像，在控制器接收第一帧显示图像时，控制器可以获取第一帧显示图像和黑画面的差异，并基于第一帧显示图像和黑画面的差异生成至少一个数据帧(例如，J个数据帧)。例如，控制器生成J个数据帧表明为显示当前显示图像，栅极驱动电路需要向J根栅线提供扫描信号(有效信号)，以使得显示面板的J行像素能够被刷新。
例如，在显示装置的至少一个示例中，控制器还被配置为使得至少一个数据帧的每个为串行的数据帧，由此栅极驱动电路可以接收串行的数据帧。
例如，控制器可以包括处理器和存储器，该处理器例如是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理单元，例如，该处理器可以实现为通用处理器，并且也为单片机、微处理器、数字信号处理器、专用的图像处理芯片、或现场可编程逻辑阵列等。存储器例如可以包括易失性存储器和/或非易失性存储器，例如可以包括只读存储器(ROM)、硬盘、闪存等。相应地，该存储器可以实现为一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，在所述计算机可读存储介质上可以存储一个或多个计算机程序指令。处理器可以运行所述程序指令，以实现下文所述的本公开实施例中控制装置的功能以及/或者其它期望的功能。该存储器还可以存储其他各种应用程序和各种数 据，以及所述应用程序使用和/或产生的各种数据等。
本公开实施例中的显示装置可以为：显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。基于栅极驱动电路所能取得的有益效果，该显示装置也能取得相同或相应的有益效果。
图8是本公开的一些实施例提供的显示装置的示例性框图，下面结合图8对本公开的一些实施例提供的显示装置做示例性说明。
如图8所示，显示装置60包括显示面板6000、栅极驱动器6010、定时控制器6020和数据驱动器6030。显示面板6000包括根据多条扫描线GL和多条数据线DL交叉限定的多个像素单元P。
例如，栅极驱动器6010包括上述任一实施例中提供的栅极驱动电路，栅极驱动器6010包括多个输出端，且栅极驱动器6010的多个输出端分别与多条扫描线GL，以使得栅极驱动器6010可用于驱动多条扫描线GL。
例如，数据驱动器6030用于驱动多条数据线DL。例如，定时控制器6020用于处理从显示装置60外部输入的图像数据RGB，向数据驱动器6030提供处理的图像数据RGB以及向栅极驱动器6010和数据驱动器6030分别输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器6010和数据驱动器6030进行控制。
例如，显示装置还可以包括控制器，控制器例如可以实现为定时控制器6020或者位于定时控制器6020中。例如，定时控制器6020可以与串行数据线SD、串行时钟信号线SCLK和接收使能信号线SCS相连，以分别经由串行数据线SD、串行时钟信号线SCLK和接收使能信号线SCS向栅极驱动器6010提供数据帧、时钟信号和使能信号。虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开的实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (28)

  1. 一种栅极驱动电路，包括：若干个扫描输出端和译码器电路，
    其中，所述译码器电路包括多个输入端和多个输出端，所述译码器电路的多个输出端与所述若干个扫描输出端一一对应；
    所述译码器电路的多个输入端被配置为接收并行的数据帧；
    所述译码器电路配置在接收到所述并行的数据帧时，在所述译码器电路的、与所述并行的数据帧对应的输出端处输出用于生成扫描信号的触发信号，以使得与所述并行的数据帧对应的扫描输出端处输出所述扫描信号。
  2. 根据权利要求1所述的栅极驱动电路，还包括：
    串并转换电路，其中，所述串并转换电路用于接收串行的数据帧，并将所述串行的数据帧转换为所述并行的数据帧；以及，
    与所述串并转换电路相连的锁存器电路，其中，所述锁存器电路用于接收并存储所述并行的数据帧，并在所述数据帧接收完成时将所述并行的数据帧输出，
    其中，所述译码器电路与所述锁存器电路相连，以接收所述锁存器电路输出的所述并行的数据帧，所述译码器电路用于在接收到所述锁存器电路输出的数据帧时，在所述译码器电路的、与所述并行的数据帧对应的输出端处输出所述用于生成所述扫描信号的触发信号。
  3. 根据权利要求1或2所述的栅极驱动电路，其中，所述译码器电路包括地址译码器，所述并行的数据帧包括并行的地址数据；
    所述地址译码器包括多个输入端和多个输出端；
    所述地址译码器的多个输入端的每个被配置为接收所述并行的地址数据中的一位；
    所述地址译码器被配置为在接收到所述并行的地址数据之后，经由所述地址译码器的、与所述并行的地址数据相对应的输出端输出所述用于生成所述扫描信号的触发信号。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述地址译码器为m-n译码器；以及
    m等于所述地址译码器的输入端的个数，n等于所述地址译码器的输出端的个数。
  5. 根据权利要4所述的栅极驱动电路，其中，所述m-n译码器包括至少一个二四译码器。
  6. 根据权利要求3-5任一所述的栅极驱动电路，其中，所述译码器电路还包括模式译码器；
    所述并行的数据帧还包括并行的模式数据，所述并行的模式数据与所述并行的地址数据在所述并行的数据帧中彼此并列；以及
    所述模式译码器被配置为在所述并行的模式数据对应于全关模式时，使得所述译码器的所有的输出端均不输出所述用于生成所述扫描信号的触发信号或均输出所述用于生成所述扫描信号的触发信号。
  7. 根据权利要求6所述的栅极驱动电路，其中，所述模式译码器包括全关译码器；以及
    所述全关译码器被配置为在所述并行的模式数据对应于全关模式时，向所述地址译码器的使能端提供无效信号，以使得所述译码器的所有的输出端均不输出所述用于生成所述扫描信号的触发信号。
  8. 根据权利要求7所述的栅极驱动电路，其中，所述全关译码器包括第一与门；
    所述并行的模式数据包括第一位数据和第二位数据；
    所述第一与门的第一输入端被配置为接收与所述第一位数据反相的数据；
    所述第一与门的第二输入端被配置为接收所述第二位数据；以及
    所述第一与门的输出端被配置为与所述地址译码器的使能端相连。
  9. 根据权利要求6-8所述的栅极驱动电路，其中，所述模式译码器包括全开译码器；
    所述全开译码器被配置为在所述并行的模式数据对应于全开模式时，使得所述译码器的所有的输出端输出均输出所述用于生成所述扫描信号的触发信号。
  10. 根据权利要求9所述的栅极驱动电路，其中，所述全开译码器包括第二与门以及多个或门；
    所述并行的模式数据包括第一位数据和第二位数据；
    所述第二与门的第一输入端被配置为接收所述第一位数据；
    所述第二与门的第二输入端被配置为接收所述第二位数据；
    所述第二与门的输出端被配置为与所述多个或门中的每个或门的第一输入端相连；
    所述多个或门的第二输入端分别与所述地址译码器的多个输出端相连。
  11. 根据权利要求3-10任一所述的栅极驱动电路，还包括电平转换电路，其中，所述电平转换电路被配置为接收所述用于生成扫描信号的触发信号，将所述用于生成扫描信号的触发信号转换为所述扫描信号，以及使得所述扫描信号经由与所述并行的数据帧对应的扫描输出端输出。
  12. 根据权利要求2-11任一所述的栅极驱动电路，还包括串行数据接口，其中，所述串并转换电路与所述串行数据接口相连，以经由所述串行数据接口接收所述串行的数据帧。
  13. 根据权利要求12所述的栅极驱动电路，其中，所述串行数据接口包括串行数据线和串行时钟信号线；
    所述串行数据线和所述串行时钟信号线均与所述串并转换电路相连；以及
    所述串并转换电路用于在每次所述串行时钟信号线上的电信号满足触发条件时读取所述串行数据线上的一位数据。
  14. 根据权利要求2-13任一所述的栅极驱动电路，其中，所述串并转换电路包括至少两级触发器；
    所述至少两级触发器的触发输入端均与所述串行时钟信号线相连，每级所述触发器输出所述并行的数据帧的一位数据；以及
    第一级所述触发器的输入端与所述串行数据线相连，除第一级以外的任意一级所述触发器的输入端与上一级所述触发器的输出端相连。
  15. 根据权利要求14所述的栅极驱动电路，其中，所述至少两级触发器的每个为D触发器。
  16. 根据权利要求12-15任一所述的栅极驱动电路，其中，所述串行数据接口还包括与所述锁存器电路电连接的接收使能信号线，
    所述锁存器电路用于在所述接收使能信号线上的电信号由有效电平转为无效电平时将所述并行的数据帧输出。
  17. 根据权利要求2-16任一所述的栅极驱动电路，其中，所述锁存器电路包括至少两个边沿触发器，
    所述至少两个边沿触发器的触发输入端均与所述接收使能信号线电连接，每个所述边沿触发器的输入端接收所述并行的数据帧的一位数据，每个所述边沿触发器的输出端可输出所述并行的数据帧的一位数据。
  18. 根据权利要求17所述的栅极驱动电路，其中，所述至少两个边沿触发器的每个为D触发器。
  19. 根据权利要求16-18任一所述的栅极驱动电路，还包括反相器，
    其中，所述反相器包括输入端和输出端；
    所述反相器的输入端与所述接收使能信号线相连，以接收所述接收使能信号线上的电信号；
    所述反相器被配置为将接收到的所述接收使能信号线上的电信号反相后从所述反相器的输出端输出；以及
    所述反相器的输出端与所述至少两个边沿触发器的每个的触发输入端相连。
  20. 根据权利要求12所述的栅极驱动电路，其中，所述串口数据接口为串行外设接口SPI的串行总线接口，所述数据帧包括地址数据和模式数据，所述译码器电路包括地址译码器、模式译码器和若干个电平转换器；其中，
    所述地址译码器以二四译码器为最小组成单元，用于在接收到所述锁存器电路输出的数据帧中的所述地址数据时，向与所述数据帧中的地址数据相对应的电平转换器输出触发信号；
    每个所述电平转换器与一个所述扫描输出端相连，可用于在接收到所述地址译码器输出的所述触发信号时，在与所述每个所述电平转换器连接的扫描输出端处输出所述扫描信号；
    所述模式译码器用于在接收到所述锁存器电路输出的数据帧中的所述模式数据且所述模式数据所对应的工作模式为全开模式时，使得所述若干个扫描输出端均输出栅极有效电平电压，以使得所述若干个扫描输出端均输出所述扫描信号；以及
    所述模式译码器用于在接收到所述锁存器电路输出的数据帧中的所述模式数据且所述模式数据所对应的工作模式为全关模式时，使得所述若干个扫描输出端均输出栅极无效电平电压，以使得所述若干个扫描输出端均不输出所述扫描信号。
  21. 根据权利要求1或2所述的栅极驱动电路，其中，所述数据帧包括地址数据；以及
    所述译码器电路被配置为在所述译码器电路的、与所述地址数据对应的输出端处输出所述用于生成所述扫描信号的触发信号。
  22. 根据权利要求21所述的栅极驱动电路，其中，所述数据帧还包括模式数据；
    所述译码器电路用于在接收到所述并行的数据帧时，根据所述数据帧中的模式数据确定当前的工作模式，所述当前的工作模式包括一般模式；
    在所述当前的工作模式为一般模式时，所述译码器电路被配置为在所述译码器电路的、与所述数据帧中的地址数据相对应的输出端处输出所述用于生成所述扫描信号的触发信号。
  23. 根据权利要求22所述的栅极驱动电路，其中，所述当前的工作模式还包括全开模式；
    在所述当前的工作模式为所述全开模式时，所述译码器电路被配置为使得所述若干个扫描输出端处同时输出栅极有效电平电压，以使得所述若干个扫描输出端均输出所述扫描信号。
  24. 根据权利要求22或23所述的栅极驱动电路，其中，所述当前的工作模式还包括全关模式；以及
    在所述当前的工作模式为全关模式时，所述译码器电路被配置为使得所述若干个扫描输出端处同时输出栅极无效电平电压，以使得所述若干个扫描输出端均不输出所述扫描信号。
  25. 一种显示装置，包括至少一个如权利要求1至24中任一项所述的栅极驱动电路。
  26. 根据权利要求25所述的显示装置，还包括控制器，其中，所述控制器被配置为接收显示图像，获取所述显示图像与前一帧显示图像的差异，并基于所述差异生成至少一个数据帧。
  27. 根据权利要求26所述的显示装置，其中，所述控制器还被配置为使得所述至少一个数据帧的每个为串行的数据帧。
  28. 一种如权利要求1至24中任一项所述的栅极驱动电路的驱动方法，包括：
    在接收到第一帧的显示数据时，依次将包括每一所述扫描输出端的地址数据的数据帧发送至所述栅极驱动电路；
    在接收到所述第一帧的显示数据之后的任一帧的显示数据时，通过比较当前帧的显示数据与上一帧的显示数据确定刷新扫描输出端，并分别在与每个所述刷新扫描输出端对应的时刻将包括该刷新扫描输出端的地址数据的数据帧发送至所述栅极驱动电路，其中，所述刷新扫描输出端是在将所述上一帧的显示数据所对应的显示画面刷新为所述当前帧的显示数据所对应的显示画面时，所述若干个扫描输出端中需要输出扫描信号的扫描输出端。
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