WO2019157863A1 - 移位寄存器、栅极驱动电路、显示装置以及驱动方法 - Google Patents

移位寄存器、栅极驱动电路、显示装置以及驱动方法 Download PDF

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Publication number
WO2019157863A1
WO2019157863A1 PCT/CN2018/122801 CN2018122801W WO2019157863A1 WO 2019157863 A1 WO2019157863 A1 WO 2019157863A1 CN 2018122801 W CN2018122801 W CN 2018122801W WO 2019157863 A1 WO2019157863 A1 WO 2019157863A1
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Prior art keywords
pull
transistor
blanking
output
input
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PCT/CN2018/122801
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/478,366 priority Critical patent/US11475824B2/en
Priority to EP18899020.4A priority patent/EP3754645A4/en
Publication of WO2019157863A1 publication Critical patent/WO2019157863A1/zh
Priority to US17/844,899 priority patent/US11688326B2/en
Priority to US18/306,723 priority patent/US12118915B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the gate drive circuit is currently integrated in the gate integrated circuit (GATE IC).
  • GATE IC gate integrated circuit
  • the area of the chip in the IC design is the main factor affecting the cost of the chip, how to effectively reduce it. Chip area is a key consideration for technology developers.
  • an OLED gate drive circuit is usually composed of three sub-circuits, that is, a sense unit, a scan unit, and a connection unit (or a gate circuit or a Hiz circuit) that outputs a composite pulse.
  • the structure is very complicated and cannot meet the requirements of high-resolution narrow borders.
  • a shift register comprising: a first input sub-circuit configured to receive a first input signal from a first input and output a blanking output control signal; a second input sub-circuit, configured Receiving a second input signal from the second input terminal and outputting the display output control signal; the output sub-circuit is configured to output a composite output signal via the output terminal under control of the first node, the composite output signal being independent of each other The display output signal outputted during the display period and the blanking output signal output during the blanking period.
  • the shift register further includes: a blanking reset sub-circuit configured to, prior to the end of the blanking period of one frame, the first node and/or under the control of a blanking reset control signal The output is reset.
  • the output subcircuit includes at least one shift signal output and at least one pixel signal output.
  • the charging sub-circuit includes a charging transistor, a first pole and/or a control pole of the charging transistor is coupled to the first input terminal, and a second pole of the charging transistor is coupled to the blanking pull-up control node;
  • the storage subcircuit includes a first capacitor, a first end of the first capacitor is coupled to the blanking pull-up control node;
  • the isolation sub-circuit includes a first isolation transistor and a second isolation transistor, wherein the first a control terminal of the isolation transistor is connected to the blanking pull-up control node, a first electrode of the second isolation transistor is connected to a second electrode of the first isolation transistor, and a second electrode of the second isolation transistor is connected to the The first node, the control electrode of the second isolation transistor is connected to the isolation control signal line.
  • the second input sub-circuit includes a first display input transistor, a first pole of the first display input transistor is coupled to the first node, and a second pole of the first display input transistor And/or a control electrode is connected to the second input end;
  • the output sub-circuit includes an output transistor and an output capacitor, wherein a first pole of the output transistor is connected to an output clock signal line, and a second pole of the output transistor is connected to an output end
  • the control electrode of the output transistor is connected to the first node, the first end of the output capacitor is connected to the first node, and the second end of the output capacitor is connected to the output end.
  • the second input sub-circuit further includes a second display input transistor, the first pole of the second display input transistor being coupled to the control electrode, and coupled to the first of the first display input transistors a second pole of the second display input transistor is coupled to the first node.
  • the display reset sub-circuit includes a display reset transistor, a first pole of the display reset transistor is connected to the first node, and a gate of the display reset transistor is connected to display a reset control terminal, the display The second pole of the reset transistor is connected to display a reset signal line.
  • the blanking reset subcircuit includes a first blanking reset transistor, a first pole of the first blanking reset transistor is coupled to the first node, and the first blanking reset transistor is controlled The pole is connected to the blanking reset control terminal, and the second pole of the first blanking reset transistor is connected to the blanking reset signal line.
  • the pull-down control sub-circuit includes a first pull-down control transistor and a second pull-down control transistor, wherein the first pole of the first pull-down control transistor is connected to the control electrode and connected to the pull-down control signal line a second pole of the first pull-down control transistor is connected to the pull-down node, a first pole of the second pull-down control transistor is connected to the pull-down node, and a control pole of the second pull-down control transistor is connected to the first node, a second pole of the second pull-down control transistor is connected to the pull-down signal line;
  • the pull-down sub-circuit includes a first pull-down transistor and a second pull-down transistor, wherein a first pole of the first pull-down transistor is connected to the first a node, a control pole of the first pull-down transistor is connected to the pull-down node, a second pole of the first pull-down transistor is connected to a pull-down signal line, and a first pole of the second pull-down transistor is connected to
  • the shift register further includes: a leakproof electronic circuit configured to input an operating potential to the control under the control of the first node and/or the blanking pull-up control node A first pole and/or a second pole of the second isolation transistor.
  • a gate driving circuit including a cascaded N-row shift register, the shift register being a shift register as described above, wherein the shift of the i-th stage The second input end and the first input end of the register are connected to the output end of the shift register of the i-1th stage, and the output end of the shift register of the i-th stage and the display reset end of the shift register of the i-1th stage Connection, where N is an integer greater than 2, 1 ⁇ i ⁇ N; the second input of the shift register of the first stage is connected to the display signal line, the first input is connected to the blanking signal line; the shift of the Nth stage The display reset control terminal of the bit register is connected to the display reset signal line.
  • a display device comprising a gate drive circuit as previously described.
  • a driving method applied to a shift register as described above comprising: displaying a display via a second input sub-circuit through a display period of one frame, including a first control phase a control signal is input to the first node; a first output stage outputs a first output signal via the output sub-circuit under control of the first node; a blanking period of one frame, including a second control phase, via the first input
  • the sub-circuit inputs a blanking output control signal to the first node; a second output stage.
  • a second output signal is output via the output sub-circuit under the control of the first node.
  • the driving method further includes: displaying a reset phase, resetting the first node under control of displaying a reset control signal.
  • the driving method further includes: a blanking reset phase to reset the first node under control of a blanking reset control signal.
  • FIG. 1 shows a schematic block diagram of a structure of a shift register for an OLED panel according to the prior art
  • FIG. 3a illustrates an exemplary circuit configuration 1 of an input sub-circuit in accordance with an embodiment of the present disclosure
  • FIG. 3b illustrates an exemplary circuit configuration 2 of a display input subcircuit in accordance with an embodiment of the present disclosure
  • FIG. 3c illustrates an exemplary circuit configuration 3 of a display input subcircuit in accordance with an embodiment of the present disclosure
  • FIG. 3d illustrates an exemplary circuit structure 4 of a display input subcircuit in accordance with an embodiment of the present disclosure
  • FIG. 3e illustrates an exemplary circuit configuration 5 of an input sub-circuit in accordance with an embodiment of the present disclosure
  • Figure 3f shows a schematic simulation of the potential at the output OUT and the first pull-up node Q according to the prior art
  • FIG. 3g shows a simulated schematic diagram of the potential at the output terminal OUT and the first pull-up node Q, in accordance with an embodiment of the present disclosure
  • FIG. 4a illustrates an exemplary circuit configuration 1 of an output subcircuit in accordance with an embodiment of the present disclosure
  • 4b illustrates an exemplary circuit configuration 2 of an output subcircuit in accordance with an embodiment of the present disclosure
  • 4c illustrates an exemplary circuit configuration three of an output subcircuit in accordance with an embodiment of the present disclosure
  • FIG. 6a illustrates an exemplary circuit configuration 1 of a blanking input sub-circuit in accordance with an embodiment of the present disclosure
  • FIG. 6b illustrates an exemplary circuit configuration 2 of a blanking input sub-circuit in accordance with an embodiment of the present disclosure
  • FIG. 6c illustrates an exemplary circuit configuration three of a blanking input subcircuit in accordance with an embodiment of the present disclosure
  • FIG. 6d illustrates an exemplary circuit configuration 4 of a blanking input subcircuit in accordance with an embodiment of the present disclosure
  • FIG. 6e illustrates an exemplary circuit configuration 5 of a blanking input subcircuit in accordance with an embodiment of the present disclosure
  • FIG. 6f illustrates an exemplary circuit structure 6 of a blanking input sub-circuit in accordance with an embodiment of the present disclosure
  • FIG. 7 illustrates still another schematic block diagram of a structure of a shift register according to an embodiment of the present disclosure
  • FIG. 8 illustrates an exemplary circuit configuration 1 of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 9 illustrates an exemplary circuit configuration 2 of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 11 illustrates an exemplary circuit configuration 4 of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 12 shows a schematic block diagram of a gate driving circuit in accordance with an embodiment of the present disclosure
  • FIG. 13 illustrates an exemplary circuit structure of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 14a illustrates a driving timing diagram of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 14b illustrates a driving timing diagram 1 of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 14c illustrates a driving timing diagram 2 of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 15 illustrates a driving timing chart of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 16 illustrates another schematic block diagram of a gate driving circuit in accordance with an embodiment of the present disclosure
  • FIG. 17 illustrates a driving timing chart of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 18 shows still another schematic block diagram of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 19 illustrates a driving timing diagram of a gate driving circuit according to an embodiment of the present disclosure
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the connection modes of the drain and the source of each transistor are interchangeable. Therefore, the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the thin film transistor used in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor. In an embodiment of the present disclosure, when an N-type thin film transistor is employed, its first electrode may be a source and the second electrode may be a drain.
  • a thin film transistor is an N-type transistor
  • the thin film transistor is turned on. It is conceivable that when a P-type transistor is used, the timing of the drive signal needs to be adjusted accordingly.
  • the details are not described herein, but should also be within the scope of the present invention.
  • FIG. 1 shows a schematic block diagram of the structure of a shift register for an OLED panel according to the prior art.
  • the above shift register has a drawback of being oversized.
  • a shift register provided according to an embodiment of the present disclosure will be described below.
  • the first input sub-circuit is configured to receive the first input signal from the first input and to input the blanking output control signal to the first node in a blanking period of one frame in accordance with the first input signal.
  • the second input sub-circuit is configured to receive the second input signal from the second input and to input the display output control signal to the first node according to the second input signal during a display period of one frame.
  • the "blanking" in the blanking input sub-circuit in the present disclosure merely indicates that the circuit is related to the blanking period, and does not limit the circuit to operate only in the blanking period.
  • the following embodiments are the same, no longer Narration.
  • the blanking input sub-circuit can charge the blanking pull-up control node H, which will be mentioned later, during the display period, and keep the high level of the blanking pull-up control node H to the blanking period.
  • the blanking input sub-circuit can charge the first pull-up node Q to be at a high level during the blanking period.
  • the blanking input sub-circuit 210 is configured to receive a first input signal (hereinafter also referred to as a “blanking input signal” from a first input (hereinafter also referred to as a “blanking input”). "), and a blanking output control signal (hereinafter also referred to as a “blanking pull-up signal”) is input to the first pull-up node Q in a blanking period of one frame.
  • a first input signal hereinafter also referred to as a "blanking input signal” from a first input (hereinafter also referred to as a “blanking input”).
  • a blanking output control signal hereinafter also referred to as a "blanking pull-up signal”
  • the blanking input sub-circuit 210 can be configured to receive and store the blanking input signal and output a blanking pull-up signal to the first pull-up node Q according to the blanking input signal during a blanking period of one frame. Thus, the potential of the first pull-up node Q is pulled up to the operating potential.
  • the blanking input sub-circuit 210 may receive the blanking input signal during a blanking period of one frame and store the blanking pull-up control signal, and according to the blanking pull-up control signal during the blanking period of the next frame A pull-up node Q outputs a blanking pull-up signal to pull up the potential of the first pull-up node Q to the operating potential.
  • the output sub-circuit 230 is configured to output a composite output signal via the output under the control of the first pull-up node Q.
  • the composite output signal can include a display output signal and a blanking output signal, wherein the display output signal and the blanking output signal can be two waveforms that are independent of each other having different widths and timings.
  • FIG. 3a-3e illustrate an exemplary circuit structure of display input subcircuit 220, in accordance with an embodiment of the present disclosure.
  • display input sub-circuit 220 can have a variety of different connection configurations and control methods.
  • display input subcircuit 220 can include display input transistor M5. As shown in FIG. 3a, the first electrode of the display input transistor M5 is connected to the display input terminal STU2, the second electrode of the display input transistor M5 is connected to the first pull-up node Q, and the control electrode of the display input transistor M5 is connected to the A clock signal line CLKA. In some embodiments, during display of one frame, under the control of the first clock signal input by the first clock signal line CLKA, the display input transistor M5 will be turned on, and the display input signal input to the display input terminal STU2 is used as The pull-up signal is input to the first pull-up node Q.
  • the first pole of the display input transistor M5 is connected to the control pole and is connected to the display input terminal STU2, and the second pole of the display input transistor M5 is connected to the first pull-up node Q.
  • the display input transistor M5 during display of one frame, under the control of the display input signal input by the display input STU2, the display input transistor M5 will be turned on, and at the same time, the display input signal input to the input signal line STU2 is displayed as a display.
  • the pull-up signal is input to the first pull-up node Q.
  • Figure 3f shows a simulated schematic of the burr at the output.
  • the output terminal OUT may be large due to capacitive coupling in the circuit.
  • the glitch such a glitch may cause the row shift register to output an erroneous output signal, causing the shift register to malfunction.
  • Figure 3g shows a schematic representation of the simulation of the improved output.
  • the display sub-circuit 220 further includes the second display input transistor M16
  • the high-level signal of the VDD input does not directly pull up the first pull-up node Q, but realizes the first pull-up through the second display input transistor M16 connected in series.
  • the potential of the node Q is pulled up, thereby alleviating the coupling effect of the capacitance in the circuit and thereby reducing the glitch at the output terminal OUT.
  • 4a-4c illustrate an exemplary circuit structure of output sub-circuit 230 in accordance with an embodiment of the present disclosure.
  • the output sub-circuit 230 can include an output transistor M11 and an output capacitor C2.
  • the first pole of the output transistor M11 is connected to the fourth clock signal line CLKD
  • the second pole of the output transistor M11 is connected to the output terminal CR/OUT
  • the gate of the output transistor M11 is connected to the first pull-up node Q.
  • the first end of the output capacitor is connected to the first pull-up node Q
  • the second end of the output capacitor is connected to the output terminal CR/OUT.
  • the output capacitor C2 is used to store and maintain the potential of the first pull-up node Q.
  • the output sub-circuit 230 can further include two outputs.
  • the output sub-circuit 230 may include a first output transistor M11 and a second output transistor M13.
  • the first electrode of the first output transistor M11 is connected to the fourth clock signal line CLKD
  • the second electrode of the first output transistor M11 is connected to the first output terminal CR
  • the control electrode of the first output transistor M11 is connected to the first pull-up node Q.
  • the first electrode of the second output transistor M13 is connected to the fifth clock signal line CLKE, the second electrode of the second output transistor M13 is connected to the second output terminal OUT1, and the control electrode of the second output transistor M13 is connected to the first pull-up node Q.
  • the signal output from the first output terminal CR may be used as a shift driving signal of the gate driving circuit, and the signal output from the second output terminal OUT1 may be used as a driving signal of the pixel circuit.
  • the fourth clock signal line CLKD and the fifth clock signal line CLKE may be different clock signal lines or the same clock signal line.
  • output sub-circuit 230 can further include a plurality of outputs.
  • the output sub-circuit 230 further includes a third output transistor M15, the first electrode of the third output transistor M15 is connected to the sixth clock signal line CLKF, and the second electrode of the third output transistor M15 is connected to the third output.
  • the terminal OUT2, the control electrode of the third output transistor M15 is connected to the first pull-up node Q.
  • the sixth clock signal line CLKF may be the same clock signal line as the fourth clock signal line CLKD and the fifth clock signal line CLKE, or may be a clock signal line different therefrom.
  • FIG. 5 shows a schematic block diagram of another structure of a shift register in accordance with an embodiment of the present disclosure.
  • the shift register 400 includes a blanking input sub-circuit 410, a display input sub-circuit 420, and an output sub-circuit 430.
  • the display input sub-circuit 420 and the output sub-circuit 430 may be the display input sub-circuit 220 and the output sub-circuit 230 and their variants as shown in FIG. 2, FIG. 3a to FIG. 3g, and details are not described herein again.
  • the charging sub-circuit 411 is configured to charge the blanking pull-up control node H according to the blanking input signal.
  • the charging sub-circuit 411 can receive the blanking input signal and input a high level blanking pull-up control signal to the blanking pull-up control node H under the control of the blanking input signal.
  • One end of the storage sub-circuit 412 is connected to the blanking pull-up control node H, and is configured to store a blanking pull-up control signal.
  • the first pull-up node Q can be separately controlled by the blanking input sub-circuit and the display input sub-circuit at different time periods, thereby realizing that the blanking input sub-circuit and the display input sub-circuit share the same
  • the output unit implements the output of the composite output signal.
  • FIG. 6a-6f illustrate an exemplary circuit structure of a blanking input subcircuit in accordance with an embodiment of the present disclosure.
  • the blanking input sub-circuit 410 can have a variety of different connection configurations and control methods.
  • the charging sub-circuit 411 can be configured to input a blanking input signal to the blanking pull-up control node H.
  • the first pole of the charging transistor M1 is connected to the blanking input terminal STU1
  • the second pole of the charging transistor M1 is connected to the blanking pull-up control node H.
  • the control electrode of the charging transistor M1 is connected to the second clock signal line CLKB. Wherein, when the second clock signal line CLKB inputs a high-level on-signal, the charging transistor M1 is turned on under the control of the second clock signal input by the second clock signal line CLKB, and inputs the blanking input terminal STU1.
  • the blanking input signal is input to the blanking pull-up control node H.
  • the control electrode of the charging transistor M1 is connected to the first pole and is connected to the blanking input signal line STU1, and the second pole of the charging transistor M1 is connected to the blanking pull-up control node H.
  • the charging transistor M1 is turned on under the control of the on-signal, and inputs the blanking input signal input to the blanking input terminal STU1 to the blanking pull-up. Control node H.
  • the charging transistor M1 when the blanking input terminal STU1 inputs a high-level turn-on signal, the charging transistor M1 is turned on under the control of the blanking input signal input by the blanking input terminal STU1, and the high-level signal of the VDD input is taken as The implicit pull-up control signal is input to the blanking pull-up control node H.
  • the storage sub-circuit 412 can include a first capacitor C1 configured to store a blanking pull-up control signal.
  • One end of the first capacitor C1 is connected to the blanking pull-up control node H.
  • the first end of the first capacitor C1 is connected to the blanking pull-up control node H
  • the second end of the first capacitor C1 is connected to the first signal end VSS1.
  • VSS1 can input a low level signal.
  • the charging sub-circuit inputs the blanking pull-up control signal to the blanking pull-up control node H, the first capacitor can be charged and the position of the blanking pull-up control node H is maintained at a high level. .
  • the first capacitor C1 can also have other connections.
  • the first end of the first capacitor C1 is connected to the blanking pull-up control node H, and the second end of the first capacitor C1 is connected to one end of the isolation sub-circuit 413 (such as the third clock signal line). CLKC).
  • the first end of the first capacitor C1 is connected to the blanking pull-up control node H, and the second end of the first capacitor C1 is connected to a point in the isolation sub-circuit 413 (such as the first isolation transistor).
  • the isolation sub-circuit 413 may include a first isolation transistor M3 and a second isolation transistor M4. In some embodiments, the isolation sub-circuit 413 is configured to output a blanking pull-up signal to the first pull-up node Q under the control of the blanking pull-up control node.
  • the first electrode of the first isolation transistor M3 is connected to the third clock signal line CLKC
  • the second electrode of the first isolation transistor M3 is connected to the second isolation transistor M4.
  • the first pole, the control pole is connected to the blanking pull-up control node H.
  • the second electrode of the second isolation transistor M4 is connected to the first pull-up node Q
  • the second isolation transistor M4 is connected to the third clock signal line CLKC.
  • the second isolation transistor M4 When the third clock signal line CLKC inputs a high-level on-signal, the second isolation transistor M4 is turned on under the control of the on-signal, and the high-level signal input from the third clock signal line CLKC is used as blanking.
  • the pull signal is input to the first pull-up node Q.
  • the first electrode of the first isolation transistor M3 may be connected to the high level signal line VDD.
  • the first isolation transistor M3 is turned on under the control of the blanking pull-up control node H.
  • the third clock signal line CLKC inputs a high-level on-signal
  • the second isolation transistor M4 is turned on under the control of the on-signal, and the high-level signal input from the high-level signal line VDD is used as blanking.
  • the pull signal is input to the first pull-up node Q.
  • the isolation sub-circuit 413 includes a first isolation transistor M3, the first electrode of the first isolation transistor M3 is connected to the blanking pull-up control node H, and the second electrode of the first isolation transistor M3 is connected to the first Pulling the node Q, the control electrode is connected to the third clock signal line CLKC.
  • the third clock signal line CLKC inputs a high-level turn-on signal
  • the first isolation transistor M3 is turned on under the control of the on-signal, and the high-level blanking stored at the blanking pull-up control node H is blanked.
  • the pull-up control signal is input to the first pull-up node Q as a blanking pull-up signal.
  • FIG. 7 shows a schematic block diagram of still another structure of a shift register according to an embodiment of the present disclosure.
  • the shift register 400 may include a blanking input sub-circuit 410, a display input sub-circuit 420, an output sub-circuit 430, a pull-down control sub-circuit 440, a pull-down sub-circuit 450, a display reset sub-circuit 460, and a blanking reset.
  • Subcircuit 470 and initial reset subcircuit 480 may be included in the shift register 400.
  • the blanking input sub-circuit 410, the display input sub-circuit 420, and the output sub-circuit 430 may be the blanking input sub-circuit 210/310, the display input sub-circuit 220/320, and the output sub-circuit as shown in FIGS. 230/330 and its variants are not described here.
  • the shift register 400 can also include a pull-down control sub-circuit 440 configured to control the potential of the pull-down node QB in accordance with the first pull-up node Q.
  • a pull-down control sub-circuit 440 configured to control the potential of the pull-down node QB in accordance with the first pull-up node Q. For example, when the potential of the first pull-up node Q is at a high level, the pull-down control sub-circuit 440 can pull down the pull-down node QB to a low level under the control of the first pull-up node Q. For another example, when the potential of the first pull-up node Q is at a low level, the pull-down control sub-circuit 440 can pull up the pull-down node QB to a high level under the control of the first pull-up node Q.
  • the shift register 400 can also include a pull-down sub-circuit 450 configured to pull the first pull-up node Q and the output terminal OUT to a non-operating potential under the control of the pull-down node QB. For example, when the output terminal OUT does not output a signal, the first pull-up node Q and the output terminal OUT can be pulled down to a non-operating potential by controlling the potential of the pull-down node QB, thereby reducing the noise at the output terminal of the shift register circuit.
  • a pull-down sub-circuit 450 configured to pull the first pull-up node Q and the output terminal OUT to a non-operating potential under the control of the pull-down node QB.
  • shift register 400 can also include a display reset sub-circuit 460 configured to reset the first pull-up node Q under control of displaying a reset control signal.
  • the display reset control circuit 460 can receive the display reset control signal, thereby the first pull-up node The potential of Q is pulled low.
  • shift register 400 can also include an initial reset sub-circuit 480 configured to receive an initial reset control signal and reset the blanking pull-up control node H before shift register 400 begins to operate.
  • initial reset sub-circuit 480 configured to receive an initial reset control signal and reset the blanking pull-up control node H before shift register 400 begins to operate.
  • the shift register of FIG. 7 shows the pull-down control sub-circuit 440, the pull-down sub-circuit 450, the display reset sub-circuit 460, the blanking reset sub-circuit 470, and the initial reset sub-circuit 480
  • the examples do not limit the scope of protection of the present disclosure.
  • the technician may choose to use or not use one or more of the above sub-circuits according to the situation, and various combinations of the foregoing sub-circuits are not deviated from the principles of the present disclosure, and thus will not be described again. .
  • the first pull-up node Q can be separately controlled by the blanking input sub-circuit and the display input sub-circuit at different time periods, thereby realizing that the blanking input sub-circuit and the display input sub-circuit share the same output.
  • the unit implements the output of the composite output signal. Also, by controlling the potential of the output terminal and the pull-up node during the non-output period, the noise of the shift register can be reduced.
  • FIG. 8 illustrates an exemplary circuit structure of a shift register in accordance with an embodiment of the present disclosure.
  • the blanking input sub-circuit 410, the display input sub-circuit 420, and the output sub-circuit 430 shown in FIG. 8 and the blanking input sub-circuit, the display input sub-circuit, and the output sub-circuit shown in FIGS. 2-5 are The same, will not be described here.
  • the fourth signal terminal VSS4 can input a low-level non-conduction signal.
  • the second pull-down control transistor M8 When the first pull-up node Q is at a high level, the second pull-down control transistor M8 will be turned on under the control of the first pull-up node Q, by designing the trench of the first pull-down control transistor M7 and the second pull-down control transistor M8.
  • the channel width to length ratio can pull the potential of the pull-down node QB to a low level.
  • the second pull-down control transistor M8 will be turned off under the control of the first pull-up node Q. At this time, the high level signal input from the seventh clock signal line CLKM is input to the pull-down node QB, and the potential of the pull-down node QB is pulled up to the high level.
  • the pull-down control sub-circuit 440 may further include a third pull-down control transistor M10, the control electrode of the third pull-down control transistor M10 is connected to the first pole, and is connected to the eighth clock signal line. CLKN, the second pole of the third pull-down control transistor M10 is connected to the pull-down node QB. It can be seen that the third pull-down control transistor M10 and the first pull-down control transistor M7 have the same structure.
  • the functions of the pull-down control sub-circuit 440 can be implemented alternately using the third pull-down control transistor M10 and the first pull-down control transistor M7.
  • the seventh clock signal line CLKM inputs a signal of a high level
  • the eighth clock signal line CLKN inputs a signal of a low level. Therefore, at this time, the first pull-down control transistor M7 is turned on, and the third pull-down control transistor M10 is turned off.
  • the seventh clock signal line CLKM inputs a signal of a low level
  • the eighth clock signal line CLKN inputs a signal of a high level. Therefore, at this time, the first pull-down control transistor M7 is turned off, and the third pull-down control transistor M10 is turned on.
  • the pull-down sub-circuit 450 may include a first pull-down transistor M9, a first pole of the first pull-down transistor M9 is connected to the first pull-up node Q, and a second pole of the first pull-down transistor M9 is connected to the third
  • the signal line VSS3 and the control electrode are connected to the pull-down node QB.
  • the third signal line VSS3 can input a low-level non-conduction signal.
  • the pull-down sub-circuit may also include more pull-down transistors accordingly.
  • the pull-down sub-circuit 450 may further include a third pull-down transistor M14_a.
  • the first pole of the third pull-down transistor M14_a is connected to the second output terminal OUT
  • the second pole of the third pull-down transistor M14_a is connected to the sixth signal line VSS6, and the gate of the third pull-down transistor M14_a is connected to the pull-down node QB.
  • the sixth signal line VSS6 can input a low-level non-conduction signal.
  • the display reset sub-circuit 460 may include a display reset transistor M6, the first pole of the display reset transistor M6 is connected to the first pull-up node Q, and the second pole of the reset transistor M6 is connected to the second signal line VSS2 for display.
  • the gate of the reset transistor M6 is connected to the display reset control terminal STD2.
  • the second signal line VSS2 can input a low-level non-conduction signal.
  • the blanking reset sub-circuit 470 may include a first blanking reset transistor M15.
  • the first pole of the first blanking reset transistor M15 is connected to the first pull-up node Q, and the first blanking reset transistor M15 is The second pole is connected to the seventh signal line VSS7, and the gate of the first blanking reset transistor M15 is connected to the blanking reset control terminal TRST2.
  • the seventh signal line VSS7 can input a low-level non-conduction signal.
  • the blanking reset control terminal TRST2 can input a high level on signal. At this time, the first blanking reset transistor M15 will be turned on, and the first pull-up node Q is pulled down to Low level.
  • the blanking reset sub-circuit 470 may further include a second blanking reset transistor M12_b.
  • the first pole of the second blanking reset transistor M12_b is connected to the first output terminal CR, and the second blanking reset transistor M12_b is The second pole is connected to the fifth signal line VSS5, and the gate of the second blanking reset transistor M12_b is connected to the blanking reset control terminal TRST2.
  • the blanking reset control terminal TRST2 inputs a high level on signal, the second blanking reset transistor M12_b will be turned on, and the first output terminal CR is pulled down to a low level.
  • the blanking reset sub-circuit 470 can also include more blanking reset transistors accordingly.
  • the blanking reset sub-circuit 470 may further include a third blanking reset transistor M14_b, the first pole of the third blanking reset transistor M14_b is connected to the second output terminal OUT, and the third blanking is performed.
  • the second electrode of the reset transistor M14_b is connected to the sixth signal line VSS6, and the gate of the third blanking reset transistor M14_b is connected to the blanking reset control terminal TRST2.
  • the blanking reset sub-circuit 470 can include more blanking reset transistors corresponding to the output and used to reset the output.
  • the initial reset sub-circuit 480 may include an initial reset transistor M2, the first end of the initial reset transistor M2 is connected to the blanking pull-up control node H, and the second pole of the initial reset transistor M2 is connected to the first signal line VSS1, The gate of the initial reset transistor M2 is connected to the initial reset control terminal TRST1.
  • the first signal line VSS1 can input a low-level non-conduction signal.
  • the line VSS7 may be the same signal line or a different signal line. As long as the function of the shift register as described above and the control mode of each transistor therein can be realized, those skilled in the art can arbitrarily set the above signal line according to actual conditions.
  • FIG. 9 illustrates an exemplary circuit structure of a shift register according to an embodiment of the present disclosure.
  • the pull-down control sub-circuit 440 may be an inverter having an input connected to the first pull-up node Q and an output connected to the pull-down node QB.
  • the first pull-up node Q When the first pull-up node Q is at a high level, the potential at the pull-down node QB can be controlled to a low level by using an inverter.
  • the first portion 450-1 of the pull-down sub-circuit can also be an inverter. When the pull-down node QB is at a high level, the potential at the first pull-up node Q can be controlled to a low level by an inverter.
  • FIG. 10 illustrates an exemplary circuit structure of a shift register according to an embodiment of the present disclosure.
  • the potential at the blanking pull-up control node H can be maintained by the first capacitor C1
  • the potential at the first pull-up node Q can be maintained by the output capacitor C2.
  • the potential of the first pull-up node Q and/or the blanking pull-up control node H is maintained at a high level, there are some transistors whose first pole is connected to the first pull-up node Q and/or the blanking pull-up control node H, The second pole is connected to a signal line of a low level.
  • the first pole of the charging transistor M1 is connected to the blanking input signal line STU1
  • the second pole of the charging transistor M1 is connected to the blanking pull-up control node H.
  • the charging transistor M1 may leak.
  • the first electrode of the charging transistor M1_a is connected to the blanking input signal line STU1
  • the second electrode of the charging transistor M1_a is connected to the leakage preventing electronic circuit 1001
  • the control electrode of the charging transistor M1_a is connected.
  • Two clock signal lines CLKB Two clock signal lines CLKB.
  • the first pole of the initial reset transistor M12_b is connected to the leakproof electronic circuit 1001
  • the second pole of the initial reset transistor M12_b is connected to the first signal line VSS1
  • the gate of the initial reset transistor M12_b is connected to the initial reset control terminal TRST.
  • the shift register 1000 can include a leak-proof electronic circuit 1001 configured to prevent the charge at the blanking pull-up control node H from passing through the charge transistor when the blanking pull-up control node H is at a high level.
  • M1_a leaks to the blanking input signal line STU1, or leaks to the first signal line VSS1 via the initial reset transistor M12_b.
  • the leakage prevention electronic circuit 1000 may include a first leakage preventing transistor M1_b and a second leakage preventing transistor M15.
  • the first pole of the first leakage preventing transistor M1_b is connected to the blanking pull-up control node H
  • the second pole of the first leakage preventing transistor M1_b is connected to the second pole of the charging transistor M1_a
  • the control pole of the first leakage preventing transistor M1_b is connected with the M1_a The control pole.
  • the first pole of the second leakage preventing transistor M15 is connected to the first pole of the first leakage preventing transistor M1_b, the second pole of the second leakage preventing transistor M15 is connected to the leakage preventing signal input terminal VA, and the control pole of the second leakage preventing transistor M15 is connected. Blanking the pull-up control node H. Wherein, the leakage prevention signal input terminal VA can input a signal of a high level.
  • the second leakage preventing transistor M15 When the blanking pull-up control node H is at a high level, the second leakage preventing transistor M15 is turned on under the control of the blanking pull-up control node H, and inputs a high-level signal input from the leakage preventing signal input terminal VA to the first a first pole of the leakage preventing transistor M1_b, such that the first pole and the second pole of the first leakage preventing transistor M1_b are in a high level state, preventing the charge from the blanking pull-up control node H from passing through the first defense The leakage transistor M1_b is leaking.
  • the combination of the first leakage preventing transistor M1_b and the charging transistor M1_a can achieve the same effect as the aforementioned charging transistor, and at the same time has an anti-leakage effect.
  • the shift register 1000 further includes a third leakage preventing transistor M2_a
  • the first pole of the third leakage preventing transistor M2_a is connected to the blanking pull-up control node H
  • the second pole of the third leakage preventing transistor M2_a is connected.
  • the gate of the third leakage preventing transistor M2_a is connected to the gate of the initial reset transistor M12_b.
  • the working principle of the third leakage preventing transistor M2_a is the same as that of the first leakage preventing transistor M1_b, and can prevent the charge at the blanking pull-up control node H from leaking to the signal terminal VSS1 of the low level through the initial reset transistor M2_b. effect.
  • the leakage-proof electronic circuit of the same principle as described above can be used to achieve leakage prevention. effect.
  • shift register 1000 can further include a second leak-proof electronic circuit 1002.
  • the second leakage-proof electronic circuit 1002 may include transistors M4_b, M5_b, M9_a and M6-a for leakage prevention, the structure and principle thereof.
  • the structure and principle of the first leakage preventing transistor M1_b and the third leakage preventing transistor M2_a shown in the first leakage preventing electronic circuit 1001 are the same.
  • the second leakage-proof electronic circuit 1002 may include a transistor M16.
  • the first pole of the M16 is connected to one of the transistors M4_b, M5_b, M9_a and M6-a for leakage prevention, and the second pole of the M16 is connected to the leakage-proof signal input terminal.
  • the control pole of VA, M16 is connected to the first pull-up node Q. Among them, the leakage prevention signal input terminal VA can input a signal of a high level.
  • FIG. 10 shows only one exemplary circuit structure including a leakage preventing structure, and does not constitute a limitation on the scope of the present disclosure.
  • FIG. 11 illustrates an exemplary circuit structure of a shift register according to an embodiment of the present disclosure.
  • the isolation sub-circuit in the shift register 1100 shown in FIG. 11 employs the structure of the isolation sub-circuit as shown in FIG. 6f, in which the first pull-up node Q and the blanking pull-up control node H pass through the isolation transistor. M3 is connected.
  • the potentials of the first pull-up node Q and the blanking pull-up control node H are different (for example, one of the first pull-up node Q and the blanking pull-up control node H is at a high level, the other is at a low level Level), there may be a case where leakage occurs between the first pull-up node Q and the blanking pull-up control node H.
  • the shift register may include a first leakproof electronic circuit 1101 and a second leakproof electronic circuit 1102.
  • the first leakproof electronic circuit 1101 may include a first leakage preventing transistor M3_a and a second leakage preventing transistor M15.
  • the first pole of the first leakage preventing transistor M3_a is connected to the blanking pull-up control node H
  • the second pole of the first leakage preventing transistor M3_a is connected to the first pole of the isolation transistor M3_b
  • the control of the first leakage preventing transistor M3_a The pole is connected to the gate of the isolation transistor M3_b.
  • the first pole of the second leakage preventing transistor M15 is connected to the leakage preventing signal input terminal VA
  • the second pole of the second leakage preventing transistor M15 is connected to the second pole of the first leakage preventing transistor M3_a
  • the control of the second leakage preventing transistor M15 The pole is connected to the blanking pull-up control node H.
  • the second leakage preventing transistor M15 can be turned on under the control of the blanking pull-up control node H, and the high-level signal input from the leakage preventing signal input terminal VA It is input to the second pole of the first leakage preventing transistor M3_a (i.e., point A in Fig. 11).
  • the first leakage preventing electronic circuit 1101 can be used to prevent leakage of the blanking pull-up control node H through the isolation transistor M3 to the first pull-up node Q when the blanking pull-up control node H is at a high level.
  • the second leakage preventing electronic circuit 1102 may include a third leakage preventing transistor M3_c and a fourth leakage preventing transistor M16.
  • the first pole of the third leakage preventing transistor M3_c is connected to the first pull-up node Q
  • the second pole of the third leakage preventing transistor M3_c is connected to the second pole of the isolation transistor M3_b
  • the control pole of the third leakage preventing transistor M3_c Connected to the gate of isolation transistor M3_b.
  • the first pole of the fourth leakage preventing transistor M16 is connected to the leakage preventing signal input terminal VA
  • the second pole of the fourth leakage preventing transistor M16 is connected to the second pole of the third leakage preventing transistor M3_c
  • the control of the fourth leakage preventing transistor M16 The pole is connected to the first pull-up node Q.
  • the fourth leakage preventing transistor M16 can be turned on under the control of the first pull-up node Q, and input a high-level signal input from the leakage preventing signal input terminal VA to The second pole of the third leakage preventing transistor M3_c (ie, point B in FIG. 11).
  • the second leakage preventing electronic circuit 1102 it is possible to prevent leakage of the first pull-up node Q through the isolation transistor M3 to the blanking pull-up control node H when the first pull-up node Q is at a high level.
  • the capacitor in the shift register as described above can be either a capacitor or a coupling capacitor of the transistor.
  • FIG. 12 shows a schematic block diagram of a gate drive circuit in accordance with an embodiment of the present disclosure.
  • the gate driving circuit includes a multi-stage cascaded shift register, wherein any one or more stages of shift registers may adopt the structure of a shift register as shown in one of FIGS. 2-11 or Its variant.
  • the display input terminal STU2 of the shift register of the i-th stage and the blanking input terminal STU1 and the shift register of the i-1th stage are The output terminal CR is connected, and the output terminal CR of the shift register of the i-th stage is connected to the display reset terminal STD2 of the shift register of the i-1th stage, where N is an integer greater than 2, and 1 ⁇ i ⁇ N.
  • the display input terminal STU2 of the shift register of the first stage is connected to the display signal line, and the blanking input terminal is connected to the blanking signal line; the display reset control terminal STD2 of the shift register of the Nth stage is connected to the display reset signal line.
  • Each row of shift registers is connected to the second clock signal line CLKB and the third clock signal line CLKC, respectively.
  • Each row of shift registers can also be connected to the initial reset signal line TRST.
  • the odd row shift registers are respectively connected to the first clock signal line CLKA_o and the fourth clock signal line CLKD_o, and the even row shift registers are respectively connected to the first clock signal line CLKA_e and the fourth clock signal line CLKD_e.
  • FIG. 13 An exemplary circuit structure of a gate driving circuit in accordance with an embodiment of the present disclosure is shown in FIG.
  • the cascaded shift registers in the gate drive circuit shown in FIG. 13 can be replaced by variations of any of the aforementioned shift registers, and will not be described again.
  • control terminal of the charging transistor of the odd-numbered shift register is connected to the second clock signal line CLKB, and the control terminal of the charging transistor of the even-numbered shift register is connected to the third clock signal line CLKC.
  • FIG. 14a illustrates a driving timing diagram of a gate driving circuit in accordance with an embodiment of the present disclosure.
  • the drive timing diagram shown in Figure 14a applies to the gate drive circuit shown in Figures 12-13.
  • the shift register shown in FIG. 8 as an example, the driving timing of the gate driving circuit including the shift register of the multi-stage cascade is described.
  • CLKA_odd represents the first clock signal line CLKA of the shift register of the odd-numbered rows (for example, the first, third, fifth, ... rows) in the gate driving circuit
  • CLKA_even represents the gate driving The first clock signal line CLKA of the shift register of even lines (for example, lines 2, 4, 6...) in the circuit
  • CLKD_odd represents the fourth clock signal line CLKD of the shift register of the odd-numbered rows (eg, lines 1, 3, 5...) in the gate drive circuit
  • CLKD_even represents the even-numbered lines in the gate drive circuit (for example, the second The fourth clock signal line CLKD of the shift register of 4, 6, ... row).
  • Q_1H represents the potential change at the first pull-up node Q in the first row shift register of the gate drive circuit
  • Q_2H represents the potential change at the first pull-up node Q in the second row shift register of the gate drive circuit
  • OUT_1H represents the potential change at the output terminal OUT in the first row shift register in the gate drive circuit
  • OUT_2H represents the potential change at the output terminal OUT in the second row shift register in the gate drive circuit.
  • STU1, STU2 shown in Figure 14a represent the blanking input signal and display input signal of the first row of shift register connections, respectively, and STD2 represents the display reset control signal of the last row of shift register connections.
  • one of the seventh clock signal line CLKM and the eighth clock signal line CLKM inputs a high level conduction signal, and the other input a low level non-conduction signal. . Therefore, at this time, the pull-down node QB of each row shift register is maintained at the high level state, and the first pull-up node Q is maintained at the low level.
  • the gate driving circuit can receive the initial reset control signal TRST1, and blanking up the shift register of each shift register in the gate driving circuit through the initial reset sub-circuit The control node resets.
  • Figure 14b shows another drive timing diagram for the initial reset of the shift register in accordance with the present disclosure.
  • the shift register may omit the initial reset sub-circuit and the initial reset signal line TRST1.
  • the blanking pull-up control node H can be initially reset using the second clock signal line CLKB and the third clock signal line CLKC.
  • the shift register of each row can be realized by inputting a second clock signal CLKB of a high level before inputting the first frame, and then inputting a third clock signal CLKC of a high level.
  • the reset of the pull-up control node H is blanked.
  • blanking pull-up control for each row of shift registers can also be realized by inputting a high-level third clock signal CLKC and then inputting a high-level second clock signal CLKB before displaying the first frame.
  • Reset of node H can also be realized by simultaneously inputting the second clock signal CLKB of the high level and the third clock signal CLKC.
  • the shift register when the shift register includes a blanking reset sub-circuit (such as the blanking reset sub-circuit 470 shown in FIG. 8), it is also possible to utilize the blanking reset sub-circuit pair first before displaying the first frame.
  • the pull-up node Q is reset.
  • a signal of a high level can be input through the blanking reset control terminal TRST2.
  • the reset of the blanking pull-up control node H can be realized while the second clock signal and the third clock signal inputting the high level are used as the initial reset signal, and the high level is input.
  • the reset signal is blanked to achieve an initial reset of the first pull-up node Q.
  • the high level signal input by the TRST2 may cover the high level signal input from the second clock signal line CLKB and the third clock signal line CLKC. That is, the rising edge of the initial reset signal input by TRST2 is earlier than the rising edge of each high-level signal input by the second clock signal line CLKB and the third clock signal line CLKC, and the falling edge is later than the second clock signal line CLKB and The falling edge of each high level signal input by the third clock signal line CLKC.
  • the circuit structure of the shift register can be further simplified by the above-described initial reset driving method.
  • the first row of shift registers receives a signal from the display input STU2 for displaying the input high level.
  • the display input sub-circuit can output a display pull-up signal to the first pull-up node Q according to the display input signal, and pull up the potential of the first pull-up node Q to a high level.
  • the output sub-circuit receives a high-level signal input from the fourth clock signal line CLKD_odd of the first row.
  • the output transistors M11 and M13 are turned on under the control of the first pull-up node Q, the high-level signal input from the fourth clock signal line CLKD can be outputted from the output terminal via the output transistors M11 and M13.
  • the cascaded plurality of shift registers as shown in FIG. 13 will complete the output of the display signal line by line.
  • the output of the first row shift register outputs the signal OUT_1H
  • the output of the second row shift register outputs the signal OUT_2H, and so on, and will not be described again.
  • the reset control is connected to the output of the second row of shift registers. Therefore, when the second row shift register outputs the display output signal OUT_2H, the first pull-up node Q of the first row shift register is reset to the low level.
  • the first pull-up node Q of each row of shift registers is then reset to a low level after outputting the display output signal.
  • the first pull-up node Q of the last row shift register will be reset under the control of the display reset control signal STD2.
  • the first row shift register receives the high level signal input by the blanking input terminal STU1 and the second clock signal line CLKB, and the second clock signal line CLKB inputs the high level signal, therefore,
  • the charging transistor M1 is turned on, and the potential of the blanking pull-up control node H is pulled up to a high level by the charging transistor M1. Due to the presence of the first capacitor C1, the blanking pull-up control node H will remain in a high state.
  • the shift register can receive the blanking reset signal through the blanking reset signal line, thereby resetting the potential of the first pull-up node Q and/or the output.
  • each row shift register repeats the driving timing of the shift register identical to the display phase of the first frame, and outputs the driving signal of the pixel circuit row by row, which will not be described herein.
  • the third clock signal line CLKC inputs a high level signal, and since the blanking pull-up control node H is in a high level state, the first isolation transistor M3 is a guide. Therefore, the high-level signal input by the third clock signal line CLKC can be used to pull up the potential of the first pull-up node Q to a high level.
  • the fourth clock signal line CLKD outputs a high level signal. At this time, since the output transistor M3 is turned on under the control of the first pull-up node Q, the high-level signal input from the fourth clock signal line CLKD can be output as the blanking output signal via the output terminal.
  • the output terminal CR of the first row shift register is connected to the blanking input terminal of the second row shift register. Therefore, the blanking output signal of the first row shift register can be used as the first
  • the blanking input signal of the two-row shift register pulls up the potential of the blanking pull-up control node H of the second row shift register to a high level.
  • the shift register Before the end of the blanking phase of the second frame, the shift register can receive the blanking reset signal through the blanking reset signal line, thereby resetting the potential of the first pull-up node Q and/or the output.
  • the driving timing of the shift register of the first frame display phase is repeated, and the driving signals of the pixel circuits are outputted row by row, and will not be described herein.
  • the second clock signal line CLKB inputs a high level clock signal
  • the second line shift register repeats the driving timing of the first line shift register in the blanking phase of the second frame
  • the second row shift register outputs a blanking output signal.
  • the blanking output signal of the second row of shift register outputs can be used to pull the potential of the blanking pull-up control node H of the third row of shift registers to a high level.
  • the second clock signal line CLKB inputs a high-level clock signal, and the charging transistor M1 is turned on under the control of the high-level clock signal.
  • the blanking input terminal of the first row shift register inputs a signal of a low level, and therefore, the charge stored in the first capacitor of the first row shift register can be discharged via the charging transistor, and blanking is performed
  • the potential of the pull-up control node H is pulled down to a low level.
  • the shift register Before the end of the blanking phase of the third frame, the shift register can receive the blanking reset signal through the blanking reset signal line, thereby resetting the potential of the first pull-up node Q and/or the output.
  • the cascaded shift registers output the corresponding drive signals row by row.
  • the cascaded shift registers sequentially output blanking output signals.
  • the first row shift register outputs a blanking output signal for the first row of pixel circuit cells during the blanking phase of the second frame
  • the second row of shift registers is in the blanking phase of the third frame.
  • the blanking output signal for the second row of pixel circuit units is output, and so on.
  • FIG. 15 illustrates a driving timing chart of a gate driving circuit according to an embodiment of the present disclosure.
  • the cascaded shift registers output the corresponding drive signals row by row.
  • the driving timing of the display phase is the same as that shown in FIG. 14a, and details are not described herein again.
  • the blanking input terminal of the first line shift register is displayed in the first frame.
  • the phase inputs a high level blanking input signal
  • the third clock signal line CLKB inputs a high level signal, thereby pulling up the potential at the H point of the blanking pull-up control node of the first row shift register.
  • the third clock signal line CLKC inputs a high-level clock signal
  • the second isolation transistor M4 is turned on under the control of the high-level signal of the CLKC input
  • the first row shift register is turned on.
  • the potential of the first pull-up node Q is pulled up to a high level.
  • the fourth clock signal line CLKD_odd connected to the first row shift register inputs a fourth clock signal of a high level, and outputs the fourth clock signal as a blanking output signal from the output terminal.
  • the second clock signal line CLKB and the third clock signal line CLKC sequentially input a high level on signal, thereby controlling each row of shift registers to sequentially output a blanking output. signal.
  • the first row shift register outputs a blanking output signal during the blanking phase of the first frame
  • the second row shift register outputs a blanking output signal during the blanking phase of the second frame, and so on.
  • the cascaded shift register can sequentially output the display output signals row by row in the display phase of one frame, and the frequency of one line of signals is outputted per frame during the blanking period of one frame.
  • the lines sequentially output blanking output signals.
  • the display output signal and the blanking output signal of each shift register share an output transistor.
  • FIG. 16 shows a schematic block diagram of a gate drive circuit in accordance with an embodiment of the present disclosure. As shown in FIG. 16, only the first four stages of the N-stage cascaded shift register are shown. For 2 ⁇ i ⁇ N-1, the blanking input of the i-th row shift register is connected to the output of the i-1th shift register, and the display input of the i-th shift register is connected to the i-2 At the output of the row shift register, the display reset terminal of the ith row shift register is connected to the output of the i+2th row shift register.
  • the blanking input end and the display input end of the first row shift register are respectively connected to the blanking input signal line and the first display input signal line, and the display input end of the second row shift register is connected to the second display input signal line.
  • the display reset end of the N-1th row shift register is connected to the first display reset signal line, and the display reset end of the Nth row shift register is connected to the first display reset signal line.
  • Each row of shift registers is connected to a second clock signal line CLKB and a third clock signal line CLKC, respectively.
  • Each row of shift registers can also be connected to the initial reset signal line TRST.
  • the odd row shift registers are respectively connected to the first clock signal line CLKA_o and the fourth clock signal line CLKD_o, and the even row shift registers are respectively connected to the first clock signal line CLKA_e and the fourth clock signal line CLKD_e.
  • FIG. 17 shows a driving timing chart of a gate driving circuit according to an embodiment of the present disclosure.
  • the driving timing shown in Fig. 17 can be used for the gate driving circuit shown in Fig. 16.
  • CLKD_1, CLKD_2, CLKD_3, and CLKD_4 respectively represent the fourth clock signal line to which the shift registers of the first, second, third, and fourth rows are connected.
  • Q ⁇ 1> and Q ⁇ 2> represent potential changes at the first pull-up node Q in the shift registers of the first and second rows, respectively.
  • OUT ⁇ 1>, OUT ⁇ 2>, OUT ⁇ 3>, and OUT ⁇ 4> represent the potential changes at the output terminals CR and OUT in the shift registers of the first, second, third, and fourth rows, respectively.
  • one of the seventh clock signal line CLKM and the eighth clock signal line CLKM inputs a high level conduction signal, and the other input a low level non-conduction signal. . Therefore, at this time, the pull-down node QB is maintained in the high state, and the first pull-up node Q is maintained in the low state.
  • the gate driving circuit can receive the initial reset control signal TRST before displaying the first frame, and shift each of the gate driving circuits by the initial reset sub-circuit as described above.
  • the blanking pull-up control node H of the register is reset.
  • the first row of shift registers receives a signal from the display input STU2 for displaying the input high level.
  • the display input sub-circuit can output a display pull-up signal to the first pull-up node Q according to the display input signal, and pull up the potential of the first pull-up node Q to a high level.
  • the output sub-circuit receives a high-level signal input from the fourth clock signal line CLKD_1 of the first row.
  • the output transistors M11 and M13 are turned on under the control of the first pull-up node Q, the high-level signal input from the fourth clock signal line CLKD can be outputted from the output terminal via the output transistors M11 and M13.
  • the second row shift register it can receive a signal for displaying the input high level from the second display input signal line STU2_2.
  • the display input sub-circuit of the second row shift register may output a display pull-up signal to the first pull-up node Q according to the display input signal, and pull up the potential of the first pull-up node Q to a high level.
  • the output sub-circuit of the second row shift register receives a high level signal input from the fourth clock signal line CLKD_2.
  • the output transistors M11, M13 are turned on under the control of the first pull-up node Q, the high-level signal input by the fourth clock signal line CLKD_2 can be outputted from the output terminal via the output transistors M11, M13. CR, OUT_1H output.
  • the clock signal input from the fourth clock signal line CLKD_2 connected to the second row shift register is the same as the clock signal input from the clock signal input from the fourth clock signal line CLKD_12 connected to the first row shift register.
  • the rising edge of the clock signal input by the fourth clock signal line CLKD_2 connected to the second row shift register is later than the rising edge of the clock signal input by the fourth clock signal line CLKD_1 connected to the first row shift register.
  • the width, correspondingly, the display input signal output by the second row shift register is also half the width of the clock signal later than the display input signal output by the first row shift register. At this time, there is a 50% pulse overlap between the display output signal of the first row shift register and the display output signal of the second row shift register.
  • the odd-numbered shift registers in the cascaded plurality of shift registers as shown in FIG. 16 will be based on The display output signal of the first line shift register completes the output of the display signal line by line.
  • an even-numbered shift register of the cascaded plurality of shift registers as shown in FIG. 16 will complete the output of the display signal line by line according to the display output signal of the first row shift register.
  • the driving method of the gate driving circuit shown in FIG. 16 in the blanking phase is the same as that in the blanking phase of the gate driving circuit shown in FIGS. 12 and 13 . I will not repeat them here.
  • the N-row cascading shift register may be divided into a plurality of shift register groups, for example, the gate drive circuit includes m groups, wherein each group includes n shift registers as described above.
  • the blanking input signal terminals of the above-mentioned N-line cascaded shift registers are connected in a row-by-row cascade manner. That is, the output of the first row shift register is connected to the blanking input of the second row shift register, and the output of the second row shift register is connected to the blanking input of the third row shift register. And so on.
  • the n shift registers in each of the above-mentioned shift register groups are respectively connected to the n shift registers in the next set of shift register by a row-by-row connection. That is, the output of the first shift register in the first group of shift register groups is connected to the first shift register in the second group of shift register groups (ie, the nth in the N-row shift register). +1 line) display input, the output of the second shift register in the first group shift register group is connected to the second shift register in the second group shift register group (ie, N line shift) The display input of the n+2th line in the register, and so on.
  • the display output signal of each row shift register in the gate drive circuit as described above will have a portion where the display output signal of the next shift register has a 1/n pulse overlap.
  • the display output signal of the gate driving circuit shown in FIG. 16 employs an odd-line cascading, even-numbered cascading connection manner to realize a display output signal having 50% overlap. If the first, fourth, and seventh rows are cascaded, the second, fifth, and eighth rows are cascaded, and the third, sixth, and eighth rows are cascaded to realize a display output signal having 33% overlap.
  • a person skilled in the art can select the connection mode of the gate driving circuit according to the actual situation, thereby outputting display output signals having different overlapping ratios between adjacent shift registers.
  • FIG. 18 shows a schematic block diagram of a gate driving circuit in accordance with an embodiment of the present disclosure.
  • N is a positive integer.
  • the blanking input of the i-th row shift register is connected to the output of the i-1th shift register, and the display input of the i-th shift register is connected to the i-2
  • the display reset terminal of the ith row shift register is connected to the output of the i+3th row shift register.
  • the blanking input end and the display input end of the first row shift register are respectively connected to the blanking input signal line and the first display input signal line, and the display input end of the second row shift register is connected to the second display input signal line.
  • the display reset end of the N-2th row shift register is connected to the first display reset signal line, and the display reset end of the N-1th row shift register is connected to the second display reset signal line.
  • the display reset terminal of the Nth row shift register is connected to the third display reset signal line.
  • Each row of shift registers is connected to the second clock signal line CLKB and the third clock signal line CLKC, respectively.
  • Each row of shift registers can also be connected to the initial reset signal line TRST.
  • the odd row shift registers are respectively connected to the first clock signal line CLKA_o and the fourth clock signal line CLKD_o, and the even row shift registers are respectively connected to the first clock signal line CLKA_e and the fourth clock signal line CLKD_e.
  • the difference between the gate driving circuit shown in FIG. 18 and the gate driving circuit shown in FIG. 16 is that the output terminal of the ith row shift register in FIG. 16 is connected to the display input of the i+2th row shift register.
  • the terminal, and the output of the i+2th row shift register are connected to the display reset control terminal of the i-th row shift register.
  • FIG. 19 illustrates a driving timing diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the driving timing shown in Fig. 19 can be used for the gate driving circuit shown in Fig. 18.
  • the gate drive circuit shown in FIG. 18 differs from the gate drive circuit shown in FIG. 16 only in that the connection manner of the reset control terminal is different. Therefore, the driving timing of the display input of each row shift register and the driving timing of the blanking input in the driving timing shown in FIG. 19 are both the same as the driving timing shown in FIG. 17, and details are not described herein again.
  • the output terminal OUT outputs a driving signal for driving the pixel circuit
  • the output transistor M13 will employ a bulky transistor.
  • the reset phase is displayed, and the charge accumulated at the output terminal OUT can be reset by the display reset transistor M14_a, where the display reset transistor M14_a also needs to be used. Larger transistor.
  • the reset transistor M14_a can be displayed at this time. A smaller transistor is used, thereby further reducing the volume of the shift register unit.
  • the potential of the first pull-up node Q rises due to the bootstrap effect when the output terminal of the output sub-circuit is at a high level, the current flowing through the output transistor M13 when discharging the output terminal can be larger, and the discharge speed Faster.
  • FIG. 20 shows a flowchart of a driving method for a shift register as described above according to an embodiment of the present disclosure.
  • the driving method 2000 may include a step 2001 of inputting a display pull-up signal to the first pull-up node via the display input sub-circuit.
  • Step 2002 the first output stage outputs a first output signal via the output sub-circuit under the control of the first pull-up node.
  • Step 2003 the second control phase, inputting the blanking pull-up signal to the first pull-up node via the blanking input sub-circuit.
  • Step 2004, the second output stage A second output signal is output via the output sub-circuit under the control of the first pull-up node.
  • the driving method 2000 may further include a step 2002b of displaying a reset phase to reset the first pull-up node under control of displaying the reset control signal.
  • the driving method 2000 may further include a step 2004b of the blanking reset phase to reset the first pull-up node under the control of the blanking reset control signal.
  • a driving method for a shift register according to an embodiment of the present disclosure, a blanking input sub-circuit for controlling an output sub-circuit to output a blanking output signal during a blanking period, and a control output sub-circuit outputting a display output signal during a display period
  • the display input sub-circuits can share the same pull-up node Q and the same output sub-circuit, thereby implementing a smaller-sized shift register structure.

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Abstract

公开了一种移位寄存器(200)，包括：第一输入子电路(210)，配置成从第一输入端接收第一输入信号，并根据第一输入信号在一帧的消隐时段将消隐输出控制信号输入到第一节点(Q)；第二输入子电路(220)，配置成从第二输入端接收第二输入信号，并根据第二输入信号在一帧的显示时段将显示输出控制信号输入到所述第一节点(Q)；输出子电路(230)，配置成在所述第一节点(Q)的控制下，经由输出端(OUT)输出复合输出信号，所述复合输出信号包括彼此独立地在显示时段输出的显示输出信号和在消隐时段输出的消隐输出信号。

Description

移位寄存器、栅极驱动电路、显示装置以及驱动方法
相关申请的交叉引用
本申请要求于2018年02月14日递交的中国专利申请第201810151627.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的一部分。
技术领域
本公开涉及一种移位寄存器、包括该移位寄存器的栅极驱动电路、显示装置以及应用于该移位寄存器的驱动方法。
背景技术
在显示领域特别是有机发光二极管OLED显示中，栅极驱动电路目前都集成在栅极集成电路(GATE IC)中，集成电路IC设计中芯片的面积是影响芯片成本的主要因素，如何有效地降低芯片面积是技术开发人员需要着重考虑的。
目前OLED栅极驱动电路通常要用三个子电路组合而成，即检测单元(sense unit)，显示单元(scan unit)和输出两者复合脉冲的连接单元(或门电路或Hiz电路)，这样电路的结构非常复杂，无法满足高分辨率窄边框的要求。
发明内容
本公开提供了一种移位寄存器、栅极驱动电路、显示装置以及驱动方法移位寄存器。
根据本公开的一方面，提供了一种移位寄存器，包括：第一输入子电路，配置成从第一输入端接收第一输入信号并输出消隐输出控制信号；第二输入子电路，配置成从第二输入端接收第二输入信号并输出显示输出控制信号；输出子电路，配置成在所述第一节点的控制下，经由输出端输出复合输出信号，所述复合输出信号包括彼此独立地在显示时段输出的显示输出信号和在 消隐时段输出的消隐输出信号。
在一些实施例中，所述第一输入子电路配置成从第一输入端接收第一输入信号，并根据第一输入信号在一帧的消隐时段将消隐输出控制信号输入到第一节点；所述第二输入子电路配置成从第二输入端接收第二输入信号，并根据第二输入信号在一帧的显示时段将显示输出控制信号输入到所述第一节点。
在一些实施例中，所述第一输入子电路包括：充电子电路，配置成根据所述第一输入信号将所述第一输入信号输入到消隐上拉控制节点；存储子电路，其一端连接消隐上拉控制节点，配置成根据所述第一输入信号存储消隐上拉控制信号；隔离子电路，配置成在一帧的消隐时段，根据所述消隐输出控制信号将所述消隐输出控制信号输入到所述第一节点。
在一些实施例中，所述移位寄存器还包括：显示复位子电路，配置成在显示复位控制信号的控制下对所述第一节点进行复位。
在一些实施例中，所述移位寄存器还包括：消隐复位子电路，配置成在一帧的消隐时段结束前，在消隐复位控制信号的控制下对所述第一节点和/或所述输出端进行复位。
在一些实施例中，所述输出子电路包括至少一个移位信号输出端以及至少一个像素信号输出端。
在一些实施例中，所述移位寄存器还包括：下拉控制子电路，配置成根据所述第一节点的控制下拉节点的电位；下拉子电路，配置成在所述下拉节点的控制下，将所述第一节点和所述输出端下拉为非工作电位。
在一些实施例中，所述充电子电路包括充电晶体管，充电晶体管的第一极和/或控制极连接所述第一输入端，充电晶体管的第二极连接所述消隐上拉控制节点；以及所述存储子电路包括第一电容，第一电容的第一端连接所述消隐上拉控制节点；以及所述隔离子电路包括第一隔离晶体管和第二隔离晶体管，其中所述第一隔离晶体管的控制端连接所述消隐上拉控制节点，所述第二隔离晶体管的第一极连接所述第一隔离晶体管的第二极，所述第二隔离晶体管的第二极连接所述第一节点，所述第二隔离晶体管的控制极连接隔离控制信号线。
在一些实施例中，所述第二输入子电路包括第一显示输入晶体管，所述 第一显示输入晶体管的第一极连接所述第一节点，所述第一显示输入晶体管的第二极和/或控制极连接所述第二输入端；所述输出子电路包括输出晶体管和输出电容，其中所述输出晶体管的第一极连接输出时钟信号线，所述输出晶体管的第二极连接输出端，所述输出晶体管的控制极连接所述第一节点，所述输出电容的第一端连接所述第一节点，所述输出电容的第二端连接所述输出端。
在一些实施例中，所述第二输入子电路还包括第二显示输入晶体管，所述第二显示输入晶体管的第一极和控制极相连，并连接到所述第一显示输入晶体管的第一极，所述第二显示输入晶体管的第二极连接所述第一节点。
在一些实施例中，所述显示复位子电路包括显示复位晶体管，所述显示复位晶体管的第一极连接所述第一节点，所述显示复位晶体管的控制极连接显示复位控制端，所述显示复位晶体管的第二极连接显示复位信号线。
在一些实施例中，所述消隐复位子电路包括第一消隐复位晶体管，所述第一消隐复位晶体管的第一极连接所述第一节点，所述第一消隐复位晶体管的控制极连接消隐复位控制端，所述第一消隐复位晶体管的第二极连接消隐复位信号线。
在一些实施例中，所述消隐复位子电路还包括第二消隐复位晶体管，所述第二消隐复位晶体管的第一极连接所述输出端，所述第二消隐复位晶体管的控制极连接消隐复位控制端，所述第二消隐复位晶体管的第二极连接消隐复位信号线。
在一些实施例中，所述下拉控制子电路包括第一下拉控制晶体管和第二下拉控制晶体管，其中所述第一下拉控制晶体管的第一极和控制极相连并连接到下拉控制信号线，所述第一下拉控制晶体管第二极连接下拉节点，所述第二下拉控制晶体管的第一极连接所述下拉节点，所述第二下拉控制晶体管的控制极连接所述第一节点，所述第二下拉控制晶体管的第二极连接下拉信号线；所述下拉子电路包括第一下拉晶体管和第二下拉晶体管，其中所述第一下拉晶体管的第一极连接所述第一节点，所述第一下拉晶体管的控制极连接所述下拉节点，所述第一下拉晶体管的第二极连接下拉信号线，所述第二下拉晶体管的第一极连接所述输出端，所述第二下拉晶体管的控制极连接所述下拉节点，所述第二下拉晶体管的第二极连接下拉信号线。
在一些实施例中，所述移位寄存器还包括：防漏电子电路，其配置成在所述第一节点和/或所述消隐上拉控制节点的控制下，将工作电位输入到所述第二隔离晶体管的第一极和/或第二极。
根据本公开的另一方面，提供了一种栅极驱动电路，包括级联的N行移位寄存器，所述移位寄存器为如前所述的移位寄存器，其中，第i级的移位寄存器的第二输入端和第一输入端与第i-1级的移位寄存器的输出端连接，第i级的移位寄存器的输出端与第i-1级的移位寄存器的显示复位端连接，其中N为大于2的整数，1<i≤N；第1级的移位寄存器的第二输入端连接到显示信号线，第一输入端连接到消隐信号线；第N级的移位寄存器的显示复位控制端与显示复位信号线连接。
根据本公开的另一方面，提供了一种显示装置，其特征在于，包括如前所述的栅极驱动电路。
根据本公开的另一方面，提供了一种应用于如前所述的移位寄存器的驱动方法，包括：在一帧的显示时段，包括第一控制阶段，经由第二输入子电路将显示输出控制信号输入到第一节点；第一输出阶段，在所述第一节点的控制下经由输出子电路输出第一输出信号；在一帧的消隐时段，包括第二控制阶段，经由第一输入子电路将消隐输出控制信号输入到所述第一节点；第二输出阶段。在所述第一节点的控制下经由输出子电路输出第二输出信号。
在一些实施例中，所述驱动方法还包括：显示复位阶段，在显示复位控制信号的控制下对所述第一节点进行复位。
在一些实施例中，所述驱动方法还包括：消隐复位阶段，在消隐复位控制信号的控制下对所述第一节点进行复位。
根据本公开提供移位寄存器，可以实现利用一个移位寄存器电路实现检测单元、显示单元以及连接单元的功能，减小了栅极驱动电路的结构。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员而言，在没有做出创造性劳动的前提下，还可以根据这些附图获得其他的附图。以下附图并未刻意 按实际尺寸等比例缩放绘制，重点在于示出本公开的主旨。
图1示出了根据现有技术的一种用于OLED面板的移位寄存器的结构的示意框图；
图2示出了根据本公开的实施例的移位寄存器的结构的示意框图；
图3a示出了根据本公开的实施例的显示输入子电路的示例性的电路结构一；
图3b示出了根据本公开的实施例的显示输入子电路的示例性的电路结构二；
图3c示出了根据本公开的实施例的显示输入子电路的示例性的电路结构三；
图3d示出了根据本公开的实施例的显示输入子电路的示例性的电路结构四；
图3e示出了根据本公开的实施例的显示输入子电路的示例性的电路结构五；
图3f示出了根据现有技术的输出端OUT以及第一上拉节点Q处的电位的仿真示意图；
图3g示出了根据本公开的实施例的输出端OUT以及第一上拉节点Q处的电位的仿真示意图；
图4a示出了根据本公开的实施例的输出子电路的示例性的电路结构一；
图4b示出了根据本公开的实施例的输出子电路的示例性的电路结构二；
图4c示出了根据本公开的实施例的输出子电路的示例性的电路结构三；
图5示出了根据本公开的实施例的移位寄存器的结构的示意框图；
图6a示出了根据本公开的实施例的消隐输入子电路的示例性的电路结构一；
图6b示出了根据本公开的实施例的消隐输入子电路的示例性的电路结构二；
图6c示出了根据本公开的实施例的消隐输入子电路的示例性的电路结构三；
图6d示出了根据本公开的实施例的消隐输入子电路的示例性的电路结构四；
图6e示出了根据本公开的实施例的消隐输入子电路的示例性的电路结构五；
图6f示出了根据本公开的实施例的消隐输入子电路的示例性的电路结构六；
图7示出了根据本公开的实施例的移位寄存器的结构的再一示意框图；
图8示出了根据本公开的实施例的移位寄存器的示例性的电路结构一；
图9示出根据本公开的实施例的移位寄存器的示例性的电路结构二；
图10示出了根据本公开的实施例的移位寄存器的示例性的电路结构三；
图11示出了根据本公开的实施例的移位寄存器的示例性的电路结构四；
图12示出了根据本公开的实施例的栅极驱动电路的示意性框图；
图13示出了根据本公开的实施例的栅极驱动电路的示例性的电路结构；
图14a示出了根据本公开的实施例的栅极驱动电路的驱动时序图；
图14b示出了根据本公开的实施例的栅极驱动电路的驱动时序图一；
图14c示出了根据本公开的实施例的栅极驱动电路的驱动时序图二；
图15示出了根据本公开的实施例的栅极驱动电路的驱动时序图；
图16示出了根据本公开的实施例的栅极驱动电路的另一示意性框图；
图17示出了根据本公开的实施例的栅极驱动电路的驱动时序图；
图18示出了根据本公开的实施例的栅极驱动电路的再一示意性框图；
图19示出了根据本公开的实施例的栅极驱动电路的驱动时序图；以及
图20示出了根据本公开实施例的用于如前所述的移位寄存器的驱动方法的流程图。
具体实施方式
下面将结合附图对本公开实施例中的技术方案进行清楚、完整地描述，显而易见地，所描述的实施例仅仅是本公开的部分实施例，而不是全部的实施例。基于本公开实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，也属于本公开保护的范围。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
如本公开说明书和权利要求书中所示，除非上下文明确提示例外情形，“一”、“一个”、“一种”和/或“该”等词并非特指单数，也可包括复数。一般说来，术语“包括”与“包含”仅提示包括已明确标识的步骤和元素，而这些步骤和元素不构成一个排它性的罗列，方法或者设备也可能包含其他的步骤或元素。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的连接方式可以互换，因此，本公开实施例中各晶体管的漏极、源极实际是没有区别的。这里，仅仅是为了区分晶体管除栅极之外的两极，而将其中一极称为漏极，另一极称为源极。本公开实施例中采用的薄膜晶体管可以为N型晶体管，也可以为P型晶体管。在本公开实施例中，当采用N型薄膜晶体管时，其第一极可以是源极，第二极可以是漏极。在以下实施例中，以薄膜晶体管为N型晶体管为例进行的说明，即栅极的信号是高电平时，薄膜晶体管导通。可以想到，当采用P型晶体管时，需要相应调整驱动信号的时序。具体细节不在 此赘述，但也应该在本发明的保护范围内。
图1示出了根据现有技术的一种用于OLED面板的移位寄存器的结构的示意框图。
如图1中所示出的，现有技术中用于OLED面板的移位寄存器通常有显示单元、检测单元以及补偿单元三个部分组成。其中，显示单元和检测单元分别包括一组输出晶体管。利用上述三个部分的电路结构，移位寄存器可以输出具有不同宽度和时序的两个波形组成的复合波形的输出脉冲。
然而，由于在上述现有的用于OLED面板的移位寄存器中，分别利用显示单元和检测单元实现复合波形的输出脉冲，上述的移位寄存器具有尺寸过大的缺点。为了进一步减小移位寄存器以及包括移位寄存器的栅极驱动电路的尺寸，以下将介绍根据本公开的实施例提供的移位寄存器。
图2示出了根据本公开的实施例的移位寄存器的结构的示意框图。如图2所示，移位寄存器200包括第一输入子电路210，第二输入子电路220以及输出子电路230。其中第一输入子电路210、第二输入子电路220以及输出子电路230通过第一节点Q相连接。由于在本公开中以N型晶体管为例进行说明，因此，在本公开中，第一节点Q也被称作是第一上拉节点Q。如果将本公开中的N型晶体管替换为P型晶体管，则在本公开中提及的“上拉节点”、“上拉信号”也可以被称作“下拉节点”、“下拉信号”。第一输入子电路配置成从第一输入端接收第一输入信号，并根据第一输入信号在一帧的消隐时段将消隐输出控制信号输入到第一节点。第二输入子电路配置成从第二输入端接收第二输入信号，并根据第二输入信号在一帧的显示时段将显示输出控制信号输入到所述第一节点。
在本公开中，第一输入子电路210也被称作是消隐输入子电路210，第二输入子电路220在本公开中也被称作是显示输入子电路220。
本公开中的消隐输入子电路中的“消隐”仅是表示该电路和消隐时段有关，而并不限定该电路仅工作在消隐时段中，以下各实施例与此相同，不再赘述。例如，消隐输入子电路可以在显示时段对下文中将提到的消隐上拉控制节点H充电，并使消隐上拉控制节点H的高电平保持至消隐时段。消隐输入子电路在消隐时段可以对第一上拉节点Q充电以使其为高电平。
在一些实施例中，消隐输入子电路210配置成从第一输入端(在下文中 也称作是“消隐输入端”)接收第一输入信号(在下文中也称作是“消隐输入信号”)，并在一帧的消隐时段将消隐输出控制信号(在下文中也称作是“消隐上拉信号”)输入到第一上拉节点Q。
在一些实施例中，消隐输入子电路210可以配置成接收并存储消隐输入信号，并在一帧的消隐时段期间根据消隐输入信号向第一上拉节点Q输出消隐上拉信号，从而将第一上拉节点Q的电位上拉到工作电位。
例如，消隐输入子电路210可以在一帧的显示时段期间接收消隐输入信号并根据消隐输入信号存储消隐上拉控制信号，并在这一帧的消隐时段期间根据消隐上拉控制信号向第一上拉节点Q输出消隐上拉信号，从而将第一上拉节点Q的电位上拉到工作电位。又例如，消隐输入子电路210可以在一帧的消隐时段期间接收消隐输入信号并存储消隐上拉控制信号，并在下一帧的消隐时段期间根据消隐上拉控制信号向第一上拉节点Q输出消隐上拉信号，从而将第一上拉节点Q的电位上拉到工作电位。
在一些实施例中，显示输入子电路220配置成在一帧的显示时段从第二输入端(在下文中也称作“显示输入端”)接收第二输入信号(在下文中也称作“显示输入信号”)，并将显示输出控制信号(在下文中也称作“显示上拉信号”)输入到第一上拉节点Q，从而将第一上拉节点Q的电位上拉到工作电位。
输出子电路230配置成在第一上拉节点Q的控制下，经由输出端输出复合输出信号。例如，复合输出信号可以包括显示输出信号和消隐输出信号，其中显示输出信号和消隐输出信号可以是具有不同宽度和时序的相互独立的两个波形。
在一些实施例中，在一帧的显示时段期间，输出子电路230配置成在第一上拉节点Q的控制下经由输出端输出显示输出信号。在一帧的消隐时段期间，输出子电路230配置成在第一上拉节点Q的控制下经由输出端输出消隐输出信号。
根据本公开实施例的移位寄存器，用于控制输出子电路在消隐时段输出消隐输出信号的消隐输入子电路和用于控制输出子电路在显示时段输出显示输出信号的显示输入子电路可以共用同一个上拉节点Q以及同一个输出子电路，从而实现更小尺寸的移位寄存器结构。
图3a-3e示出了根据本公开的实施例的显示输入子电路220的示例性的电路结构。如图3a-图3e中所示出的，显示输入子电路220可以具有多种不同的连接结构及控制方法。
如图所示，显示输入子电路220可以包括显示输入晶体管M5。如图3a中示出的，显示输入晶体管M5的第一极连接到显示输入端STU2，显示输入晶体管M5的第二极连接到第一上拉节点Q，显示输入晶体管M5的控制极连接到第一时钟信号线CLKA。在一些实施例中，在一帧的显示期间，在第一时钟信号线CLKA输入的第一时钟信号的控制下，显示输入晶体管M5将导通，并将显示输入端STU2输入的显示输入信号作为显示上拉信号输入到第一上拉节点Q。
如图3b和图3d中示出的，显示输入晶体管M5的第一极可以连接到高电平信号线VDD/VGH，并始终输入高电平的导通信号，显示输入晶体管M5的第二极连接到第一上拉节点Q，显示输入晶体管M5的控制极连接到显示输入端STU2。在一些实施例中，在一帧的显示期间，在显示输入端STU2输入的显示输入信号的控制下，显示输入晶体管M5将导通，并将高电平信号线VDD/VGH输入的高电平信号作为显示上拉信号输入到第一上拉节点Q。
又例如，如图3c中示出的，显示输入晶体管M5的第一极和控制极相连接，并连接到显示输入端STU2，显示输入晶体管M5的第二极连接到第一上拉节点Q。在一些实施例中，在一帧的显示期间，在显示输入端STU2输入的显示输入信号的控制下，显示输入晶体管M5将导通，并同时将显示输入信号线STU2输入的显示输入信号作为显示上拉信号输入到第一上拉节点Q。
显示子电路220还可以包括第二显示输入晶体管M16，其连接在显示输入晶体管M5和第一上拉节点Q之间。例如，如图3e中示出的，第二显示输入晶体管M16的第一极和控制极相连，并连接显示输入晶体管M5的第二极，第二显示输入晶体管M16的第二极连接第一上拉节点Q。
利用图3e中示出的显示输入电路，当显示输入晶体管在显示输入端的控制下导通时，可以防止高电平的信号输入到第一上拉节点Q时，由于电路中的电容耦合而在输出端产生的毛刺。
图3f示出了输出端产生毛刺的仿真示意图。如前所述，当利用如图3b中的高电平信号线VDD直接将第一上拉节点Q处的电位上拉到高电平时，输出端OUT处由于电路中的电容耦合，可能出现大的毛刺，这样的毛刺可能会使该行移位寄存器输出错误的输出信号，从而导致移位寄存器工作不正常。
图3g示出了改进后的输出端的仿真示意图。当显示子电路220进一步包括第二显示输入晶体管M16时，VDD输入的高电平信号不直接拉高第一上拉节点Q，而是经过串联的第二显示输入晶体管M16实现对第一上拉节点Q的电位拉升，从而缓解了电路中电容的耦合效应，并从而减轻了输出端OUT处的毛刺现象。
图4a-图4c示出了根据本公开的实施例的输出子电路230的示例性的电路结构。
如图4a所示，输出子电路230可以包括输出晶体管M11和输出电容C2。其中输出晶体管M11的第一极连接第四时钟信号线CLKD，输出晶体管M11的第二极连接输出端CR/OUT，输出晶体管M11的控制极连接第一上拉节点Q。输出电容的第一端连接第一上拉节点Q，输出电容的第二端连接输出端CR/OUT。输出电容C2用于存储并维持第一上拉节点Q的电位。当第一上拉节点Q的电位维持在高电平时，输出晶体管M11在第一上拉节点Q的控制下导通，并将第四时钟信号线CLKD输入的信号作为输出信号从输出端CR/OUT输出。其中CR/OUT输出的信号可以同时作为像素电路的驱动信号，也可以作为栅极驱动电路的移位驱动信号。
在一些实施例中，为了增加移位寄存器的驱动能力，输出子电路230可以进一步包括两个输出端。例如，如图4b所示，输出子电路230可以包括第一输出晶体管M11和第二输出晶体管M13。其中第一输出晶体管M11的第一极连接第四时钟信号线CLKD，第一输出晶体管M11的第二极连接第一输出端CR，第一输出晶体管M11的控制极连接第一上拉节点Q。第二输出晶体管M13的第一极连接第五时钟信号线CLKE，第二输出晶体管M13的第二极连接第二输出端OUT1，第二输出晶体管M13的控制极连接第一上拉节点Q。其中可以将第一输出端CR输出的信号用作栅极驱动电路的移位驱动信号，将第二输出端OUT1输出的信号用作像素电路的驱动信号。其中第四 时钟信号线CLKD和第五时钟信号线CLKE可以是不同的时钟信号线，也可以是相同的时钟信号线。
在另一些实施例中，输出子电路230可以进一步包括多个输出端。例如，如图4c所示，输出子电路230进一步包括第三输出晶体管M15，第三输出晶体管M15的第一极连接第六时钟信号线CLKF，第三输出晶体管M15的第二极连接第三输出端OUT2，第三输出晶体管M15的控制极连接第一上拉节点Q。其中第六时钟信号线CLKF可以是与第四时钟信号线CLKD、第五时钟信号线CLKE相同的时钟信号线，也可以是与其不同的时钟信号线。
利用图4c中示出的输出子电路，可以向像素电路提供两路不同的驱动信号，增加像素电路的驱动方式的灵活性。例如，对于3T1C型的像素电路，可以分别提供用于扫描晶体管和感测晶体管的驱动信号。
尽管以上仅示出了移位寄存器包括一个、两个、三个输出端的实例，本领域技术人员可以理解，根据本公开的原理，可以根据实际情况设置更多个输出端。上述示例不应构成对本公开保护范围的限制。
图5示出了根据本公开的实施例的移位寄存器的另一结构的示意框图。如图5所示，移位寄存器400包括消隐输入子电路410，显示输入子电路420以及输出子电路430。其中显示输入子电路420和输出子电路430可以是如图2、图3a到图3g示出的显示输入子电路220与输出子电路230及其变型，在此不再赘述。
如图5所示，消隐输入子电路410可以包括充电子电路411、存储子电路412以及隔离子电路413。
充电子电路411配置成根据消隐输入信号对消隐上拉控制节点H进行充电。在一些实施例中，充电子电路411可以接收消隐输入信号，并在消隐输入信号的控制下将高电平的消隐上拉控制信号输入到消隐上拉控制节点H。
存储子电路412的一端连接消隐上拉控制节点H，配置成存储消隐上拉控制信号。
隔离子电路413配置成在一帧的消隐时段，根据消隐上拉控制信号将消隐上拉信号输入到所述第一上拉节点Q。在一些实施例中，隔离子电路413设置在第一上拉节点Q和消隐上拉控制节点H之间，用于防止第一上拉节点Q与消隐上拉控制节点H的互相影响。例如，在不需要输出消隐上拉信号时， 隔离子电路413可以断开第一上拉节点Q与消隐上拉控制节点H之间的连接。
根据本公开实施例的移位寄存器，可以实现在不同时段通过消隐输入子电路和显示输入子电路分别控制第一上拉节点Q，从而实现消隐输入子电路和显示输入子电路共用同一个输出单元实现复合输出信号的输出。
图6a-6f示出了根据本公开的实施例的消隐输入子电路的示例性的电路结构。如图6a-6f中所示出的，消隐输入子电路410可以有多种不同的连接结构及控制方法。
充电子电路411可以包括充电晶体管M1，配置成根据消隐输入信号对消隐上拉控制节点H进行充电。充电晶体管M1的第一极和/或控制极连接所述消隐输入端，充电晶体管M1的第二极连接所述消隐上拉控制节点。
在一些实施例中，充电子电路411可以配置成将消隐输入信号输入到消隐上拉控制节点H。例如，如图6a(或图6c、图6d、图6f)中示出的，充电晶体管M1的第一极连接消隐输入端STU1，充电晶体管M1的第二极连接消隐上拉控制节点H，充电晶体管M1的控制极连接第二时钟信号线CLKB。其中，当第二时钟信号线CLKB输入高电平的导通信号时，充电晶体管M1在第二时钟信号线CLKB输入的第二时钟信号的控制下导通，并将消隐输入端STU1输入的消隐输入信号输入到消隐上拉控制节点H。又例如，如图6e中示出的，充电晶体管M1的控制极和第一极相连接，并连接到消隐输入信号线STU1，充电晶体管M1的第二极连接到消隐上拉控制节点H。其中，当消隐输入端STU1输入高电平的导通信号时，充电晶体管M1在导通信号的控制下导通，并将消隐输入端STU1输入的消隐输入信号输入到消隐上拉控制节点H。
在另一些实施例中，充电子电路可以配置成在消隐输入信号的控制下将高电平的消隐上拉控制信号输入到消隐上拉控制节点H。例如，充电晶体管M1的第一极可以连接高电平信号线VDD，充电晶体管M1的第二极连接消隐上拉控制节点H，充电晶体管M1的控制极连接消隐输入端STU1。其中，当消隐输入端STU1输入高电平的导通信号时，充电晶体管M1在消隐输入端STU1输入的消隐输入信号的控制下导通，并将VDD输入的高电平信号作为消隐上拉控制信号输入到消隐上拉控制节点H。
存储子电路412可以包括第一电容C1，配置成存储消隐上拉控制信号。第一电容C1的一端连接消隐上拉控制节点H。如图6a所示，第一电容C1的第一端连接消隐上拉控制节点H，第一电容C1的第二端连接第一信号端VSS1。其中VSS1可以输入低电平信号。如前所述，当充电子电路将消隐上拉控制信号输入到消隐上拉控制节点H时，可以对第一电容充电并将消隐上拉控制节点H的点位维持在高电平。
第一电容C1还可以有其他连接方式。例如，如图6c中所示出的，第一电容C1的第一端连接消隐上拉控制节点H，第一电容C1的第二端连接隔离子电路413的一端(如第三时钟信号线CLKC)。又例如，如图6d中示出的，第一电容C1的第一端连接消隐上拉控制节点H，第一电容C1的第二端连接隔离子电路413中的一点(如第一隔离晶体管M3和第二隔离晶体管M4的连接点N)。
隔离子电路413可以包括第一隔离晶体管M3和第二隔离晶体管M4。在一些实施例中，隔离子电路413配置成在消隐上拉控制节点的控制下将消隐上拉信号输出到第一上拉节点Q。
例如，如图6a(或6c、6d、6e)所示，其中，第一隔离晶体管M3的第一极连接第三时钟信号线CLKC，第一隔离晶体管M3的第二极连接第二隔离晶体管M4的第一极，控制极连接消隐上拉控制节点H。第二隔离晶体管M4的第二极连接第一上拉节点Q，第二隔离晶体管M4控制极连接第三时钟信号线CLKC。当消隐上拉控制节点H在存储子电路的控制下维持在高电平时，第一隔离晶体管M3在消隐上拉控制节点H的控制下导通。当第三时钟信号线CLKC输入高电平的导通信号时，第二隔离晶体管M4在导通信号的控制下导通，并将第三时钟信号线CLKC输入的高电平信号作为消隐上拉信号输入到第一上拉节点Q。
又例如，如图6b所示，第一隔离晶体管M3的第一极可以连接高电平信号线VDD。当消隐上拉控制节点H在存储子电路的控制下维持在高电平时，第一隔离晶体管M3在消隐上拉控制节点H的控制下导通。当第三时钟信号线CLKC输入高电平的导通信号时，第二隔离晶体管M4在导通信号的控制下导通，并将高电平信号线VDD输入的高电平信号作为消隐上拉信号输入到第一上拉节点Q。
在一些实施例中，隔离子电路413配置成将消隐上拉控制节点处存储的高电平信号作为消隐上拉信号输出到第一上拉节点Q。
例如，如图6f所示，隔离子电路413包括第一隔离晶体管M3，第一隔离晶体管M3的第一极连接消隐上拉控制节点H，第一隔离晶体管M3的第二极连接第一上拉节点Q，控制极连接第三时钟信号线CLKC。当第三时钟信号线CLKC输入高电平的导通信号时，第一隔离晶体管M3在导通信号的控制下导通，并将消隐上拉控制节点H处存储的高电平的消隐上拉控制信号作为消隐上拉信号输入到第一上拉节点Q。
如前所述，充电子电路411、存储子电路412以及隔离子电路413可以分别具有多种不同的连接方式。尽管图6a-6f中仅示出了六种示例性的连接方式，本领域技术人员可以理解，根据上述的本公开的原理，可以将前述的充电子电路411、存储子电路412以及隔离子电路413的各种变型进行任意组合。
图7示出了根据本公开的实施例的移位寄存器的再一结构的示意框图。如图7所示，移位寄存器400可以包括消隐输入子电路410，显示输入子电路420、输出子电路430、下拉控制子电路440、下拉子电路450、显示复位子电路460、消隐复位子电路470以及初始复位子电路480。其中消隐输入子电路410、显示输入子电路420和输出子电路430可以是如图2-图5中示出的消隐输入子电路210/310、显示输入子电路220/320以及输出子电路230/330及其变型，在此不再赘述。
如图7所示，移位寄存器400还可以包括下拉控制子电路440，其配置成根据第一上拉节点Q控制下拉节点QB的电位。例如，当第一上拉节点Q的电位处于高电平时，下拉控制子电路440可以在第一上拉节点Q的控制下将下拉节点QB下拉到低电平。又例如，当第一上拉节点Q的电位处于低电平时，下拉控制子电路440可以在第一上拉节点Q的控制下将下拉节点QB上拉至高电平。
移位寄存器400还可以包括下拉子电路450，其配置成在下拉节点QB的控制下，将第一上拉节点Q和输出端OUT下拉为非工作电位。例如，当输出端OUT不输出信号时，可以通过控制下拉节点QB的电位将第一上拉节点Q和输出端OUT下拉为非工作电位，从而降低移位寄存器电路中输出端 的噪声。
在一些实施例中，移位寄存器400还可以包括显示复位子电路460，其配置成在显示复位控制信号的控制下对第一上拉节点Q进行复位。在一些实施例中，当移位寄存器400在一帧的显示时段期间输出显示输出信号后，在显示时段结束之前，可以通过显示复位子电路460接收显示复位控制信号，从而将第一上拉节点Q的电位下拉至低电平。
在一些实施例中，移位寄存器400还可以包括消隐复位子电路470，其配置成在一帧的消隐时段结束前对第一上拉节点Q和/或输出端OUT进行复位。在一些实施例中，当移位寄存器400在一帧的消隐时段期间输出消隐输出信号后，在消隐时段结束之前，可以通过消隐复位子电路470接收消隐复位控制信号，从而将第一上拉节点Q的电位下拉至低电平。在另一些实施例中，还可以通过消隐复位子电路470将输出端OUT的电位也下拉至低电平，从而降低移位寄存器电路中输出端的噪声。
在一些实施例中，移位寄存器400还可以包括初始复位子电路480，其配置成在移位寄存器400开始工作之前，接收初始复位控制信号，并对消隐上拉控制节点H进行复位。
本领域技术人员可以理解，尽管图7中的移位寄存器示出了下拉控制子电路440、下拉子电路450、显示复位子电路460、消隐复位子电路470以及初始复位子电路480，然而上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不使用上述各子电路中的一个或多个，基于前述各子电路的各种组合变型均不脱离本公开的原理，对此不再加以赘述。
根据本公开提供的移位寄存器，可以实现在不同时段通过消隐输入子电路和显示输入子电路分别控制第一上拉节点Q，从而实现消隐输入子电路和显示输入子电路共用同一个输出单元实现复合输出信号的输出。并且，通过在非输出时段控制输出端和上拉节点的电位，可以降低移位寄存器的噪声。
图8示出了根据本公开的实施例的移位寄存器的一种示例性的电路结构。其中，图8中示出的消隐输入子电路410、显示输入子电路420以及输出子电路430与图2-图5中示出的消隐输入子电路、显示输入子电路和输出子电路是相同的，在此不再赘述。
如图8所示，下拉控制子电路440可以包括第一下拉控制晶体管M7，第一下拉控制晶体管M7的控制极与第一极相连接，并连接到第七时钟信号线CLKM，第一下拉控制晶体管M7的第二极连接下拉节点QB。在移位寄存器400的工作期间，第七时钟信号线CLKM可以始终输入高电平的导通信号。下拉控制子电路440还可以包括第二下拉控制晶体管M8，第二下拉控制晶体管M8的第一极连接下拉节点QB，第二下拉控制晶体管M8的第二极连接第四信号端VSS4，控制极连接第一上拉节点Q。其中，第四信号端VSS4可以输入低电平的非导通信号。当第一上拉节点Q处于高电平时，第二下拉控制晶体管M8将在第一上拉节点Q的控制下导通，通过设计第一下拉控制晶体管M7和第二下拉控制晶体管M8的沟道宽长比，可以将下拉节点QB的电位下拉到低电平。当第一上拉节点Q处于低电平时，第二下拉控制晶体管M8将在第一上拉节点Q的控制下关断。此时，第七时钟信号线CLKM输入的高电平信号将输入到下拉节点QB，并将下拉节点QB的电位上拉至高电平。
在上述实施例中，第七时钟信号线CLKM在移位寄存器的工作期间始终输入高电平的信号，因此第一下拉控制晶体管M7始终处于导通状态。为了避免晶体管长期导通引起的性能漂移，下拉控制子电路440还可以包括第三下拉控制晶体管M10，第三下拉控制晶体管M10的控制极与第一极相连接，并连接到第八时钟信号线CLKN，第三下拉控制晶体管M10的第二极连接下拉节点QB。可以看出，第三下拉控制晶体管M10和第一下拉控制晶体管M7的结构相同。在移位寄存器的工作过程中，可以交替使用第三下拉控制晶体管M10和第一下拉控制晶体管M7实现下拉控制子电路440的功能。例如，当第七时钟信号线CLKM输入高电平的信号时，第八时钟信号线CLKN输入低电平的信号。因此，此时第一下拉控制晶体管M7导通，第三下拉控制晶体管M10关断。当第七时钟信号线CLKM输入低电平的信号时，第八时钟信号线CLKN输入高电平的信号。因此，此时第一下拉控制晶体管M7关断，第三下拉控制晶体管M10导通。
如图8所示，下拉子电路450可以包括第一下拉晶体管M9，第一下拉晶体管M9的第一极连接第一上拉节点Q，第一下拉晶体管M9的第二极连接第三信号线VSS3，控制极连接下拉节点QB。其中第三信号线VSS3可以 输入低电平的非导通信号。当下拉节点QB处于高电平时，第一下拉晶体管M9将在下拉节点QB的控制下导通，并将第一上拉节点Q下拉至低电平。
下拉子电路450还可以包括第二下拉晶体管M12_a，其中，第二下拉晶体管M12_a的第一极连接第一输出端CR，第二下拉晶体管M12_a的第二极连接第五信号线VSS5，第二下拉晶体管M12_a的控制极连接下拉节点QB。其中第五信号线VSS5可以输入低电平的非导通信号。当下拉节点QB处于高电平时，第二下拉晶体管M12_a将在下拉节点QB的控制下导通，并将第一输出端CR下拉至低电平。
当输出子电路包括多个输出端时，下拉子电路还可以相应地包括更多的下拉晶体管。例如，如图8中示出的，下拉子电路450还可以包括第三下拉晶体管M14_a。第三下拉晶体管M14_a的第一极连接第二输出端OUT，第三下拉晶体管M14_a的第二极连接第六信号线VSS6，第三下拉晶体管M14_a的控制极连接下拉节点QB。其中第六信号线VSS6可以输入低电平的非导通信号。当下拉节点QB处于高电平时，第三下拉晶体管M14_a将在下拉节点QB的控制下导通，并分别将第二输出端OUT下拉至低电平。
如图8所示，显示复位子电路460可以包括显示复位晶体管M6，显示复位晶体管M6的第一极连接第一上拉节点Q，显示复位晶体管M6的第二极连接第二信号线VSS2，显示复位晶体管M6的控制极连接显示复位控制端STD2。其中第二信号线VSS2可以输入低电平的非导通信号。在一帧的显示时段，当显示复位控制端STD2输入高电平的导通信号时，显示复位晶体管M6将导通，并将第一上拉节点Q下拉至低电平。
如图8所示，消隐复位子电路470可以包括第一消隐复位晶体管M15，第一消隐复位晶体管M15的第一极连接第一上拉节点Q，第一消隐复位晶体管M15的第二极连接第七信号线VSS7，第一消隐复位晶体管M15的控制极连接消隐复位控制端TRST2。其中第七信号线VSS7可以输入低电平的非导通信号。在一帧的消隐时段结束前，消隐复位控制端TRST2可以输入高电平的导通信号，此时，第一消隐复位晶体管M15将导通，并将第一上拉节点Q下拉至低电平。
在一些实施例中，消隐复位子电路470还可以包括第二消隐复位晶体管M12_b，第二消隐复位晶体管M12_b的第一极连接第一输出端CR，第二消 隐复位晶体管M12_b的第二极连接第五信号线VSS5，第二消隐复位晶体管M12_b的控制极连接消隐复位控制端TRST2。当消隐复位控制端TRST2输入高电平的导通信号时，第二消隐复位晶体管M12_b将导通，并将第一输出端CR下拉至低电平。
当输出子电路包括多个输出端时，消隐复位子电路470还可以相应地包括更多的消隐复位晶体管。例如，如图8中所示出的，消隐复位子电路470还可以包括第三消隐复位晶体管M14_b，第三消隐复位晶体管M14_b的第一极连接第二输出端OUT，第三消隐复位晶体管M14_b的第二极连接第六信号线VSS6，第三消隐复位晶体管M14_b的控制极连接消隐复位控制端TRST2。当消隐复位控制端TRST2输入高电平的导通信号时，第三消隐复位晶体管M14_b将导通，并将第二输出端OUT下拉至低电平。本领域技术人员可以理解，当输出子电路包括更多个输出端时，消隐复位子电路470可以包括更多对应于输出端，并用于对输出端复位的消隐复位晶体管。
如图8所示，初始复位子电路480可以包括初始复位晶体管M2，初始复位晶体管M2的第一端连接消隐上拉控制节点H，初始复位晶体管M2的第二极连接第一信号线VSS1，初始复位晶体管M2的控制极连接初始复位控制端TRST1。其中，第一信号线VSS1可以输入低电平的非导通信号。当初始复位控制端TRST1输入高电平的导通信号时，初始复位晶体管M2将导通，并对消隐上拉控制节点H进行复位。
需要说明的是，图8中示出的第一信号线VSS1、第二信号线VSS2、第三信号线VSS3、第四信号线VSS4、第五信号线VSS5、第六信号线VSS6和第七信号线VSS7可以是相同的信号线，也可以是不同的信号线。只要能够实现如前所述的移位寄存器的功能以及其中各晶体管的控制方式，本领域技术人员可以根据实际情况任意设置上述信号线。
图9示出根据本公开的实施例的移位寄存器的示例性的电路结构。如图9所示，下拉控制子电路440可以是反相器，反相器的输入端连接到第一上拉节点Q，反相器的输出端连接到下拉节点QB。当第一上拉节点Q处于高电平时，利用反相器，可以将下拉节点QB处的电位控制为低电平。类似地，下拉子电路的第一部分450-1也可以是反相器。当下拉节点QB处于高电平时，可以利用反相器将第一上拉节点Q处的电位控制为低电平。
在现有技术的移位寄存器中，由于OLED面板性能不稳定，需要利用外部补偿算法，在外部补偿电路中栅极驱动电路的检测阶段，输出晶体管的控制极Q点需要保持一帧以上的时间为高电平，但是由于TFT处于负偏压下，可能发生阈值电压负漂并在Q点为高电平时漏电，使得输出异常。
图10示出了根据本公开的实施例的移位寄存器的示例性的电路结构。如前所述，在本公开提供的移位寄存器中，可以利用第一电容C1维持消隐上拉控制节点H处的电位，利用输出电容C2维持第一上拉节点Q处的电位。当第一上拉节点Q和/或消隐上拉控制节点H的电位维持在高电平时，存在一些晶体管其第一极连接第一上拉节点Q和/或消隐上拉控制节点H，第二极连接低电平的信号线。即使当这些晶体管的控制极输入的是非导通信号的情况下，由于其两端之间存在电压差，也可能出现漏电的情况，从而使得移位寄存器中对于第一上拉节点Q和/或消隐上拉控制节点H的电位维持的效果变差。
以消隐上拉控制节点H点为例，如图6a所示，充电晶体管M1的第一极连接消隐输入信号线STU1，充电晶体管M1的第二极连接消隐上拉控制节点H。当消隐上拉控制节点H处于高电平，消隐输入信号线输入的是低电平的输入信号时，充电晶体管M1可能出现漏电的情况。
针对上述问题，以下将描述一种用于防漏电的移位寄存器的电路结构。
在图10示出的移位寄存器1000中，充电晶体管M1_a的第一极连接消隐输入信号线STU1，充电晶体管M1_a的第二极连接连接防漏电子电路1001，充电晶体管M1_a的控制极连接第二时钟信号线CLKB。初始复位晶体管M12_b的第一极连接防漏电子电路1001，初始复位晶体管M12_b的第二极连接第一信号线VSS1，初始复位晶体管M12_b的控制极连接初始复位控制端TRST。
如图10所示，移位寄存器1000可以包括防漏电子电路1001，其配置成用于在消隐上拉控制节点H处于高电平时，防止消隐上拉控制节点H处的电荷经由充电晶体管M1_a漏电到消隐输入信号线STU1，或经由初始复位晶体管M12_b漏电到第一信号线VSS1。
防漏电子电路1000可以包括第一防漏电晶体管M1_b以及第二防漏电晶体管M15。其中第一防漏电晶体管M1_b的第一极连接消隐上拉控制节点H， 第一防漏电晶体管M1_b的第二极连接充电晶体管M1_a的第二极，第一防漏电晶体管M1_b的控制极连接M1_a的控制极。第二防漏电晶体管M15的第一极连接第一防漏电晶体管M1_b的第一极，第二防漏电晶体管M15的第二极连接防漏电信号输入端VA，第二防漏电晶体管M15的控制极连接消隐上拉控制节点H。其中，防漏电信号输入端VA可以输入高电平的信号。当消隐上拉控制节点H处于高电平时，第二防漏电晶体管M15在消隐上拉控制节点H的控制下导通，并将防漏电信号输入端VA输入的高电平信号输入到第一防漏电晶体管M1_b的第一极，从而使得第一防漏电晶体管M1_b的第一极和第二极都处于高电平的状态，防止从消隐上拉控制节点H处的电荷通过第一防漏电晶体管M1_b漏电。此时，由于充电晶体管M1_a的控制极连接M1_b的控制极，因此第一防漏电晶体管M1_b和充电晶体管M1_a的结合可以实现与前述的充电晶体管相同的效果，并同时具有防漏电的效果。
类似地，当移位寄存器1000中还可以包括第三防漏电晶体管M2_a，第三防漏电晶体管M2_a的第一极连接到消隐上拉控制节点H，第三防漏电晶体管M2_a的第二极连接到初始复位晶体管M12_b的第一极，第三防漏电晶体管M2_a的控制极连接到初始复位晶体管M12_b的控制极。第三防漏电晶体管M2_a的工作原理与第一防漏电晶体管M1_b的工作原理相同，并可以实现防止消隐上拉控制节点H处的电荷通过初始复位晶体管M2_b向低电平的信号端VSS1漏电的效果。
类似地，对于连接到第一上拉节点Q的输入晶体管M5_a、第二隔离晶体管M4_a、显示复位晶体管M6_b、第一下拉晶体管M9_b，可以采用与前述相同原理的防漏电子电路实现防漏电的效果。
例如，移位寄存器1000可以进一步包括第二防漏电子电路1002。其中，针对上述每个单独的与第一上拉节点Q相连接的晶体管，第二防漏电子电路1002可以包括用于防漏电的晶体管M4_b、M5_b、M9_a以及M6-a，其结构与原理和第一防漏电子电路1001中示出的第一防漏电晶体管M1_b和第三防漏电晶体管M2_a的结构与原理是相同的。例如，第二防漏电子电路1002可以包括晶体管M16，M16的第一极连接用于防漏电的晶体管M4_b、M5_b、M9_a以及M6-a的一极，M16的第二极连接防漏电信号输入端VA，M16的控制极连接第一上拉节点Q。其中，防漏电信号输入端VA可以输入高电平 的信号。
本领域技术人员可以理解，根据本公开提供的防漏电的原理的实施例，可以根据实际情况选择移位寄存器电路中的一个或多个晶体管增加防漏电的结构。图10仅示出了包括防漏电结构的一种示例性的电路结构，而不构成对本公开保护范围的限制。
图11示出了根据本公开的实施例的移位寄存器的示例性的电路结构。在图11中示出的移位寄存器1100中的隔离子电路采用的是如图6f中所示的隔离子电路的结构，其中第一上拉节点Q与消隐上拉控制节点H通过隔离晶体管M3相连接。因此，当第一上拉节点Q和消隐上拉控制节点H的电位不同时(例如，第一上拉节点Q和消隐上拉控制节点H中的一个处于高电平，另一个处于低电平)，可能出现第一上拉节点Q和消隐上拉控制节点H之间发生漏电的情况。
为了防止第一上拉节点Q和消隐上拉控制节点H出现漏电的情况，可以采用图11中示出的示例性的电路结构。如图11所示，移位寄存器可以包括第一防漏电子电路1101和第二防漏电子电路1102。
第一防漏电子电路1101可以包括第一防漏电晶体管M3_a和第二防漏电晶体管M15。其中，第一防漏电晶体管M3_a的第一极连接到消隐上拉控制节点H，第一防漏电晶体管M3_a的第二极连接到隔离晶体管M3_b的第一极，第一防漏电晶体管M3_a的控制极连接到隔离晶体管M3_b的控制极。第二防漏电晶体管M15的第一极连接到防漏电信号输入端VA，第二防漏电晶体管M15的第二极连接到第一防漏电晶体管M3_a的第二极，第二防漏电晶体管M15的控制极连接到消隐上拉控制节点H。其中，当消隐上拉控制节点H处于高电平时，第二防漏电晶体管M15可以在消隐上拉控制节点H的控制下导通，并将防漏电信号输入端VA输入的高电平信号输入到第一防漏电晶体管M3_a的第二极(即，图11中的A点)。
利用第一防漏电子电路1101可以实现当消隐上拉控制节点H处于高电平时，防止消隐上拉控制节点H处经过隔离晶体管M3向第一上拉节点Q的漏电。
第二防漏电子电路1102可以包括第三防漏电晶体管M3_c和第四防漏电晶体管M16。其中，第三防漏电晶体管M3_c的第一极连接到第一上拉节点 Q，第三防漏电晶体管M3_c的第二极连接到隔离晶体管M3_b的第二极，第三防漏电晶体管M3_c的控制极连接到隔离晶体管M3_b的控制极。第四防漏电晶体管M16的第一极连接到防漏电信号输入端VA，第四防漏电晶体管M16的第二极连接到第三防漏电晶体管M3_c的第二极，第四防漏电晶体管M16的控制极连接到第一上拉节点Q。其中，当第一上拉节点Q处于高电平时，第四防漏电晶体管M16可以在第一上拉节点Q的控制下导通，并将防漏电信号输入端VA输入的高电平信号输入到第三防漏电晶体管M3_c的第二极(即，图11中的B点)。
利用第二防漏电子电路1102可以实现当第一上拉节点Q处于高电平时，防止第一上拉节点Q处经过隔离晶体管M3向消隐上拉控制节点H的漏电。
因此，利用本公开的实施例提供的防漏电子电路的结构，可以防止当第一上拉节点Q与消隐上拉控制节点H电位不同时可能出现的漏电的情况。
如前所述的移位寄存器中的电容，既可以是电容器，也可以是晶体管的耦合电容。
图12示出了根据本公开的实施例的栅极驱动电路的示意性的框图。如图12所示，该栅极驱动电路包括多级级联的移位寄存器，其中任意一级或多级的移位寄存器可以采用如图2-11之一所示的移位寄存器的结构或其变型。
根据图12所示的栅极驱动电路的移位寄存器的级联结构，其中，第i级的移位寄存器的显示输入端STU2和消隐输入端STU1与第i-1级的移位寄存器的输出端CR连接，第i级的移位寄存器的输出端CR与第i-1级的移位寄存器的显示复位端STD2连接，其中N为大于2的整数，1<i≤N。第1级的移位寄存器的显示输入端STU2连接到显示信号线，消隐输入端连接到消隐信号线；第N级的移位寄存器的显示复位控制端STD2与显示复位信号线连接。
每一行移位寄存器分别连接到第二时钟信号线CLKB以及第三时钟信号线CLKC。每一行移位寄存器还可以连接到初始复位信号线TRST。其中，奇数行移位寄存器分别连接到第一时钟信号线CLKA_o、第四时钟信号线CLKD_o，偶数行移位寄存器分别连接到第一时钟信号线CLKA_e、第四时钟信号线CLKD_e。
图13中示出了根据本公开的实施例的栅极驱动电路的示例性的电路结 构。图13中示出的栅极驱动电路中级联的移位寄存器可以由前述任一移位寄存器的变型进行替换，在此不再加以赘述。
如图13所示，其中，奇数行的移位寄存器的充电晶体管的控制端连接第二时钟信号线CLKB，偶数行的移位寄存器的充电晶体管的控制端连接第三时钟信号线CLKC。
图14a示出了根据本公开的实施例的栅极驱动电路的驱动时序图。图14a示出的驱动时序图适用于图12-13示出的栅极驱动电路。以下，以图8中示出的移位寄存器作为示例，描述包括多级级联的移位寄存器构成的栅极驱动电路的驱动时序。
其中，图14a中示出的驱动时序中，CLKA_odd表示栅极驱动电路中奇数行(例如，第1、3、5…行)的移位寄存器的第一时钟信号线CLKA，CLKA_even表示栅极驱动电路中偶数行(例如，第2、4、6…行)的移位寄存器的第一时钟信号线CLKA。类似地，CLKD_odd表示栅极驱动电路中奇数行(例如，第1、3、5…行)的移位寄存器的第四时钟信号线CLKD，CLKD_even表示栅极驱动电路中偶数行(例如，第2、4、6…行)的移位寄存器的第四时钟信号线CLKD。Q_1H表示栅极驱动电路中第一行移位寄存器中第一上拉节点Q处的电位变化，Q_2H表示栅极驱动电路中第二行移位寄存器中第一上拉节点Q处的电位变化。OUT_1H表示栅极驱动电路中第一行移位寄存器中输出端OUT处的电位变化，OUT_2H表示栅极驱动电路中第二行移位寄存器中输出端OUT处的电位变化。
图14a中示出的STU1、STU2分别代表第一行移位寄存器连接的消隐输入信号和显示输入信号，STD2代表最后一行移位寄存器连接的显示复位控制信号。
如图14a所示，在移位寄存器开始工作之前，第七时钟信号线CLKM和第八时钟信号线CLKM中的一个输入高电平的导通信号，另一个输入低电平的非导通信号。因此，此时各行移位寄存器的下拉节点QB被维持在高电平状态，第一上拉节点Q被维持在低电平的状态。当栅极驱动电路开始工作时，在显示第一帧之前，栅极驱动电路可以接收初始复位控制信号TRST1，并通过初始复位子电路对栅极驱动电路中的各移位寄存器的消隐上拉控制节点进行复位。
图14b示出了根据本公开的移位寄存器的用于初始复位的另一驱动时序图。在一些实施例中，移位寄存器可以省略初始复位子电路以及初始复位信号线TRST1。此时，可以利用第二时钟信号线CLKB和第三时钟信号线CLKC对消隐上拉控制节点H进行初始复位。例如，如图14b所示，可以通过在在显示第一帧之前先输入高电平的第二时钟信号CLKB，再输入高电平的第三时钟信号CLKC，从而实现对每一行移位寄存器的消隐上拉控制节点H的复位。又例如，也可以通过在显示第一帧之前先输入高电平的第三时钟信号CLKC，再输入高电平的第二时钟信号CLKB，从而实现对每一行移位寄存器的消隐上拉控制节点H的复位。再例如，如图14c所示，也可以通过同时输入高电平的第二时钟信号CLKB和第三时钟信号CLKC，实现对每一行移位寄存器的消隐上拉控制节点H的复位。
在一些实施例中，当移位寄存器包括消隐复位子电路时(如图8中示出的消隐复位子电路470)，还可以在显示第一帧之前利用消隐复位子电路对第一上拉节点Q进行复位。此时，可以通过消隐复位控制端TRST2输入高电平的信号。例如，如图14b、图14c所示，可以在输入高电平的第二时钟信号和第三时钟信号作为初始复位信号实现对消隐上拉控制节点H的复位的同时，输入高电平的消隐复位信号，从而实现对第一上拉节点Q的初始复位。在这里，TRST2输入的高电平的信号可以覆盖第二时钟信号线CLKB和第三时钟信号线CLKC输入的高电平信号。也就是说，TRST2输入的初始复位信号的上升沿早于第二时钟信号线CLKB和第三时钟信号线CLKC输入的各高电平信号的上升沿，下降沿晚于第二时钟信号线CLKB和第三时钟信号线CLKC输入的各高电平信号的下降沿。
利用上述初始复位的驱动方法，可以进一步简化移位寄存器的电路结构。
本领域技术人员可以理解，下文中描述的移位寄存器的驱动方法中都可以应用图14b、图14c中示出的初始复位驱动方法。
在第一帧的显示阶段，第一行移位寄存器从其显示输入端STU2接收用于显示输入的高电平的信号。此时，显示输入子电路可以根据显示输入信号向第一上拉节点Q输出显示上拉信号，并将第一上拉节点Q的电位上拉至高电平。之后，输出子电路从第一行的第四时钟信号线CLKD_odd接收高电平的信号输入。此时，由于输出晶体管M11、M13在第一上拉节点Q的控制 下导通，因此，第四时钟信号线CLKD输入的高电平信号可以经由输出晶体管M11、M13作为显示输出信号从输出端CR、OUT_1H输出。
由于第一行移位寄存器的显示输出信号可以作为第二行移位寄存器的显示输入信号，因此，如图13所示的级联的多个移位寄存器将逐行完成显示信号的输出。例如，如图14a中所示出的，第一行移位寄存器的输出端输出信号OUT_1H，然后，第二行移位寄存器的输出端输出信号OUT_2H，以此类推，在此不再赘述。
对于第一行移位寄存器，其显示复位控制端连接到第二行移位寄存器的输出端。因此，当第二行移位寄存器输出显示输出信号OUT_2H时，第一行移位寄存器的第一上拉节点Q被复位至低电平。
以此类推，之后各行移位寄存器的第一上拉节点Q在输出显示输出信号之后被复位至低电平。最后一行移位寄存器的第一上拉节点Q将根据显示复位控制信号STD2的控制下进行复位。
至此，第一帧的显示时段结束。
在第一帧的消隐阶段，第一行移位寄存器接收消隐输入端STU1和第二时钟信号线CLKB输入的高电平的信号，第二时钟信号线CLKB输入高电平信号，因此，充电晶体管M1被导通，并通过充电晶体管M1将消隐上拉控制节点H的电位上拉至高电平。由于第一电容C1的存在，消隐上拉控制节点H将保持高电平的状态。
在第一帧的消隐阶段结束前，移位寄存器可以通过消隐复位信号线接收消隐复位信号，从而对第一上拉节点Q和/或输出端的电位进行复位。
至此，第一帧的驱动时序结束。
在第二帧的显示阶段，各行移位寄存器重复与第一帧的显示阶段相同的移位寄存器的驱动时序，并逐行输出像素电路的驱动信号，在此不再加以赘述。
在第二帧的消隐期间，对于第一行移位寄存器，第三时钟信号线CLKC输入高电平信号，由于消隐上拉控制节点H处于高电平状态，第一隔离晶体管M3是导通的，因此利用第三时钟信号线CLKC输入的高电平信号可以将第一上拉节点Q的电位上拉至高电平。同时，第四时钟信号线CLKD输出高电平信号。此时，由于输出晶体管M3在第一上拉节点Q的控制下导通，因 此，可以经由输出端输出第四时钟信号线CLKD输入的高电平信号作为消隐输出信号。
如图12、13中示出的，第一行移位寄存器的输出端CR连接到第二行移位寄存器的消隐输入端，因此，第一行移位寄存器的消隐输出信号可以作为第二行移位寄存器的消隐输入信号，并将第二行移位寄存器的消隐上拉控制节点H的电位上拉至高电平。
在第二帧的消隐阶段结束前，移位寄存器可以通过消隐复位信号线接收消隐复位信号，从而对第一上拉节点Q和/或输出端的电位进行复位。
至此，第二帧的驱动时序结束。
在第三帧的显示阶段，重复第一帧显示阶段的移位寄存器的驱动时序，逐行输出像素电路的驱动信号，在此不再加以赘述。
在第三帧的消隐时段，第二时钟信号线CLKB输入高电平的时钟信号，第二行移位寄存器重复第一行移位寄存器在第二帧的消隐阶段的驱动时序，并从第二行移位寄存器输出消隐输出信号。如前所述，第二行移位寄存器输出的消隐输出信号可以用于将第三行移位寄存器的消隐上拉控制节点H的电位上拉至高电平。
对于第一行移位寄存器来说，此时第二时钟信号线CLKB输入高电平的时钟信号，充电晶体管M1在该高电平的时钟信号的控制下导通。并且，此时第一行移位寄存器的消隐输入端输入的是低电平的信号，因此，第一行移位寄存器的第一电容中存储的电荷可以经由充电晶体管放电，并将消隐上拉控制节点H的电位下拉到低电平。
在第三帧的消隐阶段结束前，移位寄存器可以通过消隐复位信号线接收消隐复位信号，从而对第一上拉节点Q和/或输出端的电位进行复位。
至此，第三帧的驱动时序结束。
如上所述，在每一帧的显示阶段，级联的移位寄存器逐行输出相应的驱动信号。从第二帧开始，在每一帧的消隐阶段，级联的移位寄存器依次输出消隐输出信号。例如，如前所述，第一行移位寄存器在第二帧的消隐阶段输出用于第一行像素电路单元的消隐输出信号，第二行移位寄存器在第三帧的消隐阶段输出用于第二行像素电路单元的消隐输出信号，以此类推。
图15示出了根据本公开的实施例的栅极驱动电路的驱动时序图。在每一 帧的显示阶段，级联的移位寄存器逐行输出相应的驱动信号。显示阶段的驱动时序与图14a中示出的相同，在此不再赘述。
在图15示出的驱动时序中，与图14a中示出的驱动时序不同的是，在图15示出的驱动时序中，第一行移位寄存器的消隐输入端在第一帧的显示阶段输入高电平的消隐输入信号，同时第三时钟信号线CLKB输入高电平信号，从而拉高第一行移位寄存器的消隐上拉控制节点H点处的电位。在第一帧的消隐阶段，第三时钟信号线CLKC输入高电平的时钟信号，第二隔离晶体管M4在CLKC输入的高电平信号的控制下导通，并将第一行移位寄存器的第一上拉节点Q的电位上拉到高电平。同时，第一行移位寄存器连接的第四时钟信号线CLKD_odd输入高电平的第四时钟信号，并将第四时钟信号作为消隐输出信号从输出端输出。
从第一帧的消隐阶段开始，如图15所示，第二时钟信号线CLKB和第三时钟信号线CLKC依次输入高电平的导通信号，从而控制各行移位寄存器依次输出消隐输出信号。
如上所述，第一行移位寄存器在第一帧的消隐阶段输出消隐输出信号，第二行移位寄存器在第二帧的消隐阶段输出消隐输出信号，以此类推。
根据本公开提供的栅极驱动电路，其中级联的移位寄存器可以实现在一帧的显示阶段逐行依次输出显示输出信号，在一帧的消隐期间，以每帧输出一行信号的频率逐行依次输出消隐输出信号。其中每行移位寄存器的显示输出信号和消隐输出信号共用一个输出晶体管。
图16示出了根据本公开的实施例的栅极驱动电路的示意性的框图。如图16所示，图中仅示出了N级级联的移位寄存器的前4级。对于2＜i＜N-1，第i行移位寄存器的消隐输入端连接到第i-1行移位寄存器的输出端，第i行移位寄存器的显示输入端连接到第i-2行移位寄存器的输出端，第i行移位寄存器的显示复位端连接到第i+2行移位寄存器的输出端。同时，第一行移位寄存器的消隐输入端和显示输入端分别连接到消隐输入信号线和第一显示输入信号线，第二行移位寄存器的显示输入端连接第二显示输入信号线，以及，第N-1行移位寄存器的显示复位端连接第一显示复位信号线，第N行移位寄存器的显示复位端连接第一显示复位信号线。
每一行移位寄存器分别连接到第二时钟信号线CLKB以及第三时钟信号 线CLKC。每一行移位寄存器还可以连接到初始复位信号线TRST。其中，奇数行移位寄存器分别连接到第一时钟信号线CLKA_o、第四时钟信号线CLKD_o，偶数行移位寄存器分别连接到第一时钟信号线CLKA_e、第四时钟信号线CLKD_e。
图17示出了根据本公开的实施例的栅极驱动电路的驱动时序图。图17示出的驱动时序可以用于如图16所示的栅极驱动电路。
在图17中示出的时序图中，CLKD_1、CLKD_2、CLKD_3、CLKD_4分别代表第1、2、3、4行移位寄存器连接的第四时钟信号线。Q<1>、Q<2>分别代表第1、2行移位寄存器中第一上拉节点Q处的电位变化。OUT<1>、OUT<2>、OUT<3>、OUT<4>分别代表第1、2、3、4行移位寄存器中输出端CR、OUT处的电位变化。
如图17所示，在移位寄存器开始工作之前，第七时钟信号线CLKM和第八时钟信号线CLKM中的一个输入高电平的导通信号，另一个输入低电平的非导通信号。因此，此时下拉节点QB被维持在高电平状态，第一上拉节点Q被维持在低电平的状态。当栅极驱动电路开始工作时，在显示第一帧之前，栅极驱动电路可以接收初始复位控制信号TRST，并通过如前所述的初始复位子电路对栅极驱动电路中的每个移位寄存器的消隐上拉控制节点H进行复位。
在第一帧的显示阶段，第一行移位寄存器从其显示输入端STU2接收用于显示输入的高电平的信号。此时，显示输入子电路可以根据显示输入信号向第一上拉节点Q输出显示上拉信号，并将第一上拉节点Q的电位上拉至高电平。之后，输出子电路从第一行的第四时钟信号线CLKD_1接收高电平的信号输入。此时，由于输出晶体管M11、M13在第一上拉节点Q的控制下导通，因此，第四时钟信号线CLKD输入的高电平信号可以经由输出晶体管M11、M13作为显示输出信号从输出端CR、OUT_1H输出。
对于第二行移位寄存器，其可以从第二显示输入信号线STU2_2接收用于显示输入的高电平的信号。此时，第二行移位寄存器的显示输入子电路可以根据显示输入信号向第一上拉节点Q输出显示上拉信号，并将第一上拉节点Q的电位上拉至高电平。之后，第二行移位寄存器的输出子电路从第四时钟信号线CLKD_2接收高电平的信号输入。此时，由于输出晶体管M11、 M13在第一上拉节点Q的控制下导通，因此，第四时钟信号线CLKD_2输入的高电平信号可以经由输出晶体管M11、M13作为显示输出信号从输出端CR、OUT_1H输出。
如图17中所示出的，第二行移位寄存器连接的第四时钟信号线CLKD_2输入的时钟信号与第一行移位寄存器连接的第四时钟信号线CLKD_12输入的时钟信号的时钟宽度相同，但第二行移位寄存器连接的第四时钟信号线CLKD_2输入的时钟信号的上升沿比第一行移位寄存器连接的第四时钟信号线CLKD_1输入的时钟信号的上升沿晚半个时钟信号的宽度，相应地，第二行移位寄存器输出的显示输入信号也比第一行移位寄存器输出的显示输入信号晚半个时钟信号的宽度。此时，第一行移位寄存器的显示输出信号与第二行移位寄存器的显示输出信号之间存在50％的脉冲重叠。
由于第一行移位寄存器的显示输出信号可以作为第三行移位寄存器的显示输入信号，因此，如图16所示的级联的多个移位寄存器中的奇数级的移位寄存器将根据第一行移位寄存器的显示输出信号逐行完成显示信号的输出。类似地，如图16所示的级联的多个移位寄存器中的偶数级的移位寄存器将根据第一行移位寄存器的显示输出信号逐行完成显示信号的输出。以此类推，在此不再赘述。
通过本公开的实施例提供的栅极驱动电路，可以实现存在重叠输出的移位寄存器。
对于消隐输出信号，如图16所示，由于图中示出的级联的多个移位寄存器的消隐输出端的连接方式与图12、图13中示出的级联的多个移位寄存器的消隐输出端的连接方式相同，因此图16中示出的栅极驱动电路在消隐阶段的驱动方式与图12、图13中示出的栅极驱动电路消隐阶段的驱动方式相同，在此不再赘述。
根据图16示出的栅极驱动电路以及图17中示出的驱动时序，可以实现相邻的移位寄存器之间输出具有50％重叠的显示输出信号。本领域技术人员可以理解，利用本公开提供的原理，可以实现其他重叠比例的显示输出信号。
例如，可以将N行级联的移位寄存器划分为多个移位寄存器组，例如，栅极驱动电路中包括m组，其中每组包括n个如前所述的移位寄存器。
关于消隐输入信号，上述N行级联的移位寄存器的消隐输入信号端之间 采用逐行级联的连接方式。也就是说，第一行移位寄存器的输出端连接到第二行移位寄存器的消隐输入端，第二行移位寄存器的输出端连接到第三行移位寄存器的消隐输入端，以此类推。
关于显示输入信号，上述每一组移位寄存器组中的n个移位寄存器分别与下一组移位寄存器组中的n个移位寄存器采用逐行连接的方式。也就是说，第1组移位寄存器组中的第1个移位寄存器的输出端连接到第2组移位寄存器组中的第1个移位寄存器(即N行移位寄存器中的第n+1行)的显示输入端，第1组移位寄存器组中的第2个移位寄存器的输出端连接到第2组移位寄存器组中的第2个移位寄存器(即N行移位寄存器中的第n+2行)的显示输入端，以此类推。
如上所述的栅极驱动电路中每一行移位寄存器的显示输出信号将与下一行移位寄存器的显示输出信号具有1/n的脉冲重叠的部分。
例如，图16中示出的栅极驱动电路的显示输出信号采用的是奇数行级联，偶数行级联的连接方式以实现具有50％重叠的显示输出信号。如果采用第1、4、7…行级联，第2、5、8…行级联，第3、6、9…行级联的方式，将实现具有33％重叠的显示输出信号。本领域技术人员可以根据实际情况选择栅极驱动电路的连接方式，从而实现相邻的移位寄存器之间输出具有不同重叠比例的显示输出信号。
图18示出了根据本公开的实施例的栅极驱动电路的示意性的框图。如图18所示，图中仅示出了N级级联的移位寄存器的前4级，N是正整数。对于2＜i＜N-2，第i行移位寄存器的消隐输入端连接到第i-1行移位寄存器的输出端，第i行移位寄存器的显示输入端连接到第i-2行移位寄存器的输出端，第i行移位寄存器的显示复位端连接到第i+3行移位寄存器的输出端。同时，第一行移位寄存器的消隐输入端和显示输入端分别连接到消隐输入信号线和第一显示输入信号线，第二行移位寄存器的显示输入端连接第二显示输入信号线，以及，第N-2行移位寄存器的显示复位端连接第一显示复位信号线，第N-1行移位寄存器的显示复位端连接第二显示复位信号线。第N行移位寄存器的显示复位端连接第三显示复位信号线。
每一行移位寄存器分别连接到第二时钟信号线CLKB以及第三时钟信号线CLKC。每一行移位寄存器还可以连接到初始复位信号线TRST。其中， 奇数行移位寄存器分别连接到第一时钟信号线CLKA_o、第四时钟信号线CLKD_o，偶数行移位寄存器分别连接到第一时钟信号线CLKA_e、第四时钟信号线CLKD_e。
图18中示出的栅极驱动电路和图16中示出的栅极驱动电路的区别在于，图16中第i行移位寄存器的输出端连接到第i+2行移位寄存器的显示输入端，以及第i+2行移位寄存器的输出端连接到第i行移位寄存器的显示复位控制端。
图19示出了根据本公开的实施例的栅极驱动电路的驱动时序图。图19示出的驱动时序可以用于如图18所示的栅极驱动电路。
如前所述，图18示出的栅极驱动电路与图16中示出的栅极驱动电路的区别仅在于显示复位控制端的连接方式不同。因此，图19中示出的驱动时序中的各行移位寄存器的显示输入的驱动时序和消隐输入的驱动时序均与图17中示出的驱动时序相同，在此不再赘述。
关于显示复位阶段，根据图18、19提供的栅极驱动电路及其驱动方法，由于第一行移位寄存器的显示复位端连接到第四行移位寄存器的输出端，因此，如图19所示，当第一行移位寄存器输出显示输出信号后，第一上拉节点Q的电位维持在高电平。由于此时第四时钟信号线CLKD_1处于低电平，因此，输出端OUT处累积的电荷将经由输出晶体管向第四时钟信号线CLKD_1放电。
由于输出端OUT输出的是用于驱动像素电路的驱动信号，为了提高移位寄存器的驱动能力，因此，在现有技术的移位寄存器中，输出晶体管M13将采用体积较大的晶体管。相应地，在如图16所示的栅极驱动电路中采用的移位寄存器中，显示复位阶段，输出端OUT累积的电荷可以通过显示复位晶体管M14_a进行复位，这里的显示复位晶体管M14_a也需要采用体积较大的晶体管。
然而，根据本公开的实施例的栅极驱动电路，由于输出端OUT处累积的电荷可以经由输出晶体管M13进行放电，而不需要利用显示复位晶体管M14_a进行复位，因此，此时显示复位晶体管M14_a可以使用较小的晶体管，从而进一步减小移位寄存单元的体积。此外，由于当输出子电路的输出端处于高电平时，第一上拉节点Q的电位由于自举效应升高，因此对输出端进行 放电时流过输出晶体管M13的电流可以更大，放电速度更快。
图20示出了根据本公开实施例的用于如前所述的移位寄存器的驱动方法的流程图。如图20所示，驱动方法2000可以包括步骤2001，第一控制阶段，经由显示输入子电路将显示上拉信号输入到第一上拉节点。步骤2002，第一输出阶段，在第一上拉节点的控制下经由输出子电路输出第一输出信号。步骤2003，第二控制阶段，经由消隐输入子电路将消隐上拉信号输入到第一上拉节点。步骤2004，第二输出阶段。在第一上拉节点的控制下经由输出子电路输出第二输出信号。
在一些实施例中，驱动方法2000还可以包括步骤2002b，显示复位阶段，在显示复位控制信号的控制下对第一上拉节点进行复位。
在一些实施例中，驱动方法2000还可以包括步骤2004b，消隐复位阶段，在消隐复位控制信号的控制下对第一上拉节点进行复位。
根据本公开实施例的用于移位寄存器的驱动方法，用于控制输出子电路在消隐时段输出消隐输出信号的消隐输入子电路和用于控制输出子电路在显示时段输出显示输出信号的显示输入子电路可以共用同一个上拉节点Q以及同一个输出子电路，从而实现更小尺寸的移位寄存器结构。
除非另有定义，这里使用的所有术语(包括技术和科学术语)具有与本发明所属领域的普通技术人员共同理解的相同含义。还应当理解，诸如在通常字典里定义的那些术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
上面是对本发明的说明，而不应被认为是对其的限制。尽管描述了本发明的若干示例性实施例，但本领域技术人员将容易地理解，在不背离本发明的新颖教学和优点的前提下可以对示例性实施例进行许多修改。因此，所有这些修改都意图包含在权利要求书所限定的本发明范围内。应当理解，上面是对本发明的说明，而不应被认为是限于所公开的特定实施例，并且对所公开的实施例以及其他实施例的修改意图包含在所附权利要求书的范围内。本发明由权利要求书及其等效物限定。

Claims (20)

  1. 一种移位寄存器，包括：
    第一输入子电路，配置成从第一输入端接收第一输入信号并输出消隐输出控制信号；
    第二输入子电路，配置成从第二输入端接收第二输入信号并输出显示输出控制信号；
    输出子电路，配置成在所述第一节点的控制下，经由输出端输出复合输出信号，所述复合输出信号包括彼此独立地在显示时段输出的显示输出信号和在消隐时段输出的消隐输出信号。
  2. 根据权利要求1所述的移位寄存器，其中，
    所述第一输入子电路配置成从第一输入端接收第一输入信号，并根据第一输入信号在一帧的消隐时段将消隐输出控制信号输入到第一节点；
    所述第二输入子电路配置成从第二输入端接收第二输入信号，并根据第二输入信号在一帧的显示时段将显示输出控制信号输入到所述第一节点。
  3. 根据权利要求2所述的移位寄存器，其中，所述第一输入子电路包括：
    充电子电路，配置成根据所述第一输入信号将所述第一输入信号输入到消隐上拉控制节点；
    存储子电路，其一端连接消隐上拉控制节点，配置成根据所述第一输入信号存储消隐上拉控制信号；
    隔离子电路，配置成在一帧的消隐时段，根据所述消隐上拉控制信号将所述消隐输出控制信号输入到所述第一节点。
  4. 根据权利要求3所述的移位寄存器，还包括：
    显示复位子电路，配置成在显示复位控制信号的控制下对所述第一节点进行复位。
  5. 根据权利要求4所述的移位寄存器，还包括：
    消隐复位子电路，配置成在一帧的消隐时段结束前，在消隐复位控制信号的控制下对所述第一节点和/或所述输出端进行复位。
  6. 根据权利要求5所述的移位寄存器，其中，
    所述输出子电路包括至少一个移位信号输出端以及至少一个像素信号输出端。
  7. 根据权利要求6所述的移位寄存器，还包括：
    下拉控制子电路，配置成根据所述第一节点的控制下拉节点的电位；
    下拉子电路，配置成在所述下拉节点的控制下，将所述第一节点和所述输出端下拉为非工作电位。
  8. 根据权利要求3-7任一项所述的移位寄存器，其中，
    所述充电子电路包括充电晶体管，充电晶体管的第一极和/或控制极连接所述第一输入端，充电晶体管的第二极连接所述消隐上拉控制节点；以及
    所述存储子电路包括第一电容，第一电容的第一端连接所述消隐上拉控制节点；以及
    所述隔离子电路包括第一隔离晶体管和第二隔离晶体管，其中所述第一隔离晶体管的控制端连接所述消隐上拉控制节点，所述第二隔离晶体管的第一极连接所述第一隔离晶体管的第二极，所述第二隔离晶体管的第二极连接所述第一节点，所述第二隔离晶体管的控制极连接隔离控制信号线。
  9. 根据权利要求1-8任一项所述移位寄存器，其中，
    所述第二输入子电路包括第一显示输入晶体管，所述第一显示输入晶体管的第一极连接所述第一节点，所述第一显示输入晶体管的第二极和/或控制极连接所述第二输入端；
    所述输出子电路包括输出晶体管和输出电容，其中所述输出晶体管的第一极连接输出时钟信号线，所述输出晶体管的第二极连接输出端，所述输出晶体管的控制极连接所述第一节点，所述输出电容的第一端连接所述第一节点，所述输出电容的第二端连接所述输出端。
  10. 根据权利要求9所述的移位寄存器，其中，所述第二输入子电路还包括第二显示输入晶体管，所述第二显示输入晶体管的第一极和控制极相连，并连接到所述第一显示输入晶体管的第一极，所述第二显示输入晶体管的第二极连接所述第一节点。
  11. 根据权利要求4-10任一项所述的移位寄存器，其中，
    所述显示复位子电路包括显示复位晶体管，所述显示复位晶体管的第一极连接所述第一节点，所述显示复位晶体管的控制极连接显示复位控制端，所述显示复位晶体管的第二极连接显示复位信号线。
  12. 根据权利要求5-11任一项所述的移位寄存器，其中，所述消隐复位 子电路包括第一消隐复位晶体管，所述第一消隐复位晶体管的第一极连接所述第一节点，所述第一消隐复位晶体管的控制极连接消隐复位控制端，所述第一消隐复位晶体管的第二极连接消隐复位信号线。
  13. 根据权利要求12所述的移位寄存器，其中，所述消隐复位子电路还包括第二消隐复位晶体管，所述第二消隐复位晶体管的第一极连接所述输出端，所述第二消隐复位晶体管的控制极连接消隐复位控制端，所述第二消隐复位晶体管的第二极连接消隐复位信号线。
  14. 根据权利要求7-13任一项所述的移位寄存器，其中
    所述下拉控制子电路包括第一下拉控制晶体管和第二下拉控制晶体管，其中所述第一下拉控制晶体管的第一极和控制极相连并连接到下拉控制信号线，所述第一下拉控制晶体管第二极连接下拉节点，所述第二下拉控制晶体管的第一极连接所述下拉节点，所述第二下拉控制晶体管的控制极连接所述第一节点，所述第二下拉控制晶体管的第二极连接下拉信号线；
    所述下拉子电路包括第一下拉晶体管和第二下拉晶体管，其中所述第一下拉晶体管的第一极连接所述第一节点，所述第一下拉晶体管的控制极连接所述下拉节点，所述第一下拉晶体管的第二极连接下拉信号线，所述第二下拉晶体管的第一极连接所述输出端，所述第二下拉晶体管的控制极连接所述下拉节点，所述第二下拉晶体管的第二极连接下拉信号线。
  15. 根据权利要求8-14任一项所述的移位寄存器，还包括：
    防漏电子电路，其配置成在所述第一节点和/或所述消隐上拉控制节点的控制下，将工作电位输入到所述第二隔离晶体管的第一极和/或第二极。
  16. 一种栅极驱动电路，包括级联的N行移位寄存器，所述移位寄存器为如权利要求1-15中任一项所述的移位寄存器，其中，
    第i级的移位寄存器的第二输入端和第一输入端与第i-1级的移位寄存器的输出端连接，第i级的移位寄存器的输出端与第i-1级的移位寄存器的显示复位端连接，其中N为大于2的整数，1<i≤N；
    第1级的移位寄存器的第二输入端连接到显示信号线，第一输入端连接到消隐信号线；
    第N级的移位寄存器的显示复位控制端与显示复位信号线连接。
  17. 一种显示装置，其特征在于，包括如权利要求16所述的栅极驱动电 路。
  18. 一种应用于如权利要求1-15中任一项所述的移位寄存器的驱动方法，包括：
    在一帧的显示时段，包括
    第一控制阶段，经由第二输入子电路将显示输出控制信号输入到第一节点；
    第一输出阶段，在所述第一节点的控制下经由输出子电路输出第一输出信号；
    在一帧的消隐时段，包括
    第二控制阶段，经由第一输入子电路将消隐输出控制信号输入到所述第一节点；
    第二输出阶段。在所述第一节点的控制下经由输出子电路输出第二输出信号。
  19. 如权利要求18所述的驱动方法，还包括：
    显示复位阶段，在显示复位控制信号的控制下对所述第一节点进行复位。
  20. 如权利要求19所述的驱动方法，还包括：
    消隐复位阶段，在消隐复位控制信号的控制下对所述第一节点进行复位。
PCT/CN2018/122801 2018-02-14 2018-12-21 移位寄存器、栅极驱动电路、显示装置以及驱动方法 WO2019157863A1 (zh)

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