WO2018064869A1 - 一种量子点结构的制作方法 - Google Patents

一种量子点结构的制作方法 Download PDF

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WO2018064869A1
WO2018064869A1 PCT/CN2016/113894 CN2016113894W WO2018064869A1 WO 2018064869 A1 WO2018064869 A1 WO 2018064869A1 CN 2016113894 W CN2016113894 W CN 2016113894W WO 2018064869 A1 WO2018064869 A1 WO 2018064869A1
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quantum dot
protective film
patterned
patterned array
film layer
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French (fr)
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张子旸
黄荣
黄源清
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中国科学院苏州纳米技术与纳米仿生研究所
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Priority to US16/340,108 priority Critical patent/US10665749B2/en
Priority to JP2019518435A priority patent/JP6845926B2/ja
Publication of WO2018064869A1 publication Critical patent/WO2018064869A1/zh

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    • H01S5/00—Semiconductor lasers
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    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/341—Structures having reduced dimensionality, e.g. quantum wires
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    • H01S5/00—Semiconductor lasers
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    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
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Definitions

  • the invention belongs to the field of semiconductor quantum dots and manufacturing technologies thereof, and in particular to a method for fabricating a quantum dot structure.
  • Quantum information technology is one of the most important research directions in the field of physics.
  • the realization of quantum computing and quantum communication based on single photon state manipulation is the most important physical implementation method of quantum information technology.
  • eavesdroppers can eavesdrop through photon number splitting (PNS). Therefore, how to obtain a stable, efficient and reliable single photon source has become a bottleneck problem in the practical application of quantum communication and quantum cryptography.
  • PPS photon number splitting
  • the semiconductor quantum dot structure will be subjected to a strong three-dimensional quantum confinement effect due to its size in the three directions of X, Y and Z, and it will be subjected to a strong three-dimensional quantum confinement effect.
  • the "class-like" structure; and the semiconductor quantum dot structure also has the advantages of large wavelength tunable range and easy integration, so it is one of the ideal choices for preparing single photon emitting devices.
  • the present invention provides a method for fabricating a quantum dot structure, which uses a template selective annealing process to obtain a quantum dot structure in which the density and position of quantum dots are controllable.
  • a method for fabricating a quantum dot structure comprising: preparing a quantum dot film layer on a substrate; preparing a first protective film on the quantum dot film layer; preparing a patterned array on the first protective film; Preparing a second protective film on the first protective film and the patterned array to obtain an intermediate; annealing the intermediate to obtain a quantum dot structure on the substrate.
  • the material of the patterned array is selected from any one of TiO 2 , Al, HfO 2 , Si 3 N 4 , and SrTiO 3 ; the patterned array has a thickness of 40 nm to 300 nm, and the patterned array The length and/or width is from 10 nm to 10 ⁇ m.
  • the materials of the first protective film and the second protective film are both SiO 2 ; the first protective film has a thickness of 5 nm to 50 nm, and the second protective film has a thickness of 50 nm to 300 nm.
  • the annealing temperature of the intermediate is 550 ° C to 1000 ° C, and the annealing time is 30 s to 10 min.
  • the material of the quantum dot film layer is selected from any one of InAs, InGaAs, InGaAlAs, InSb, GaSb, and InP; the growth temperature of the quantum dot film layer is 300 ° C to 550 ° C; The thickness of the film layer is 1.4 ML to 10 ML; the density of the quantum dots in the quantum dot film layer is 10 8 cm -2 to 10 11 cm -2 .
  • the method for preparing the patterned array on the first protective film specifically includes: preparing a precursor film layer on the first protective film; and patterning the precursor film layer by using a laser direct writing process a precursor film layer forming the patterned array and a precursor residual film surrounding the patterned array; peeling off the precursor residual film, forming the pattern on the first protective film Array.
  • the material of the precursor film layer is Ti; the thickness of the precursor film layer is 40 nm to 300 nm; and the length and/or width of the patterned array is 100 nm to 500 nm.
  • the method for preparing the patterned array on the first protective film specifically includes: preparing a photoresist layer on the first protective film; and using the photolithography process or the electron beam lithography process
  • the dicing layer is patterned to form a recessed hole matching the shape of the patterned array; a patterned film layer is deposited in the recessed hole; and the photoresist layer is peeled off at the first protective film
  • the patterned array is formed thereon.
  • the material of the patterned film layer is selected from any one of TiO 2 , Al, HfO 2 , Si 3 N 4 , and SrTiO 3 ; the patterned film layer has a thickness of 40 nm to 300 nm; When the photoresist layer is patterned, the length and/or width of the patterned array is 200 nm to 10 ⁇ m; when the photoresist layer is patterned by electron beam lithography The patterned array has a length and/or a width of 10 nm to 200 nm.
  • the material of the substrate is selected from any one of GaAs, GaSb, and InP.
  • the present invention uses the patterned array as a template to form an ordered quantum dot structure by using a template selective region annealing process, and adopts a subsequent heat treatment process.
  • the fabrication method of the quantum dot structure in the technology avoids damage to the surface of the substrate, and the complete substrate surface is beneficial to reduce the defects introduced by the quantum dot structure during the growth process, thereby improving the performance of the quantum dot structure.
  • the present invention utilizes a uniform patterned array as a template pattern, which is advantageous for The uniform distribution of quantum dot structures is prepared, thereby improving the performance of quantum dot devices such as single photon devices and quantum dot lasers.
  • quantum dot structures of different densities and emission spectra can be obtained in different template regions, which are advantageous for applications in wide-spectrum devices; the present invention grows SiO 2 films of different thicknesses as the first protective film and The second protective film, under the same annealing conditions, can obtain quantum dot regions of different emission spectra, and regulate the emission spectrum of the quantum, thereby obtaining a structure having broad spectral properties on the same substrate.
  • FIGS. 1 to 7 are process flow diagrams showing a method of fabricating a quantum dot structure according to Embodiment 1 of the present invention.
  • FIGS. 8 to 10 are process flow diagrams showing a method of fabricating a quantum dot structure according to Embodiment 2 of the present invention.
  • Fig. 11 is a view showing the structure of a quantum dot structure obtained by the method for fabricating a quantum dot structure according to Embodiment 3 of the present invention.
  • Fig. 12 is a view showing the structure of a quantum dot structure obtained by the method for fabricating a quantum dot structure according to Embodiment 4 of the present invention.
  • 1 to 7 are process flow diagrams showing a method of fabricating a quantum dot structure according to the present embodiment.
  • the method for fabricating the quantum dot structure according to the embodiment includes the following steps:
  • Step 1 A quantum dot film layer 2a is prepared on the substrate 1.
  • the material of the substrate 1 is GaAs; the material of the quantum dot film layer 2a is InAs; the thickness of the quantum dot film layer 2a is 1.4 ML to 10 ML, preferably 1.4 ML to 5 ML; The density of the quantum dots in layer 2a is from 10 8 cm -2 to 10 11 cm -2 .
  • ML is a monolayer, that is, the thickness of a single layer of atoms.
  • the quantum dot film layer 2a is grown by molecular beam epitaxy SK mode, and the growth temperature is 300 ° C to 550 ° C; the specific process for preparing the quantum dot film layer 2 a with respect to the molecular beam epitaxy SK mode will not be described herein. Those skilled in the art can refer to the prior art. It is worth noting that when the quantum dot film layer 2a is prepared by the molecular beam epitaxy SK mode, the wetting layer 2b is accompanied, and the wetting layer 2b is formed on the substrate 1, and the quantum dot array in the quantum dot film layer 2a is formed. That is, "inlaid" in the wetting layer 2b, as shown in FIG.
  • the material of the substrate 1 and the quantum dot film layer 2a is not limited to the GaAs and InAs described in the embodiment; the material of the substrate 1 may also be a GaSb, InP or other semiconductor material substrate, and the quantum dot film layer 2a InGaAs, InGaAlAs, InSb, GaSb, InP, etc. can also be used as the material.
  • Step 2 A first protective film 31 is prepared on the quantum dot film layer 2a as shown in FIG.
  • SiO 2 having a thickness of 5 nm to 50 nm may be deposited as a first protective film 31 on the quantum dot film layer 2a by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • Step 3 A patterned array 4 is prepared on the first protective film 31.
  • a patterned array 4 is prepared on the first protective film 31 by a laser direct writing process.
  • the precursor film layer 4a is patterned by a direct writing process, and the precursor film layer 4a forms a patterned array 4 and a precursor residual film 4a-1 surrounding the patterned array 4, as shown in FIG. 4; 3) After development by HF acid, the precursor residual film 4a-1 is peeled off, that is, a patterned array 4 is formed on the first protective film 31, as shown in FIG.
  • Ti in the patterned region is oxidized to TiO 2 , that is, the material of the finally formed patterned array 4 is TiO 2 .
  • the feature size of the finally obtained patterned array 4 is 100 nm to 500 nm, that is, the length and/or width of the patterned array 4 is 100 nm to 500 nm. Meanwhile, since the thickness of the precursor film layer 4a prepared as described above is 40 nm to 300 nm, the thickness of the finally obtained patterned array 4 is also 40 nm to 300 nm.
  • Step 4 Preparing a second protective film 32 on the first protective film 31 and the patterned array 4 to obtain an intermediate body 10a, as shown in FIG.
  • SiO 2 having a thickness of 50 nm to 300 nm is deposited as a second protective film 32 on the first protective film 31 and the patterned array 4 by PECVD.
  • Step 5 Annealing the intermediate 10a, and peeling off the first protective film 31, the patterned array 4, and the second protective film 32, and obtaining the quantum dot structure 10 on the substrate 1, as shown in FIG.
  • the annealing temperature of the present embodiment is 550 ° C to 750 ° C, and the annealing time is 30 s to 5 min.
  • the quantum dots in the quantum dot film layer 2a on the substrate 1 are divided into two regions, and the quantum dots of one region are covered by the first protective film 31 and the patterned array. 4 and the second protective film 32 are covered, and the quantum dots of other regions around this region are covered only by the first protective film 31 and the second protective film 32.
  • the density of the quantum dots not covered by the patterned array 4 becomes low, and as the annealing time increases, the quantum dots whose density tends to be stable promote the intermixing diffusion until the disappearance .
  • the quantum dots not covered by the patterned array 4 are mutually mixed and diffused to form the second quantum dot array 22 as shown in FIG. 7 .
  • the quantum dots covered by the patterned array 4 are not changed during the annealing process to form the first quantum dot array 21 as shown in FIG. 7, whereby the quantum dot structure 10 is finally formed on the substrate 1.
  • Embodiment 2 In the description of Embodiment 2, the same points as Embodiment 1 will not be described again here, only The difference from Embodiment 1 will be described.
  • the method of fabricating the quantum dot structure in Embodiment 2 is different from that in Embodiment 1 in that the specific method of preparing the patterned array 4 on the first protective film 31 in Step 3 is different.
  • the present embodiment prepares the patterned array 4 on the first protective film 31 by a photolithography process.
  • a layer of photoresist 4b on the first protective film 31 with a silicone machine, as shown in FIG. 8; (2) using a photolithography process for the photoresist The layer 4b is patterned, and the photoresist layer 4b forms a lithographic residue 4b-2, and at the same time, a recess 4b is formed in the lithographic residue 4b-2 to match the shape of the pre-prepared patterned array 4. 1, as shown in FIG.
  • the material of the patterned film layer 4c may also be any one of Al, HfO 2 , Si 3 N 4 , and SrTiO 3 , whereby the material of the patterned array 4 corresponds to the above figure.
  • the material of the film layer 4c is the same.
  • the feature size of the finally obtained patterned array 4 is 200 nm to 10 ⁇ m, that is, the length and/or width of the patterned array 4 is 200 nm to 10 ⁇ m. Meanwhile, since the thickness of the patterned film layer 4c prepared as described above is 40 nm to 300 nm, the thickness of the patterned array 4 finally obtained is also 40 nm to 300 nm.
  • Embodiment 3 the same points as Embodiment 2 will not be described again, and only differences from Embodiment 2 will be described.
  • the method for fabricating the quantum dot structure in Embodiment 3 is different from that in Embodiment 2 in that a pattern array is prepared on the first protective film in the third step.
  • the specific method of the column is different; at the same time, the annealing time and the annealing temperature of the annealing of the intermediate in step 5 are different.
  • the photolithography process of the step (2) in the third step of the second embodiment is replaced with an electron beam lithography process to pattern the photoresist layer.
  • the feature size of the finally obtained patterned array is 10 nm to 200 nm, that is, the obtained patterned array has a length and/or a width of 10 nm to 200 nm.
  • the annealing temperature of the intermediate body 10a is 650 ° C to 1000 ° C, and the annealing time is 5 min to 10 min, whereby the quantum dot structure 10 as shown in FIG. 11 is obtained.
  • the second quantum dot array 22 disappears, and the quantum dots in the first quantum dot array 21 are also mutually mixed and diffused to form a third quantum dot array. twenty three.
  • the patterned array in this embodiment is prepared by an electron beam lithography process, and the obtained patterned array has a small feature size because it cannot form a good protection effect on the quantum dots located underneath, resulting in A plurality of quantum dots underneath also exhibit a phenomenon of intermixed diffusion, thereby forming a third quantum dot array 23, and because the annealing temperature is higher, the annealing time is longer, thereby causing the area not covered by the patterned array.
  • the quantum dot intermixed diffusion is severe and causes disappearance.
  • the fourth embodiment is different from the first embodiment in that, in the fifth step, the annealing time is 650 ° C to 1000 ° C, and the annealing time is 5 min to 10 min, thereby obtaining the quantum dot structure 10 as shown in FIG.
  • the second quantum dot array 11 disappears while the first quantum dot array 21 remains as it is.
  • the annealing temperature in this embodiment is higher than that in Embodiment 1, and the annealing time is longer than the annealing time in Embodiment 1, thereby causing quantum dots not covered by the patterned array.
  • the intermixed diffusion is severe and causes disappearance. Since the method for preparing the patterned array in this embodiment is laser direct writing, the obtained patterned array has a large feature size, so the plurality of quantum dots covered by the patterned array remain Original.
  • the preparation method of the patterned array, the annealing temperature and the annealing time all affect the shape of the finally obtained quantum dot structure, thereby preparing a different patterned array, and
  • the annealing temperature and annealing time of the intermediate are controlled to prepare a quantum dot structure with controlled density and position.
  • the second quantum dot array and the third quantum dot can be prepared by preparing a patterned array having a smaller feature size and controlling a lower annealing temperature and a shorter annealing time.

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Abstract

一种量子点结构（10）的制作方法，包括：在衬底（1）上制备量子点膜层（2a）；在所述量子点膜层（2a）上制备第一保护膜（31）；在所述第一保护膜（31）上制备图形化阵列（4）；在所述第一保护膜（31）及所述图形化阵列（4）上制备第二保护膜（32），获得中间体（10a）；对所述中间体（10a）进行退火处理，在所述衬底（1）上获得量子点结构（10）。上述方法以图形化阵列（4）作为模板，利用模板选择区域退火工艺来制作有序的量子点结构（10），并采用后续热处理工艺，一方面避免对衬底（1）的表面造成损伤，提高量子点结构（10）的性能；另一方面，可有效控制量子点密度及位置，使所获得的量子点结构（10）应用于量子点器件时，性能更为优越。

Description

一种量子点结构的制作方法 技术领域
本发明属于半导体量子点及其制造技术领域，具体地讲，涉及一种量子点结构的制作方法。
背景技术
量子信息技术是物理学领域前沿的重大的研究方向之一，而基于单光子态操纵实现量子计算、量子通信是目前量子信息技术最重要的物理实现方法。但是目前缺乏理想的单光子发射器件，因此目前来说，量子密钥通信的实验演示都采用激光衰减光源来模拟单光子发射，但是这种实验需要极为复杂的光路系统，而且单光子产生效率很低，也不能消除多光子的存在，无法避免受到多光子攻击的可能性。这将会给量子通信带来安全隐患，如窃听者可以通过光子数分裂(PNS)方法进行窃听。因此如何得到一种稳定、高效、可靠的单光子源，已经成为量子通信和量子密码实用化的一个瓶颈问题。
半导体量子点结构因其在X、Y、Z三个方向的尺寸在几纳米到几十纳米之间，所以将受到很强的三维的量子限制效应，能级分布呈类氢光谱状，具有典型的“类原子”结构；并且半导体量子点结构还具备波长可调谐范围大、易于集成等优势，因此成为制备单光子发射器件的理想选择之一。
但是，传统的Stranski-Krastanow模式(简称SK模式)量子点生长工艺很难长出密度可控，尺寸、位置可控的量子点结构。为了解决这个问题，近年来采用在纳米图形化衬底上外延生长量子点结构的技术受到了广泛关注，但这些方法不仅工艺繁琐而且对衬底有较大的损伤，不利于得到高质量的量子点结构。
发明内容
为解决上述现有技术存在的问题，本发明提供了一种量子点结构的制作方法，该制作方法采用模板选区退火工艺，从而获得了其中量子点的密度及位置可控的量子点结构。
为了达到上述发明目的，本发明采用了如下的技术方案：
一种量子点结构的制作方法，包括：在衬底上制备量子点膜层；在所述量子点膜层上制备第一保护膜；在所述第一保护膜上制备图形化阵列；在所述第一保护膜及所述图形化阵列上制备第二保护膜，获得中间体；对所述中间体进行退火处理，在所述衬底上获得量子点结构。
进一步地，所述图形化阵列的材料选自TiO2、Al、HfO2、Si3N4、SrTiO3中的任意一种；所述图形化阵列的厚度为40nm～300nm，所述图形化阵列的长和/或宽为10nm～10μm。
进一步地，所述第一保护膜和所述第二保护膜的材料均为SiO2；所述第一保护膜的厚度为5nm～50nm，所述第二保护膜的厚度为50nm～300nm。
进一步地，对所述中间体进行退火处理的退火温度为550℃～1000℃，退火时间为30s～10min。
进一步地，所述量子点膜层的材料选自InAs、InGaAs、InGaAlAs、InSb、GaSb、InP中的任意一种；所述量子点膜层的生长温度为300℃～550℃；所述量子点膜层的厚度为1.4ML～10ML；所述量子点膜层中量子点的密度为108cm-2～1011cm-2。
进一步地，在所述第一保护膜上制备所述图形化阵列的方法具体包括：在所述第一保护膜上制备前驱体膜层；采用激光直写工艺对所述前驱体膜层进行图形化处理，所述前驱体膜层形成所述图形化阵列及围绕在所述图形化阵列周围的前驱体残膜；剥离所述前驱体残膜，在所述第一保护膜上形成所述图形化阵列。
进一步地，所述前驱体膜层的材料为Ti；所述前驱体膜层的厚度为40nm～300nm；所述图形化阵列的长和/或宽为100nm～500nm。
进一步地，在所述第一保护膜上制备所述图形化阵列的方法具体包括：在所述第一保护膜上制备光刻胶层；采用光刻工艺或电子束光刻工艺对所述光刻胶层进行图形化处理，形成与所述图形化阵列的形状相匹配的凹孔；在所述凹孔中沉积图形化膜层；剥离所述光刻胶层，在所述第一保护膜上形成所述图形化阵列。
进一步地，所述图形化膜层的材料选自TiO2、Al、HfO2、Si3N4、SrTiO3中的任意一种；所述图形化膜层的厚度为40nm～300nm；当采用光刻工艺对所述光刻胶层进行图形化处理时，所述图形化阵列的长和/或宽为200nm～10μm；当采用电子束光刻工艺对所述光刻胶层进行图形化处理时，所述图形化阵列的长和/或宽为10nm～200nm。
进一步地，所述衬底的材料选自GaAs、GaSb、InP中的任意一种。
有益效果：
(1)简化了工艺流程，优化了量子点结构的制作过程；本发明以图形化阵列作为模板，利用模板选择区域退火工艺来制作有序的量子点结构，并采用后续热处理工艺，相比现有技术中量子点结构的制作方法，避免对衬底的表面造成损伤，完整的衬底表面有利于减少量子点结构在生长过程中引入的缺陷，从而提高量子点结构的性能。
(2)制备密度可控的量子点，进而提高相应的量子点结构的性能，如可将低密度量子点结构应用于单光子器件中；本发明利用均匀的图形化阵列作为模板图形，有利于制备出均匀分布的量子点结构，从而可提高单光子器件、量子点激光器等量子点器件的性能。
(3)控制退火程度，可以在不同的模板区域得到不同密度、发射谱的量子点结构，有利于在宽光谱器件中的应用；本发明通过生长不同厚度的SiO2薄膜作为第一保护膜和第二保护膜，在相同的退火条件下，可以得到不同发射谱的量子点区域，而调控量子的发射谱，进而在同一块衬底上得到具有宽光谱性质的结构。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方 面、特点和优点将变得更加清楚，附图中：
图1-图7是根据本发明的实施例1的量子点结构的制作方法的工艺流程图示。
图8-图10是根据本发明的实施例2的量子点结构的制作方法的工艺流程图示。
图11是根据本发明的实施例3的量子点结构的制作方法获得的量子点结构的结构示意图。
图12是根据本发明的实施例4的量子点结构的制作方法获得的量子点结构的结构示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。在附图中，为了清楚起见，可以夸大元件的形状和尺寸，并且相同的标号将始终被用于表示相同或相似的元件。
将理解的是，尽管在这里可使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开来。
实施例1
图1-图7是根据本实施例的量子点结构的制作方法的工艺流程图示。
具体参照图1-图7，根据本实施例的量子点结构的制作方法包括下述步骤：
步骤一：在衬底1上制备量子点膜层2a。
具体地，在本实施例中，衬底1的材料为GaAs；量子点膜层2a 的材料为InAs；量子点膜层2a的厚度为1.4ML～10ML，优选为1.4ML～5ML；量子点膜层2a中量子点的密度为108cm-2～1011cm-2。此处，ML即为单原子层(monolayer)，也即单层原子的厚度。
更为具体地，采用分子束外延SK模式生长量子点膜层2a，生长温度为300℃～550℃；关于该分子束外延SK模式来制备量子点膜层2a的具体工艺此处不再赘述，本领域技术人员参照现有技术即可。值得说明的是，当采用分子束外延SK模式制备量子点膜层2a的过程中，会伴生有浸润层2b，浸润层2b形成于衬底1上，而量子点膜层2a中的量子点阵列即“镶嵌”于该浸润层2b中，如图1所示。
当然，衬底1以及量子点膜层2a的材料并不限于本实施例中所述的GaAs及InAs；衬底1的材料还可以选用GaSb、InP或其他半导体材料衬底，量子点膜层2a的材料还可以选用InGaAs、InGaAlAs、InSb、GaSb、InP等。
步骤二：在量子点膜层2a上制备第一保护膜31，如图2所示。
具体地，可选择等离子体增强化学气相沉积法(简称PECVD)在量子点膜层2a上沉积一层厚度为5nm～50nm的SiO2作为第一保护膜31。
步骤三：在第一保护膜31上制备图形化阵列4。
参照图3-图5，本实施例采用激光直写工艺在第一保护膜31上制备图形化阵列4。
具体来讲，参照下述步骤：(1)采用电子束蒸发法在第一保护膜31上沉积厚度为40nm～300nm的Ti作为前驱体膜层4a，如图3所示；(2)采用激光直写工艺对前驱体膜层4a进行图形化处理，该前驱体膜层4a形成图形化阵列4和围绕在该图形化阵列4四周的前驱体残膜4a-1，如图4所示；(3)经HF酸显影后，前驱体残膜4a-1被剥离，即在第一保护膜31上形成图形化阵列4，如图5所示。
值得说明的是，在上述激光直写工艺处理的过程中，图形化区域的Ti即被氧化变成TiO2，也就是说，最终形成的图形化阵列4的材料为TiO2。
鉴于激光直写工艺的控制精度，最终获得的图形化阵列4的特征尺寸为100nm～500nm，也就是说，图形化阵列4的长和/或宽为100nm～500nm。同时，由于上述制备的前驱体膜层4a的厚度为40nm～300nm，因此最终获得的图形化阵列4的厚度也为40nm～300nm。
值得说明的是，当采用本实施例中的激光直写工艺在第一保护膜31上制备图形化阵列4时，Al、HfO2、Si3N4、SrTiO3等不适用于用作图形化阵列4的材料。
步骤四：在第一保护膜31及图形化阵列4上制备第二保护膜32，获得中间体10a，如图6所示。
具体地，采用PECVD在第一保护膜31及图形化阵列4上沉积一层厚度为50nm～300nm的SiO2作为第二保护膜32。
步骤五：对中间体10a进行退火处理，并剥离第一保护膜31、图形化阵列4及第二保护膜32，在衬底1上获得量子点结构10，如图7所示。
具体来讲，本实施例的退火温度为550℃～750℃，退火时间为30s～5min。
通过前述步骤一-步骤四的操作，可以看出，衬底1上量子点膜层2a中的量子点分为两个区域，一个区域的量子点上方即被第一保护膜31、图形化阵列4及第二保护膜32覆盖，而这一区域周围的其他区域的量子点上方仅被第一保护膜31和第二保护膜32覆盖。在对中间体10a进行退火的过程中，未被图形化阵列4覆盖的量子点的密度变低，随着退火时间的增加，密度趋于稳定的量子点经高温会促进互混扩散，直至消失。一般地，当控制退火温度为550℃～750℃，退火时间为30s～5min时，未被图形化阵列4覆盖的量子点即互混扩散形成如图7中所示的第二量子点阵列22，而被图形化阵列4覆盖的量子点在退火过程中未发生变化，形成如图7中所示的第一量子点阵列21，由此最终在衬底1上形成了量子点结构10。
实施例2
在实施例2的描述中，与实施例1的相同之处在此不再赘述，只 描述与实施例1的不同之处。实施例2中的量子点结构的制作方法与实施例1中的不同之处在于，步骤三中在第一保护膜31上制备图形化阵列4的具体方法不同。
参照图8-图10，本实施例采用光刻工艺在第一保护膜31上制备图形化阵列4。
具体来讲，参照下述步骤：(1)用甩胶机在第一保护膜31上旋涂一层光刻胶层4b，如图8所示；(2)采用光刻工艺对光刻胶层4b进行图形化处理，该光刻胶层4b形成光刻残胶4b-2，同时，光刻残胶4b-2内形成与预制备的图形化阵列4的形状相匹配的凹孔4b-1，如图9所示；(3)采用电子束蒸发工艺在光刻残胶4b-2及凹孔4b-1上沉积厚度为40nm～300nm的TiO2作为图形化膜层4c，其中，覆盖在光刻残胶4b-2上的图形化膜层记为4c-1，而落入凹孔4b-1内并直接覆盖在第一保护膜31上的图形化膜层记为4c-2，如图10所示；(4)剥离光刻残胶4b-2及位于其表面的图形化膜层4c-2，位于凹孔4b-1内部的图形化膜层4c-1则形成如图5中所示图形，即在第一保护膜31上形成了以TiO2为材料的图形化阵列4。
当然，在本实施例中，图形化膜层4c的材料还可以是Al、HfO2、Si3N4、SrTiO3中的任意一种，由此，图形化阵列4的材料即对应与上述图形化膜层4c的材料相同。
鉴于光刻工艺的控制精度，最终获得的图形化阵列4的特征尺寸为200nm～10μm，也就是说，图形化阵列4的长和/或宽为200nm～10μm。同时，由于上述制备的图形化膜层4c的厚度为40nm～300nm，因此最终获得的图形化阵列4的厚度也为40nm～300nm。
其余步骤参照实施例1中所述，最终获得如图7中所示的量子点结构10。
实施例3
在实施例3的描述中，与实施例2的相同之处在此不再赘述，只描述与实施例2的不同之处。实施例3中的量子点结构的制作方法与实施例2中的不同之处在于，步骤三中在第一保护膜上制备图形化阵 列的具体方法不同；同时，步骤五中对中间体进行退火的退火时间及退火温度不同。
具体来讲，本实施例将实施例2步骤三中步骤(2)的光刻工艺替换为电子束光刻工艺，以对光刻胶层进行图形化处理。
值得说明的是，鉴于电子束光刻工艺的控制精度，最终获得的图形化阵列的特征尺寸为10nm～200nm，即获得的图形化阵列的长和/或宽为10nm～200nm。
在本实施例中，中间体10a的退火温度为650℃～1000℃，退火时间为5min～10min，由此获得如图11所示的量子点结构10。
对比图7和图11中的量子点结构10的形状，可以看出，第二量子点阵列22消失，而第一量子点阵列21中的量子点也互混扩散，形成了第三量子点阵列23。这是由于，本实施例中图形化阵列采用电子束光刻工艺来制备，所获得的图形化阵列的特征尺寸较小，因为无法对位于其下方的量子点形成良好的保护作用，造成了位于其下方的多个量子点也出现了互混扩散的现象，由此形成了第三量子点阵列23，而又由于退火温度较高，退火时间较长，因此造成未被图形化阵列覆盖区域处的量子点互混扩散严重并导致消失。
实施例4
在实施例4的描述中，与实施例1的相同之处在此不再赘述，只描述与实施例1的不同之处。实施例4与实施例1的不同之处在于，在步骤五中，退火时间为650℃～1000℃，退火时间为5min～10min，由此获得如图12中的量子点结构10。
对比图7和图12中的量子点结构10的形状，可以看出，第二量子点阵列11消失，而第一量子点阵列21则保持原状。这是由于，本实施例中的退火温度较实施例1中的退火温度更高，且退火时间较实施例1中的退火时间更长，由此造成未被图形化阵列覆盖区域处的量子点互混扩散严重并导致消失，而由于本实施例中图形化阵列的制备方法为激光直写，所获得的图形化阵列的特征尺寸较大，因此被图形化阵列覆盖的多个量子点仍旧保持原状。
综上，可以看出，图形化阵列的制备方法以及退火温度、退火时间均会对最终获得的量子点结构的形状造成影响，由此，即可通过选择不同的图形化阵列的制备方法、以及控制中间体的退火温度和退火时间来制备密度、位置可控的量子点结构。
由此，本领域技术人员将理解的是，通过制备具有较小特征尺寸的图形化阵列、并控制较低退火温度及较短的退火时间，可制备获得第二量子点阵列和第三量子点阵列共存的量子点结构。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (10)

  1. 一种量子点结构的制作方法，其特征在于，包括：
    在衬底上制备量子点膜层；
    在所述量子点膜层上制备第一保护膜；
    在所述第一保护膜上制备图形化阵列；
    在所述第一保护膜及所述图形化阵列上制备第二保护膜，获得中间体；
    对所述中间体进行退火处理，在所述衬底上获得量子点结构。
  2. 根据权利要求1所述的制作方法，其特征在于，所述图形化阵列的材料选自TiO2、Al、HfO2、Si3N4、SrTiO3中的任意一种；所述图形化阵列的厚度为40nm～300nm，所述图形化阵列的长和/或宽为10nm～10μm。
  3. 根据权利要求1所述的制作方法，其特征在于，所述第一保护膜和所述第二保护膜的材料均为SiO2；所述第一保护膜的厚度为5nm～50nm，所述第二保护膜的厚度为50nm～300nm。
  4. 根据权利要求1-3任一所述的制作方法，其特征在于，对所述中间体进行退火处理的退火温度为550℃～1000℃，退火时间为30s～10min。
  5. 根据权利要求1所述的制作方法，其特征在于，所述量子点膜层的材料选自InAs、InGaAs、InGaAlAs、InSb、GaSb、InP中的任意一种；所述量子点膜层的生长温度为300℃～550℃；所述量子点膜层的厚度为1.4ML～10ML；所述量子点膜层中量子点的密度为108cm-2～1011cm-2。
  6. 根据权利要求1所述的制作方法，其特征在于，在所述第一保护膜上制备所述图形化阵列的方法具体包括：
    在所述第一保护膜上制备前驱体膜层；
    采用激光直写工艺对所述前驱体膜层进行图形化处理，所述前驱 体膜层变为所述图形化阵列及围绕在所述图形化阵列周围的前驱体残膜；
    剥离所述前驱体残膜，在所述第一保护膜上形成所述图形化阵列。
  7. 根据权利要求6所述的制作方法，其特征在于，所述前驱体膜层的材料为Ti；所述前驱体膜层的厚度为40nm～300nm；所述图形化阵列的长和/或宽为100nm～500nm。
  8. 根据权利要求1所述的制作方法，其特征在于，在所述第一保护膜上制备所述图形化阵列的方法具体包括：
    在所述第一保护膜上制备光刻胶层；
    采用光刻工艺或电子束光刻工艺对所述光刻胶层进行图形化处理，形成与所述图形化阵列的形状相匹配的凹孔；
    在所述凹孔中沉积图形化膜层；
    剥离所述光刻胶层，在所述第一保护膜上形成所述图形化阵列。
  9. 根据权利要求8所述的制作方法，其特征在于，所述图形化膜层的材料选自TiO2、Al、HfO2、Si3N4、SrTiO3中的任意一种；所述图形化膜层的厚度为40nm～300nm；当采用光刻工艺对所述光刻胶层进行图形化处理时，所述图形化阵列的长和/或宽为200nm～10μm；当采用电子束光刻工艺对所述光刻胶层进行图形化处理时，所述图形化阵列的长和/或宽为10nm～200nm。
  10. 根据权利要求1所述的制作方法，其特征在于，所述衬底的材料选自GaAs、GaSb、InP中的任意一种。
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