WO2020088509A1 - 硅基衬底、衬底基板及其制造方法、光电器件 - Google Patents

硅基衬底、衬底基板及其制造方法、光电器件 Download PDF

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WO2020088509A1
WO2020088509A1 PCT/CN2019/114307 CN2019114307W WO2020088509A1 WO 2020088509 A1 WO2020088509 A1 WO 2020088509A1 CN 2019114307 W CN2019114307 W CN 2019114307W WO 2020088509 A1 WO2020088509 A1 WO 2020088509A1
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silicon
layer
group iii
based substrate
crystal layer
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PCT/CN2019/114307
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English (en)
French (fr)
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赵壮
刘磊
乐阮平
王霆
张建军
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华为技术有限公司
中国科学院物理研究所
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Priority to JP2021523610A priority Critical patent/JP2022511666A/ja
Priority to EP19880590.5A priority patent/EP3866186A4/en
Publication of WO2020088509A1 publication Critical patent/WO2020088509A1/zh
Priority to US17/245,995 priority patent/US20210265528A1/en

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Definitions

  • the present disclosure relates to the application field of electronic technology, in particular to a silicon-based substrate, a substrate substrate, a method for manufacturing the same, and a photoelectric device.
  • Silicon-based optoelectronic integration technology refers to the technology of integrating optoelectronic devices on a silicon-based substrate. Devices such as light sources, amplifiers, or modulators formed using this technology have the advantages of low cost, micro size, and high integration.
  • the Group III-V materials can be formed on a silicon-based substrate Efficient light-emitting devices provide a good foundation for the formation of optoelectronic devices.
  • the group III-V material may be indium arsenide (InAs) or gallium arsenide (GaAs).
  • the present application provides a silicon-based substrate, a substrate substrate, a method for manufacturing the same, and a photoelectric device, which can reduce the lattice mismatch and reverse phase domain between the silicon-based substrate and the group III-V materials Yield of family materials on silicon-based substrates.
  • the present application provides a substrate substrate, including:
  • a silicon-based substrate one side of the silicon-based substrate has a periodic convex structure, and the side surface and the bottom surface of each of the convex structures have an inclination angle, and the self-annihilation of the dislocation of the silicon-based substrate can be achieved by the inclination , So as to suppress the dislocation on the side of the convex structure of the silicon-based substrate;
  • a Group III-V material layer disposed on one side of the silicon-based substrate having the raised structure.
  • the convex structure can realize the self-annihilation of dislocations and lose the lattice
  • the dislocations caused by the coordination and anti-phase domains are limited to the layer of the silicon-based substrate, so that when the group III-V materials are epitaxially grown on the silicon-based substrate, the neat crystal structure can be maintained, therefore, the silicon-based substrate is reduced Problems such as lattice mismatch and reversed-phase domains between the bottom and Group III and V materials improve the yield of Group III and V materials on the silicon-based substrate.
  • the surface of the silicon-based substrate having the periodic convex structure is a silicon (111) crystal plane.
  • the silicon (111) crystal plane can effectively suppress the dislocations, so that the dislocations no longer continue to grow upward, and the reverse phase domains can be almost completely suppressed on the 60 ° crystal plane, so it is more conducive to the epitaxial growth of Group III and V materials.
  • the silicon-based substrate includes: a sub-silicon-based substrate with periodic grooves on one side; and a silicon intermediate layer provided on the side of the sub-silicon-based substrate with the grooves, so The silicon intermediate layer is composed of the periodic convex structure;
  • each of the raised structures is located on the spacing structure between two adjacent grooves, and the sides of each two adjacent raised structures are adjacent (that is, the upper surfaces of the multiple raised structures are continuous Surface), so that a stable silicon-based substrate structure can be achieved.
  • the arrangement period of the grooves is 200 nanometers (nanometer, nm) to 800 nm, and the depth of each of the grooves is 200 nm to 1000 nm. Further, the arrangement period of the grooves is 300 nm to 500nm; the depth of each groove is 400nm to 600nm.
  • the thickness of the silicon intermediate layer is 300 nm to 800 nm.
  • the thickness of the silicon intermediate layer refers to the thickness of the silicon intermediate layer with the top platform of the groove 111 as a reference plane. Further, the The thickness is 450 nm to 650 nm.
  • the surface of the silicon-based substrate having the periodic grooves is a silicon (110) crystal plane, and the lateral boundary of each groove Perpendicular to the bottom.
  • the interface of the groove has an inverted trapezoid shape, and the top width of each groove is 100 nm to 400 nm; the bottom width of each groove is 50 nm to 200 nm. Further, the width of the top of each groove is 120 nm to 160 nm, and the width of the bottom of each groove is 100 nm to 120 nm.
  • the group III-V material layer includes a layer III-V material buffer layer and a group III-V dislocation filter layer sequentially stacked on one side of the silicon-based substrate having the raised structure.
  • a buffer layer of Group V material is used to buffer the lattice mismatch of the silicon-based substrate, and the filter group of Group III-V dislocation is used to filter the dislocation of the silicon-based substrate.
  • the thickness of the group III-V dislocation filter layer is 0 micrometer (micron, ⁇ m) to 2 ⁇ m; the surface roughness of the group III-V dislocation filter layer is 0.5 nm to 1.6 nm. Further, the thickness of the group III-V dislocation filter layer is 0.8 ⁇ m to 1.8 ⁇ m, and the surface roughness of the group III-V dislocation filter layer is 0.8 nm to 1.4 nm. Surface roughness can characterize the smoothness of the surface of the structural layer. The smaller the surface roughness value, the smoother the surface of the structural layer.
  • the buffer layer of Group III-V materials includes:
  • AlAs (aluminum arsenide) crystal layer and a GaAs (gallium arsenide) crystal layer disposed on one side of the silicon-based substrate having the raised structure are sequentially stacked.
  • the melting point of Al (aluminum) is about 660 ° C (degrees Celsius) and the melting point of Ga (gallium) is about 30 ° C
  • the melting point of the AlAs crystal layer is higher than that of the GaAs crystal layer.
  • the GaAs crystal layer is directly provided on the convex structure
  • the melting point of Ga is low
  • the atoms of the GaAs crystal layer will move on the silicon-based substrate, which will cause dislocations.
  • the AlAs crystal layer is provided on the convex structure, the melting point of Al is high, so The atoms in the AlAs crystal layer have a higher bond energy and will not move on the silicon-based substrate, thereby avoiding dislocations caused by lattice mismatch.
  • first setting the AlAs crystal layer on the raised structure of the silicon-based substrate, and then setting the GaAs crystal layer on the AlAs crystal layer can effectively avoid the dislocation caused by directly setting the GaAs crystal layer on the silicon-based substrate, Thus, a high-quality group III-V material layer is formed on the silicon-based substrate.
  • the thickness of the buffer layer of the group III-V material is 0 nm to 600 nm; the surface roughness of the GaAs crystal layer is 0.5 nm to 1.6 nm. Further, the thickness of the buffer layer of the group III-V material is 200 nm to 600 nm; the surface roughness of the GaAs crystal layer is 0.8 nm to 1.4 nm.
  • the group III-V dislocation filter layer includes: m periods of first quantum well structure layers superimposed and arranged, and each period of the first quantum well structure layer includes In 0.15 Ga 0.85 As sequentially stacked In the crystal layer and the GaAs crystal layer, m is a positive integer.
  • In 0.15 Ga 0.85 As means that the proportion of In (indium) is 15%, and the proportion of Ga is 85% of InGaAs (indium gallium arsenide).
  • the group III-V dislocation filter layer further includes: n periodic second quantum well structure layers superimposed on the m periodic first quantum well structure layers and p periodic superlattices Structure, the n-period second quantum well structure layers are stacked, and the p-period superlattice structures are stacked, and n and p are positive integers;
  • the second quantum well structure layer of each cycle includes an In 0.15 Al 0.85 As crystal layer and a GaAs crystal layer sequentially stacked;
  • the superlattice structure of each cycle includes an Al 0.6 Ga 0.4 As crystal layer and a GaAs crystal layer sequentially stacked.
  • the effect of the In 0.15 Al 0.85 As crystal layer in the second quantum well structure layer is better than that of the In 0.15 Ga 0.85 As crystal layer in the first quantum well structure layer, but due to Al ’s
  • the melting point is higher than Ga. If an In 0.15 Al 0.85 As crystal layer is formed directly on the buffer layer of the Group III-V material, it is difficult to move Al atoms. When the positions of the atoms are not correct, it is difficult to adjust and it is difficult to suppress dislocations. extend.
  • the In 0.15 Ga 0.85 As crystal layer is used as a pad, and then In 0.15 is formed
  • the Al 0.85 As crystal layer can better suppress dislocations, thereby forming a high-quality group III-V material layer on the silicon substrate.
  • the second quantum well structure layer when there are too many Al atoms, a certain dislocation may also occur. Therefore, the second quantum well structure layer includes an In 0.15 Al 0.85 As crystal layer and a GaAs crystal layer that are sequentially stacked, which can effectively suppress dislocations caused by too many Al atoms.
  • the Al 0.6 Ga 0.4 As crystal layer and the GaAs crystal layer stacked in sequence can make the surface of the finally formed Group III-V dislocation filter layer smooth and smooth, thereby obtaining a high-quality base substrate.
  • the thickness of the group III-V dislocation filter layer is thin, and a better effect of suppressing dislocations can be achieved.
  • a silicon-based substrate including:
  • each of the raised structures is located on the spacing structure between two adjacent grooves, and the sides of each two adjacent raised structures are adjacent;
  • the surface of the silicon-based substrate having the periodic convex structure is a silicon (111) crystal plane.
  • the surface of the sub-silicon base substrate with the periodic grooves is a silicon (110) crystal plane.
  • a method for manufacturing a base substrate including:
  • one side of the silicon-based substrate has a periodic convex structure, and the side surface and the bottom surface of each convex structure have an inclination angle;
  • a Group III-V material layer is formed on one side of the silicon-based substrate having the raised structure.
  • the convex structure can realize self-annihilation of dislocations Limiting the dislocations caused by lattice mismatch and anti-phase domains to the silicon-based substrate layer allows the Group III-V materials to maintain a neat crystal structure when epitaxially grown on the silicon-based substrate. Therefore, the problems of lattice mismatch and reverse phase domain between the silicon-based substrate and the Group III-V materials are reduced, and the yield of the Group III-V materials on the silicon-based substrate is improved.
  • the surface of the silicon-based substrate having the periodic convex structure is a silicon (111) crystal plane.
  • the manufacturing of a silicon-based substrate includes:
  • a silicon intermediate layer is formed on one side of the sub-silicon base substrate having the groove, the silicon intermediate layer is composed of the periodic convex structures, and each of the convex structures is located in two adjacent On the spacing structure between the grooves, every two adjacent raised structures are adjacent.
  • the surface of the sub-silicon base substrate with the periodic grooves is a silicon (110) crystal plane.
  • the manufacturing of the sub-silicon base substrate with periodic grooves on one side includes:
  • a deep ultraviolet photolithography process is used to etch the silicon wafer to obtain the sub-silicon-based substrate.
  • the forming the silicon intermediate layer on the side of the sub-silicon base substrate having the groove includes:
  • a silicon intermediate layer is formed on the side of the sub-silicon base substrate having the groove.
  • the forming of the Group III-V material layer on the side of the silicon-based substrate with the raised structure includes: using molecular beam epitaxial growth technology on the side of the silicon-based substrate with the raised structure Forming a layer III-V material.
  • a molecular beam epitaxial growth technique may be used to form a group III-V material layer on a side of the silicon-based substrate having a convex structure.
  • the molecular beam epitaxy growth technique may be used on the silicon-based substrate.
  • Forming a group III-V material layer on one side of the raised structure includes:
  • a molecular beam epitaxial growth technique is used to form a Group III-V dislocation filter layer on the Group III-V material buffer layer;
  • the buffer layer of the Group III-V material is used to buffer the lattice mismatch of the silicon-based substrate
  • the filter group of Group III-V dislocation is used to filter the dislocation of the silicon-based substrate.
  • the buffer layer of the group III-V material includes: an AlAs crystal layer and a GaAs crystal layer, and the GaAs crystal layer includes a first sub-GaAs crystal layer and a second sub-GaAs crystal layer;
  • a buffer layer of Group III-V materials can be formed on the side of the silicon-based substrate with a convex structure by a three-step method.
  • the molecular beam epitaxial growth technique is used to have the convex structure on the silicon-based substrate
  • a buffer layer of Group III-V materials is formed on one side of the surface, including:
  • the first sub-GaAs crystal layer with a thickness of 20 nm to 40 nm is grown on the AlAs crystal layer at 350 ° C. to 400 ° C .;
  • the second sub-GaAs crystal layer with a thickness of 400 nm to 600 nm is grown on the first sub-GaAs crystal layer at 550 ° C to 600 ° C.
  • the group III-V dislocation filter layer includes: m periods of first quantum well structure layers that are superimposed and arranged, and the first quantum well structure layer includes an In 0.15 Ga 0.85 As crystal layer and a GaAs crystal layer that are sequentially stacked, m It is a positive integer.
  • First growing the first sub-GaAs crystal layer in a low-temperature growth environment can slow down the growth rate of the first sub-GaAs crystal layer on the side of the silicon-based substrate having the convex structure, and further enables the first sub-GaAs crystal layer
  • Each atom is grown in the correct position, and then in a high-temperature growth environment, growing a high-quality second sub-GaAs crystal layer on the first sub-GaAs crystal layer can suppress the dislocation caused by the reverse domain, thereby A high-quality group III-V material layer is formed on the silicon-based substrate.
  • the group III-V dislocation filter layer further includes: n periodic second quantum well structure layers superimposed on the m periodic first quantum well structure layers and p periodic superlattices Structure, the n-period second quantum well structure layers are stacked, and the p-period superlattice structures are stacked, and n and p are positive integers;
  • the second quantum well structure layer of each cycle includes an In 0.15 Al 0.85 As crystal layer and a GaAs crystal layer sequentially stacked;
  • the superlattice structure of each cycle includes an Al 0.6 Ga 0.4 As crystal layer and a GaAs crystal layer sequentially stacked.
  • the molecular beam epitaxial growth technique can be used to form the first quantum well structure layer of m periods on the buffer layer of Group III-V materials, and then form the second quantum well structure layer of n periods on the first quantum well structure layer, and finally A p-period superlattice structure is formed on the second quantum well structure layer to ensure that the structure of each layer is neat.
  • the growth temperature of the first quantum well structure layer is 460 ° C to 510 ° C, the thickness of the In 0.15 Ga 0.85 As crystal layer and the GaAs crystal layer are both 10 nm; the growth temperature of the second quantum well structure layer is 460 ° C to At 510 °C, the thickness of the In 0.15 Al 0.85 As crystal layer and the GaAs crystal layer are both 10nm; the growth temperature of the superlattice structure is 550 °C to 600 °C, the thickness of the Al 0.6 Ga 0.4 As crystal layer and the GaAs crystal layer are both It is 2nm.
  • an optoelectronic device comprising: the base substrate according to the first aspect, and at least one optical film layer and / or at least one electrical film layer provided on the base substrate.
  • the optoelectronic device is a quantum dot laser, detector, amplifier, modulator, complementary metal oxide semiconductor CMOS electrical device or waveguide device.
  • the silicon-based substrate, the substrate substrate, the manufacturing method thereof, and the photoelectric device provided by the present application because one side of the silicon-based substrate is no longer a silicon (100) crystal plane, but has a periodic convex structure, the convex The structure can realize the self-annihilation of dislocations, limiting the dislocations caused by lattice mismatch and anti-phase domains to the layer of silicon-based substrate, so that when the group III-V materials are epitaxially grown on the silicon-based substrate, The neat crystal structure is maintained, therefore, the problems of lattice mismatch and reverse phase domain between the silicon-based substrate and the Group III-V materials are reduced, and the yield of the Group III-V materials on the silicon-based substrate is improved.
  • FIG. 1 is a schematic cross-sectional view of a base substrate provided by an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of another base substrate provided by an embodiment of the present invention.
  • FIG. 3 is a partially enlarged schematic view of a base substrate provided by an embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view of a silicon-based substrate provided by an embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view of another silicon-based substrate provided by an embodiment of the present invention.
  • FIG. 6 is a comparison schematic diagram of a surface scanning electron micrograph provided by an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of an X-ray diffraction spectrum of a base substrate provided by an embodiment of the present invention.
  • FIG. 8 is a flowchart of a method for manufacturing a base substrate provided by an embodiment of the present invention.
  • FIG. 9 is a flowchart of a method for manufacturing a silicon-based substrate provided by an embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional view of a silicon-based substrate provided by an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of growth of a 250 nm silicon intermediate layer on a sub-silicon substrate provided by an embodiment of the present invention.
  • FIG. 13 is a flowchart of a method for forming a buffer layer of Group III-V materials provided by an embodiment of the present invention.
  • the embodiment of the present application relates to the improvement of the silicon-based substrate and the base substrate manufactured based on the silicon-based substrate.
  • Silicon belongs to the cubic crystal system. 100) The silicon wafer on the crystal plane, the silicon wafer on the silicon (110) crystal plane and the silicon wafer on the silicon (111) crystal plane, in order to facilitate the reader's understanding, these silicon wafers are introduced as follows:
  • a silicon wafer with a silicon (100) crystal plane is also called a silicon wafer (100), [100] is the crystal orientation index, the normal of the silicon (100) crystal plane is parallel to the [100] crystal orientation, that is to say (100 ) The crystal plane is perpendicular to the [100] crystal orientation.
  • a silicon wafer with a silicon (110) crystal plane is also called a silicon wafer (110), [110] is the crystal orientation index, the normal of the silicon (110) crystal plane is parallel to the [110] crystal orientation, that is to say (110 ) The crystal plane is perpendicular to the [110] crystal orientation.
  • a silicon wafer with a silicon (111) crystal plane is also called a silicon wafer (111), [111] is the crystal orientation index, the normal of the silicon (111) crystal plane is parallel to the [111] crystal orientation, that is to say (111 ) The crystal plane is perpendicular to the [111] crystal orientation.
  • the array of atoms in various directions in the crystal is called the crystal orientation.
  • III-V materials are formed on silicon-based substrates with silicon (100) crystal planes by epitaxial growth.
  • the epitaxial growth technology refers to growth on single-crystal substrates (also called substrates) The technique of a single crystal layer with the same crystal orientation as the substrate.
  • the epitaxial growth refers to the growth of a single crystal layer using epitaxial growth technology. Among them, the surface of a silicon-based substrate having a silicon (100) crystal plane is flat. Due to the different lattice constants of silicon and the Group III-V materials and the difference between polar and non-polar bonds, lattice mismatches and anti-phase domains will occur, resulting in the epitaxial growth of Group III-V materials on silicon-based substrates.
  • a large number of dislocations and defects which may cause the atoms of the Group III and V materials to be partially arranged irregularly on the silicon-based substrate, further leading to the difficulty in achieving epitaxial growth of high-quality Group III and V materials on the silicon-based substrate .
  • FIG. 1 is a schematic cross-sectional view of a base substrate provided by an embodiment of the present application.
  • the base substrate includes:
  • one side of the silicon-based substrate 10 has a periodic convex structure 101.
  • the periodic convex structure 101 refers to a plurality of convex structures, and has a certain amount of Distribution period, there is a tilt angle between the side surface W and the bottom surface of each convex structure 101, and the tilt angle can realize the self-annihilation of the dislocation of the silicon-based substrate 10, thereby suppressing the dislocation in the convex structure of the silicon-based substrate
  • the group III-V material layer 20 is disposed on the side of the silicon-based substrate having the convex structure 101.
  • the convex structure can realize the position
  • the self-annihilation of faults restricts the dislocations caused by lattice mismatch and anti-phase domains to the silicon-based substrate layer, so that the Group III and V materials can maintain a neat crystal when epitaxially grown on the silicon-based substrate structure. Therefore, the problems of lattice mismatch and reverse phase domain between the silicon-based substrate and the Group III-V materials are reduced, and the yield of the Group III-V materials on the silicon-based substrate is improved.
  • the surface of the silicon-based substrate with periodic convex structure 101 is a silicon (111) crystal plane, for example, the inclination angle of the side surface W and the bottom surface of the convex structure is 60 degrees, and at this time, the silicon-based substrate
  • the cross section of the surface of the periodic convex structure 101 at the bottom may be a zigzag structure formed by connecting equilateral triangles with an apex angle of 60 degrees.
  • the silicon (111) crystal plane can effectively suppress the dislocations, so that the dislocations no longer continue to grow upward, and the reverse phase domain can be almost completely suppressed on the 60 ° crystal plane, so it is more conducive to the epitaxial growth of the Group III and V materials.
  • the protrusion structures in the silicon-based substrate are arranged in an array at equal distances in a specified direction, the shape and size of each protrusion structure may be the same, and the distance between each two protrusion structures may be 360 nm, where the specified
  • the direction may be the row direction or column direction of the silicon-based substrate, and the extending direction of each convex structure may be perpendicular to the specified direction and parallel to the bottom surface of the silicon-based substrate, such as the one perpendicular to the paper surface in FIG.
  • the distance between every two raised structures refers to the distance between the specified points (such as the center point) of the two raised structures in the specified direction, which can achieve better suppression of dislocations, and every two Adjacent convex structures are adjacent to each other (that is, the upper surfaces of the multiple convex structures are continuous surfaces), thereby achieving a stable silicon-based substrate structure. It should be noted that the distance between every two convex structures can be set according to experimental conditions and actual requirements, which is not limited in the embodiments of the present application.
  • a silicon-based substrate 10 includes: a child having a periodic groove 111 on one side The silicon-based substrate 11 and the silicon intermediate layer 12 provided on the side of the sub-silicon-based substrate 11 having the groove 111.
  • the periodic groove 111 refers to a plurality of grooves, and has a certain distribution period on the sub-silicon base substrate.
  • the periodic groove 111 can be subjected to a mask process and light on the silicon wafer (100) Obtained by the engraving process, the periodic grooves 111 are all blind grooves.
  • the above-mentioned silicon intermediate layer 12 is composed of periodic convex structures 101, that is, the silicon intermediate layer 12 includes a plurality of convex structures, wherein each convex structure is located in a space structure between two adjacent grooves On 112, the spacing structure 112 is used to separate two adjacent grooves.
  • the spacing structure may be called a barrier or a retaining wall.
  • FIG. 3 which is a partial enlarged view of the base substrate.
  • each convex structure 101 is located on a space structure 112 between two adjacent grooves.
  • the starting structure can be grown by epitaxial growth technology.
  • the periodic convex structure 101 and the periodic spacing structure 112 have the same arrangement period.
  • each two adjacent protruding structures 101 are adjacent, that is, the side surfaces of each two adjacent protruding structures intersect, so that there is no gap between the respective protruding structures, which can ensure a stable silicon-based Substrate structure.
  • FIG. 4 and FIG. 5 are schematic cross-sectional views of a silicon-based substrate provided by an embodiment of the present application.
  • each concave The top width of the groove 111 is greater than the bottom width.
  • the cross-section of the groove 111 is inverted trapezoid.
  • the top width of each groove may be 100 nm to 400 nm, and the bottom width may be 50 nm to 200 nm.
  • the top width of each groove may be 120 nm to 160 nm, and the bottom width may be 100 nm to 120 nm.
  • the surface of the above-mentioned silicon-based substrate with periodic grooves 111 is a silicon (110) crystal plane, and the side boundary of each groove is perpendicular to the bottom surface.
  • the arrangement period of each groove can be 200nm to 800nm, that is, the distance between the centers of every two adjacent grooves in the specified direction can be 200nm to 800nm, further, the arrangement period of each groove may be 300nm to 500nm.
  • the depth of each groove may be 200 nm to 1000 nm. Further, the depth of each groove may be 400 nm to 600 nm.
  • the extending direction of each groove may be perpendicular to the specified direction and parallel to the bottom surface of the silicon-based substrate, for example, the direction perpendicular to the paper surface in FIGS. 4 and 5, and periodic grooves may be grown in the silicon intermediate layer During the process, the anti-phase domain is effectively suppressed.
  • the silicon intermediate layer when a silicon intermediate layer is grown on the sub-silicon-based substrate, the silicon intermediate layer grows upward on the basis of the spacer structure. During the growth of the silicon intermediate layer, every two adjacent protrusions The structure transitions from the initial non-adjacent state to the final adjoining state. Therefore, an irregular hollow structure is constructed in the middle of the structure of the resulting silicon-based substrate.
  • FIG. 4 shows an enlarged schematic view of the hollow structure.
  • the hollow structure is composed of a groove 111 and a gap M between each two raised structures 101.
  • each hollow structure Arranged in an equal distance array along the specified direction, the shape and size of each hollow structure can be the same, where the specified direction can be the row direction or column direction of the silicon-based substrate, and the extending direction of each hollow structure can be perpendicular to the specified Direction, and parallel to the bottom surface of the silicon-based substrate, such as the direction perpendicular to the paper surface in FIG. 4.
  • the hollow structure is located between every two adjacent spacing structures and between every two adjacent convex structures. Every two adjacent gap structures can be separated, or every two adjacent convex structures can be separated.
  • stress refers to the interaction force generated between the various parts of the object when the object is deformed due to external factors (force, humidity, temperature field change, etc.). Stress is used to resist the effect of external factors and make the object deform from After the position is restored to the position before the deformation,
  • the method of epitaxially growing the Group III-V material on a silicon-based substrate with a silicon (100) crystal plane includes: achieving the direct epitaxy of the Group III-V material on a beveled substrate with a silicon (100) crystal plane Growth; or, to achieve epitaxial growth of Group III or V on a germanium-silicon virtual substrate (that is, the substrate is not a pure silicon-based substrate, but a silicon-based substrate doped with germanium); Direct epitaxial growth of Group III and V materials on silicon-based substrates.
  • the direct epitaxial growth of the Group III-V materials is realized on the beveled substrate of the silicon (100) crystal plane and the silicon-based substrate with a diatomic step, and the silicon-based substrate used cannot adopt traditional complementary metal oxidation
  • the manufacturing of related processes (such as masking process and photolithography process) in the manufacturing of Complementary Metal-Oxide-Semiconductor (CMOS) requires complex processes, so the manufacturing cost is relatively high.
  • the base substrate provided in the embodiment of the present application because the above-mentioned grooves can be made using a masking process and a photolithography process, and the convex structure can be made using epitaxial growth technology, so it can be compatible with related processes in CMOS manufacturing, and the manufacturing process is simple , Lower manufacturing costs.
  • the thickness of the silicon intermediate layer 12 may be 300 nm to 800 nm.
  • the thickness of the silicon intermediate layer 12 refers to the thickness of the silicon intermediate layer with the top platform of the groove 111 as a reference plane, further The thickness of the silicon intermediate layer 12 may be 450 nm to 650 nm.
  • the embodiments of the present application only deal with such parameters as the arrangement period of the groove and the protrusion structure, the depth of the groove, the width of the top of the groove, the width of the bottom of the groove, and the thickness of the silicon intermediate layer To make a schematic illustration, in actual application, these parameters can be adjusted according to the experimental conditions and actual requirements, so that the Group III and V materials can achieve a better epitaxial growth effect on the silicon-based substrate.
  • This embodiment of the present application No limitation.
  • the above-mentioned Group III-V material layer 20 may include a Group III-V material buffer layer 21 and a Group III-V dislocation filter layer 22 that are sequentially stacked on one side of the silicon-based substrate 10 having the convex structure 101.
  • the buffer layer 21 of the group III-V material is used to buffer the lattice mismatch of the silicon-based substrate 10, and the dislocation filter layer 22 of group III-V is used to filter the dislocation of the silicon-based substrate 10.
  • the above-mentioned group III-V material buffer layer 21 includes: an aluminum arsenide (AlAs) crystal layer 210 and gallium arsenide (Gallium arsenide) layered on the side of the silicon substrate 10 having the convex structure 101 in this order , GaAs) crystalline layer 211.
  • AlAs aluminum arsenide
  • GaAs gallium arsenide
  • the melting point of Al is about 660 degrees Celsius and the melting point of Ga is about 30 degrees Celsius
  • the melting point of the AlAs crystal layer is higher than that of the GaAs crystal layer.
  • the melting point of Ga is lower. Therefore, the atoms of the GaAs crystal layer will move on the silicon-based substrate, which will cause dislocations.
  • the AlAs crystal layer is provided on the convex structure, because the melting point of Al is higher, the atoms of the AlAs crystal layer have a higher Bond energy, so as not to move on the silicon-based substrate, thereby avoiding dislocations caused by lattice mismatch.
  • first setting the AlAs crystal layer on the raised structure of the silicon-based substrate, and then setting the GaAs crystal layer on the AlAs crystal layer can effectively avoid the dislocation caused by directly setting the GaAs crystal layer on the silicon-based substrate, Thus, a high-quality group III-V material layer is formed on the silicon-based substrate.
  • the thickness of the buffer layer 21 of the group III-V material may be 0 nm to 600 nm. Further, the thickness of the buffer layer 21 of the group III-V material may be 200 nm to 600 nm.
  • the surface roughness of the GaAs crystal layer may be 0.5 nm to 1.6 nm. Further, the surface roughness of the GaAs crystal layer may be 0.8 nm to 1.4 nm. Surface roughness can characterize the smoothness of the surface of the structural layer. The smaller the surface roughness value, the smoother the surface of the structural layer.
  • the above-mentioned group III-V material buffer layer may also be composed of other structures as long as it can buffer the lattice mismatch of the silicon-based substrate.
  • the above-mentioned group III-V material buffer layer includes: sequentially stacked on silicon
  • the base substrate has an AlAs crystal layer and a gallium phosphide (GaP) crystal layer on one side of the raised structure, wherein the thickness and function of the AlAs crystal layer may be the same as the AlAs crystal layer of the above-mentioned Group III-V material buffer layer
  • the above-mentioned group III-V material buffer layer only includes: an AlAs crystal layer or a GaP crystal layer provided on one side of the silicon-based substrate having a convex structure.
  • the thickness of the group III-V dislocation filter layer 22 may be 0 ⁇ m to 2 ⁇ m, and the surface roughness of the group III-V dislocation filter layer 22 may be 0.5 nm to 1.6 nm. Further, the group III-V dislocation filter The thickness of the layer may be 0.8 ⁇ m to 1.8 ⁇ m, and the surface roughness of the group III-V dislocation filter layer may be 0.8 nm to 1.4 nm.
  • the group III-V dislocation filter layer 22 includes: m periods of the first quantum well structure layer 220, the m periods of the first quantum well structure layer 220 are superimposed and the first of each period
  • the quantum well structure layer 220 includes an In 0.15 Ga 0.85 As crystal layer and a GaAs crystal layer sequentially stacked, and m is a positive integer.
  • In 0.15 Ga 0.85 As means that the proportion of In (indium) is 15%, and the proportion of Ga (gallium) is 85% of InGaAs (indium gallium arsenide).
  • the lattice of In 0.15 Ga 0.85 As is larger than that of GaAs
  • the In 0.15 Ga 0.85 As crystal layer is first provided on the buffer layer of the Group III-V material . Stress will be generated to form a stress field.
  • the stress field generated by the In 0.15 Ga 0.85 As crystal layer can offset the stress generated by the dislocations, thereby inhibiting the dislocations from continuing to extend upward.
  • the group III-V dislocation filter layer 22 may further include: n periods of the second quantum well structure layer 221 and p periods of superlattice superimposed on the m periods of the first quantum well structure layer 220 In the structure 222, n periods of second quantum well structure layers 221 are stacked, and p periods of superlattice structures 222 are stacked. N and p are positive integers.
  • the second quantum well structure layer 221 of each cycle includes an In 0.15 Al 0.85 As crystal layer and a GaAs crystal layer sequentially stacked, and the superlattice structure 222 of each cycle includes an Al 0.6 Ga 0.4 As crystal layer and GaAs sequentially stacked ⁇ ⁇ Crystal layer.
  • In 0.15 Al 0.85 As means that the proportion of In (indium) is 15%, and that the ratio of Al (aluminum) is 85%, InGaAs (indium aluminum arsenide) Al 0.6 Ga 0.4 As means that the proportion of Al (aluminum) is 60% , The ratio of Ga (gallium) is 40% of AlGaAs (aluminum gallium arsenide).
  • the effect of the In 0.15 Al 0.85 As crystal layer in the second quantum well structure layer is better than that of the In 0.15 Ga 0.85 As crystal layer in the first quantum well structure layer, but due to Al ’s
  • the melting point is higher than Ga. If an In 0.15 Al 0.85 As crystal layer is formed directly on the buffer layer of the Group III-V material, it is difficult to move Al atoms. When the positions of the atoms are not correct, it is difficult to adjust and it is difficult to suppress dislocations. extend.
  • the In 0.15 Ga 0.85 As crystal layer is used as a pad, and then In 0.15 is formed
  • the Al 0.85 As crystal layer can better suppress dislocations, thereby forming a high-quality group III-V material layer on the silicon substrate.
  • the second quantum well structure layer includes the In 0.15 Al 0.85 As crystal layer and GaAs that are sequentially stacked The crystal layer can effectively suppress dislocations caused by too many Al atoms.
  • the Al 0.6 Ga 0.4 As crystal layer and the GaAs crystal layer stacked in sequence can make the surface of the finally formed Group III-V dislocation filter layer smooth and smooth, thereby obtaining a high-quality base substrate.
  • the thickness of the group III-V dislocation filter layer is thin, and a better effect of suppressing dislocations can be achieved.
  • the larger the values of m, n, and p the better the dislocation suppression effect of the Group III-V filter layer.
  • the appropriate first quantum well structure layer can be selected according to needs.
  • the period values of the second quantum well structure layer and the superlattice structure layer are not limited in the embodiments of the present application.
  • FIG. 6 is a comparison schematic diagram of a surface scanning electron micrograph provided by an embodiment of the present application.
  • the area on the left side of the straight line T is the surface scanning electron of the base substrate provided by the related art.
  • Micrograph, the area on the right is a scanning electron micrograph of the surface of the base substrate provided by the embodiment of the present application.
  • the Group III and V material layers and silicon There are a large number of anti-phase domains and high-density dislocations between the base substrates.
  • the group III-V material layer on the silicon base substrate is highly flat, without anti-phase domains and obvious positions wrong.
  • FIG. 7 is the X-ray diffraction spectrum of the base substrate provided by the embodiment of the present application.
  • the ordinate represents the relative intensity of X-ray diffraction
  • the abscissa represents the X-ray diffraction scanning angle ⁇ (Omega), the unit of ⁇ is "degree”.
  • MQWs refer to the structure of the three-five group dislocation filter layer in the base substrate. Since the half-height width of the X-ray diffraction spectrum is smaller, the quality of the corresponding group III-V material layer is higher. It can be seen from FIG. 7 that the half-height width of the X-ray diffraction spectrum of the base substrate is about twice that of the silicon-based substrate.
  • the structure of the base substrate provided in the embodiments of the present application can effectively reduce the problems such as lattice mismatch and reverse phase domains between the silicon-based substrate and the Group III-V materials, and the quality is high.
  • the embodiments of the present application only give a schematic description of the thickness and surface roughness of the buffer layer of the Group III-V material and the thickness and surface roughness of the filter layer of the Group III-V dislocation. This application In actual application, these parameters can be adjusted according to experimental conditions and actual requirements, so as to achieve a better epitaxial growth effect of the III-V materials on the silicon-based substrate, which is not limited in the embodiments of the present application.
  • the convex structure can realize the position
  • the self-annihilation of faults restricts the dislocations caused by lattice mismatch and anti-phase domains to the silicon-based substrate layer, so that the Group III and V materials can maintain a neat crystal when epitaxially grown on the silicon-based substrate Structure, therefore, reducing the lattice mismatch and reverse domain between the silicon-based substrate and the III-V materials, and improving the yield of the III-V materials on the silicon-based substrate, thereby improving the silicon The life and yield of basic photovoltaic devices.
  • the grooves in the silicon-based substrate can be made using a mask process and a photolithography process, and the convex structure can be made using epitaxial growth technology, it can be compatible with the related processes in CMOS manufacturing, the manufacturing process is simple, and the manufacturing cost is relatively high low.
  • the silicon-based substrate includes:
  • the surface of the silicon-based substrate with periodic convex structures 101 is a silicon (111) crystal plane
  • the surface of the sub-silicon-based substrate with periodic grooves 111 is a silicon (110) crystal plane.
  • the convex structure can be realized.
  • the self-annihilation of dislocations restricts the dislocations caused by lattice mismatch and anti-phase domains to the layer of silicon-based substrate, so that the Group III and V materials can be kept neatly when epitaxially grown on the silicon-based substrate Crystal structure. Therefore, the problems of lattice mismatch and reverse phase domain between the silicon-based substrate and the Group III-V materials are reduced, and the yield of the Group III-V materials on the silicon-based substrate is improved.
  • the structure of the silicon-based substrate described above can refer to the silicon-based substrate in the base substrate in the foregoing embodiments, and the embodiments of the present application are here No longer.
  • An embodiment of the present application provides a method for manufacturing a base substrate, please refer to FIG. 8, the manufacturing method may include the following steps:
  • step 810 a silicon-based substrate is manufactured.
  • the method for manufacturing the silicon-based substrate in step 810 may include:
  • step 811 a sub-silicon substrate with periodic grooves on one side is manufactured.
  • a silicon wafer can be provided first, and the surface of the silicon wafer is a silicon (100) crystal plane, and then a mask process and a photolithography process are sequentially performed on the silicon wafer, and then the mask is removed to obtain a periodic surface The recessed silicon-based substrate.
  • the process of performing the masking process includes: forming a silicon dioxide (SiO 2 ) layer on the silicon (100) crystal plane, where chemical vapor deposition (CVD) technology or epitaxial growth may be used first Technology to form a SiO 2 layer on the silicon (100) crystal plane, CVD technology can be Plasma Enhanced Chemical Vapor Deposition (PECVD) technology, and then perform a patterning process (also called a patterning process) on the SiO 2 layer ) To obtain a SiO 2 mask, the patterning process includes photoresist coating, exposure, development, etching and photoresist stripping.
  • CVD chemical vapor deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the process of performing the photolithography process includes: exposing the silicon wafer formed with the SiO 2 mask by designated light, or bombarding the silicon wafer formed with the SiO 2 mask by designated electron beam, as specified above
  • the light may be ultraviolet light, such as deep ultraviolet light, and the exposure direction (ie, the irradiation direction) of the specified light is parallel to the [111] crystal direction; the processed silicon wafer with the SiO 2 mask formed is etched to obtain daughter silicon
  • the etching process may use a dry etching process or a wet etching process, for example, the silicon wafer formed with the SiO 2 mask is etched by a reactive ion etching technology in the dry etching process.
  • the process of removing the mask includes: in an achievable manner, the surface SiO 2 mask is removed by a dry etching process. In another achievable way, the surface SiO 2 mask is removed by a wet etching process. For example, the SiO 2 mask is etched by hydrofluoric acid.
  • FIG. 10 is a schematic cross-sectional view of a sub-silicon-based substrate 11 provided in an embodiment of the present application.
  • the surface of the sub-silicon-based substrate with periodic grooves 111 is a silicon (110) crystal plane. That is, the side boundary of the groove 111 is perpendicular to the bottom surface.
  • the width of the top of the groove may also be greater than the width of the bottom.
  • the cross-section of the groove 111 is an inverted trapezoid.
  • step 812 a silicon intermediate layer is formed on the side of the sub-silicon base substrate having the groove.
  • a molecular intermediate layer may be formed on the side of the sub-silicon base substrate with grooves using molecular beam epitaxy.
  • the molecular beam epitaxial growth technology is a kind of epitaxial growth technology.
  • the molecular beam epitaxy technology refers to putting the required crystalline material into a spray furnace under ultra-high vacuum conditions, heating the spray furnace to make the crystalline material
  • a silicon intermediate layer can be formed in a growth environment of 500 ° C to 700 ° C.
  • a silicon intermediate layer can be formed in a growth environment of 550 ° C to 650 ° C, as long as a silicon intermediate layer that meets the requirements can be grown.
  • the embodiment of the present application does not limit the temperature of the growth environment.
  • the silicon intermediate layer is composed of periodic convex structures, wherein each convex structure is located on the interval structure between two adjacent grooves, and each two adjacent convex structures are adjacent to ensure stable silicon Base substrate structure.
  • FIG. 11 and FIG. 4 are schematic diagrams of the growth process of the silicon intermediate layer on the sub-silicon substrate provided by the embodiment of the present application.
  • the embodiment of the present application uses FIG. 11 and FIG. 4 as examples The growth process of the silicon intermediate layer on the side of the sub-silicon base substrate with grooves will be described, wherein FIG. 11 is an intermediate process of the growth process of FIG. 4.
  • FIG. 11 shows that at a growth temperature of 600 ° C., molecular beam epitaxial growth technology is used to epitaxially grow a 250 nm silicon intermediate layer 12 on a sub-silicon base substrate 11 having periodic grooves 111 on the surface.
  • a 250 nm silicon intermediate layer 12 is grown on the sub-silicon base substrate 11, a stable silicon (111) crystal plane is constructed on the top of the silicon intermediate layer 12, which is the top of the silicon intermediate layer 12 A periodic raised structure 101 is constructed. 4 shows that at a growth temperature of 600 ° C., a 500 nm silicon intermediate layer 12 is epitaxially grown on a sub-silicon substrate 11 with periodic grooves 111 on the surface using molecular beam epitaxial growth technology (that is, at (On the basis of the silicon intermediate layer 12 shown in FIG. 11, a 250 nm silicon intermediate layer is grown). As can be seen from FIG.
  • the silicon intermediate layer 12 when a 500 nm silicon intermediate layer 12 is grown on the sub-silicon base substrate 11, the silicon intermediate layer 12
  • the silicon (111) stable crystal plane formed on the top of the layer 12 is adjacent, that is, the periodic convex structure 101 formed on the top of the silicon intermediate layer 12 is adjacent, and the final formation of the silicon-based substrate
  • An irregular hollow structure is constructed in the middle of the structure.
  • the hollow structure is composed of a groove 111 and a gap M between each two convex structures 101.
  • the hollow structure can effectively suppress dislocations caused by thermal expansion and contraction, further Improves the quality of the finally formed Group III-V material layer.
  • a group III-V material layer is formed on one side of the silicon-based substrate having a convex structure.
  • a molecular beam epitaxial growth technique may be used to form a group III-V material layer on a side of a silicon-based substrate having a convex structure, wherein the group III-V material buffer layer is used to buffer the lattice mismatch of the silicon-based substrate , Group III-V dislocation filter layer is used to filter the dislocation of silicon-based substrate.
  • the above step 820 may include:
  • step 821 a molecular beam epitaxial growth technique is used to form a buffer layer of Group III-V materials on the side of the silicon-based substrate having the convex structure.
  • the buffer layer of the group III-V material includes: an AlAs crystal layer and a GaAs crystal layer, and the GaAs crystal layer includes a first sub-GaAs crystal layer and a second sub-GaAs crystal layer.
  • a buffer layer of Group III-V material can be formed on the side of the silicon substrate with a convex structure by a three-step method.
  • the process of forming the buffer layer of Group III-V material may include the following steps :
  • step 8211 a molecular beam epitaxial growth technique is used to grow an AlAs crystal layer with a thickness of 5 nm to 15 nm on the side of the silicon substrate with the convex structure at 350 ° C to 400 ° C.
  • the growth of the AlAs crystal layer under a lower temperature environment can slow down the growth rate of the AlAs crystal layer on the side of the silicon substrate with the convex structure, which can further make each atom of the AlAs crystal layer grow in the correct position
  • it can effectively avoid the growth of the GaAs crystal layer directly on the raised structure of the silicon-based substrate Resulting in dislocations, thereby forming a high-quality group III-V material layer on the silicon-based substrate.
  • a molecular beam epitaxial growth technique is used to grow a first sub-GaAs crystal layer with a thickness of 20 nm to 40 nm on the AlAs crystal layer at 350 ° C to 400 ° C.
  • a molecular beam epitaxial growth technique is used to grow a second sub-GaAs crystal layer with a thickness of 400 nm to 600 nm on the GaAs crystal layer at 550 ° C to 600 ° C.
  • first growing the first sub-GaAs crystal layer in a low-temperature growth environment can slow down the growth rate of the first sub-GaAs crystal layer on the side of the silicon-based substrate having the convex structure, and further Each atom of the first sub-GaAs crystal layer is grown in the correct position, and then in a high-temperature growth environment, a high-quality second sub-GaAs crystal layer is grown on the first sub-GaAs crystal layer, which can suppress the reverse domain
  • the resulting dislocations form a high-quality group III-V material layer on the silicon-based substrate.
  • step 822 a molecular beam epitaxial growth technique is used to form a group III-V dislocation filter layer on the group III-V material buffer layer.
  • the group III-V dislocation filter layer includes: superimposed m periods of the first quantum well structure layer, the one quantum well structure layer may include an In 0.15 Ga 0.85 As crystal layer and a GaAs crystal layer sequentially stacked, m is a positive integer .
  • the group III-V dislocation filter layer may further include: n periodic second quantum well structure layers superimposed on m periodic first quantum well structure layers and p periodic superlattice structures, n and p are Positive integer.
  • the second quantum well structure layer may include an In 0.15 Al 0.85 As crystal layer and a GaAs crystal layer sequentially stacked, and the superlattice structure may include an Al 0.6 Ga 0.4 As crystal layer and a GaAs crystal layer sequentially stacked.
  • molecular beam epitaxial growth technology may be used to first form a m-period first quantum well structure layer on the III-V material buffer layer, and then form an n-period second quantum well structure layer on the first quantum well structure layer Layer, and finally form a p-period superlattice structure on the second quantum well structure layer to ensure the neat structure of each layer.
  • the growth temperature of the first quantum well structure layer may be 460 ° C to 510 ° C, the thickness of the In 0.15 Ga 0.85 As crystal layer and the GaAs crystal layer are both 10 nm, and the growth temperature of the second quantum well structure layer may be 460 ° C to At 510 °C, the thickness of In 0.15 Al 0.85 As crystal layer and GaAs crystal layer are both 10nm, the growth temperature of superlattice structure is 550 °C to 600 °C, the thickness of Al 0.6 Ga 0.4 As crystal layer and GaAs crystal layer are 2nm .
  • molecular beam epitaxy can be used to grow In 0.15 Ga 0.85 As with a thickness of 10 nm on the buffer layer of Group III-V materials in sequence at 480 ° C for 5 cycles.
  • the first quantum well structure layer may be at a temperature of 550 °C to 600 °C, the length of the thickness is 150nm to 250nm GaAs isolation layer, then at 480 °C, on the GaAs isolation layer in order to grow 5 cycles of Innm 0.15 Al 0.85 As crystal layer and GaAs crystal layer with a thickness of 10nm in order to obtain the second quantum well structure layer;
  • an In 0.15 Al 0.85 As crystal layer and a GaAs crystal layer each having a thickness of 10 nm and a period of 5 cycles can be directly stacked on the first quantum well structure layer at 480 ° C.
  • the second quantum well structure layer is sequentially stacked and grown with 5 cycles of Al 0.6 Ga 0.4 As crystal layer and GaAs crystal layer with a thickness of 2 nm in order to obtain super Lattice structure, further obtain high-quality three-five with surface roughness of about 1nm Group material single crystal thin film.
  • FIG. 14 is a surface atomic force micrograph of a substrate substrate formed with a group III-V dislocation filter layer provided by an embodiment of the present application.
  • the left ordinate and the upper abscissa Denotes the size, the unit of the size is micrometers, the ordinate on the right side represents the surface height (that is, the flatness of the surface), and the surface height unit is nanometers.
  • the surface roughness of the base substrate is about 0.8 nm, and a high-quality single crystal thin film of Group III-V material is formed on the surface.
  • the temperature of the above epitaxial growth process of each crystal layer is only a schematic illustration. In the actual implementation of the present application, other temperature ranges may also be used for epitaxial growth, which is not limited in the embodiments of the present application.
  • the manufacturing method of the base substrate provided by the embodiments of the present application, because one side of the formed silicon-based substrate is no longer a silicon (100) crystal plane, but has a periodic convex structure, through this
  • the raised structure can realize the self-annihilation of dislocations, limiting the dislocations caused by lattice mismatch and anti-phase domains to the layer of silicon-based substrate, so that the group III-V materials grow epitaxially on the silicon-based substrate , Can maintain a neat crystal structure.
  • the problems of lattice mismatch and reverse domain between the silicon-based substrate and the Group III-V materials are reduced, and the yield of the Group III-V materials on the silicon-based substrate is improved, thereby improving the silicon-based photoelectricity Device life and yield.
  • the grooves in the silicon-based substrate can be made using a mask process and a photolithography process, and the convex structure can be made using epitaxial growth technology, it can be compatible with the related processes in CMOS manufacturing, the manufacturing process is simple, and the manufacturing cost is relatively high low.
  • An embodiment of the present application provides a method for manufacturing a silicon-based substrate.
  • the manufacturing method refers to the foregoing step 810 and steps 811 to 812, which are not described in detail in the embodiment of the present application.
  • An embodiment of the present application provides an optoelectronic device.
  • the optoelectronic device includes: a base substrate and at least one optical film layer and / or at least one electrical film layer provided on the base substrate.
  • the base substrate is any base substrate provided in the embodiments of the present application.
  • the optoelectronic device refers to an optical device and / or an electrical device.
  • the optoelectronic device may be a quantum dot laser, detector, amplifier, modulator, CMOS electrical device, or waveguide device.
  • the convex can realize the self-annihilation of dislocations, limiting the dislocations caused by lattice mismatch and anti-phase domains to the layer of silicon-based substrate, so that when the group III-V materials are epitaxially grown on the silicon-based substrate, Maintain a neat crystal structure. Therefore, the problems of lattice mismatch and reverse phase domain between the silicon-based substrate and the Group III-V materials are reduced, and the yield of the Group III-V materials on the silicon-based substrate is improved.
  • the structure of the base substrate in the photovoltaic device described above can refer to the structure of the base substrate in the foregoing embodiments, and the embodiments of the present application are not described here. Repeat again.

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Abstract

一种硅基衬底(10)、衬底基板及其制造方法、光电器件，涉及电子技术应用领域，包括：硅基衬底(10)，硅基衬底(10)的一面具有周期性的凸起结构(101)，每个凸起结构(101)的侧面与底面存在倾角；设置在硅基衬底(10)具有凸起结构(101)的一面上的三五族材料层(20)。在该衬底基板(10)中，由于硅基衬底(10)的一面不再是硅(100)晶面，而是具有周期性的凸起结构(101)，该凸起结构(101)能够实现位错的自湮灭，将晶格失配以及反相畴所导致的位错限制在硅基衬底(10)这一层，使得三五族材料在该硅基衬底(10)上外延生长时，能够保持整齐的晶体结构，因此，能够减少硅基衬底(10)和三五族材料之间的晶格失配和反相畴等问题，提高三五族材料在该硅基衬底(10)上的良品率。用于在硅基衬底(10)上形成高质量的三五族材料。

Description

硅基衬底、衬底基板及其制造方法、光电器件
本申请要求于2018年11月02日提交的申请号为201811303611.8、发明名称为“硅基衬底、衬底基板及其制造方法、光电器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及电子技术应用领域，特别涉及一种硅基衬底、衬底基板及其制造方法、光电器件。
背景技术
硅基光电集成技术指的是在硅基衬底上集成光电器件的技术。采用该技术形成的光源、放大器或调制器等器件具有低成本、微尺寸以及高集成度的优点。
然而，由于硅是间接带隙材料，发光特性较差，而三五族(也称III-V族)材料具有优良的光学特性，因此，将三五族材料制备在硅基衬底上可以形成高效发光的器件，为光电器件的形成提供良好的基础。例如，该三五族材料可以为砷化铟(indium arsenide，InAs)或砷化镓(gallium arsenide，GaAs)。
但是，硅(100)晶面和三五族材料之间存在晶格失配和反相畴等问题，导致三五族材料在具有硅(100)晶面的硅基衬底上的形成极为困难。
发明内容
本申请提供了一种硅基衬底、衬底基板及其制造方法、光电器件，可以减少硅基衬底和三五族材料之间的晶格失配和反相畴等问题，提高三五族材料在硅基衬底上的良品率。
第一方面，本申请提供一种衬底基板，包括：
硅基衬底，所述硅基衬底的一面具有周期性的凸起结构，每个所述凸起结构的侧面与底面存在倾角，通过该倾角能够实现硅基衬底的位错的自湮灭，从而将位错抑制在该硅基衬底的凸起结构的侧面上；
设置在所述硅基衬底具有所述凸起结构的一面上的三五族材料层。
在该衬底基板中，由于硅基衬底的一面不再是硅(100)晶面，而是具有周期性的凸起结构，该凸起结构能够实现位错的自湮灭，将晶格失配以及反相畴所导致的位错限制在硅基衬底这一层，使得三五族材料在该硅基衬底上外延生长时，能够保持整齐的晶体结构，因此，减少了硅基衬底和三五族材料之间的晶格失配和反相畴等问题，提高了三五族材料在该硅基衬底上的良品率。
可选的，所述硅基衬底具有所述周期性的凸起结构的表面为硅(111)晶面。
硅(111)晶面能够有效抑制位错，使位错不再继续向上生长，并且反相畴在60°的晶面上几乎能够全部被抑制，因此更有利于三五族材料的外延生长。
可选的，所述硅基衬底包括：一面具有周期性的凹槽的子硅基衬底；以及设置在所述子硅基衬底具有所述凹槽的一面上的硅中间层，所述硅中间层由所述周期性的凸起结构组成；
其中，每个所述凸起结构位于两个相邻凹槽之间的间隔结构上，每两个相邻的所述凸起结构的侧面邻接(即该多个凸起结构的上表面是连续的表面)，从而可以实现稳定的硅基衬底结构。
可选的，所述凹槽的排布周期为200纳米(nanometer，nm)至800nm，每个所述凹槽的深度为200nm至1000nm，进一步的，所述凹槽的排布周期为300nm至500nm；每个所述凹槽的深度为400nm至600nm。
可选的，所述硅中间层的厚度为300nm至800nm，该硅中间层的厚度指的是硅中间层以凹槽111的顶部平台为基准面的厚度，进一步的，所述硅中间层的厚度为450nm至650nm。
该凹槽可以有多种，在一种可选的实现方式中，所述子硅基衬底具有所述周期性的凹槽的表面为硅(110)晶面，每个凹槽的侧面边界垂直于底面。
在另一种可选的实现方式中，凹槽的界面呈倒梯形，每个所述凹槽的顶部宽度为100nm至400nm；每个所述凹槽的底部宽度为50nm至200nm。进一步的，每个所述凹槽的顶部宽度为120nm至160nm，每个所述凹槽的底部宽度为100nm至120nm。
可选的，所述三五族材料层包括在所述硅基衬底具有所述凸起结构的一面上依次叠加设置的三五族材料缓冲层和三五族位错过滤层，所述三五族材料缓冲层用于缓冲所述硅基衬底的晶格失配，所述三五族位错过滤层用于过滤所述硅基衬底的位错。
可选的，所述三五族位错过滤层的厚度为0微米(micron，μm)至2μm；所述三五族位错过滤层的表面粗糙度为0.5nm至1.6nm。进一步的，所述三五族位错过滤层的厚度为0.8μm至1.8μm，所述三五族位错过滤层的表面粗糙度为0.8nm至1.4nm。表面粗糙度可以表征结构层表面的光滑程度，表面粗糙度的值越小，该结构层的表面越光滑。
可选的，所述三五族材料缓冲层包括：
依次叠加设置在所述硅基衬底具有所述凸起结构的一面上的AlAs(砷化铝)晶层和GaAs(砷化镓)晶层。
由于Al(铝)的熔点约为660℃(摄氏度)，Ga(镓)的熔点约为30℃，AlAs晶层的熔点较GaAs晶层的熔点高，当在凸起结构上直接设置GaAs晶层时，由于Ga的熔点较低，因此GaAs晶层的原子在硅基衬底上会出现移动，进而产生位错，当在凸起结构上设置AlAs晶层时，由于Al的熔点较高，因此AlAs晶层的原子具有更高的键能，在硅基衬底上不会移动，从而避免晶格失配所导致的位错。所以先在硅基衬底的凸起结构上设置AlAs晶层，再在AlAs晶层上设置GaAs晶层，可以有效的避免直接将GaAs晶层设置在硅基衬底上所导致的位错，从而在硅基衬底上形成高质量的三五族材料层。
可选的，所述三五族材料缓冲层的厚度为0nm至600nm；所述GaAs晶层的表面粗糙度为0.5nm至1.6nm。进一步的，所述三五族材料缓冲层的厚度为200nm至600nm；所述GaAs晶层的表面粗糙度为0.8nm至1.4nm。
可选的，所述三五族位错过滤层包括：叠加设置的m个周期的第一量子阱结构层，每个周期的所述第一量子阱结构层包括依次叠加的In 0.15Ga 0.85As晶层和GaAs晶层，m为正整数。其中，In 0.15Ga 0.85As表示In(铟)的比例为15％，Ga的比例为85％的InGaAs(砷化铟镓)。
上述第一量子阱结构层中，由于In 0.15Ga 0.85As的晶格比GaAs的晶格大，因此，当先在三五族材料缓冲层上设置In 0.15Ga 0.85As晶层时，会产生应力，从而形成应力场，In 0.15Ga 0.85As晶层所产生的应力场能够将位错所产生的应力抵消掉，从而抑制位错继续向上延伸。
可选的，所述三五族位错过滤层还包括：叠加在所述m个周期的第一量子阱结构层上的n个周期的第二量子阱结构层以及p个周期的超晶格结构，所述n个周期的第二量子阱结构层叠加设置，所述p个周期的超晶格结构叠加设置，n和p为正整数；
每个周期的所述第二量子阱结构层包括依次叠加的In 0.15Al 0.85As晶层和GaAs晶层；
每个周期的所述超晶格结构包括依次叠加的Al 0.6Ga 0.4As晶层和GaAs晶层。
其中，第二量子阱结构层中的In 0.15Al 0.85As晶层抑制位错的效果相比于上述第一量子阱结构层中的In 0.15Ga 0.85As晶层，效果更好，但是由于Al的熔点比Ga高，若直接在三五族材料缓冲层上形成In 0.15Al 0.85As晶层，使Al原子移动较为困难，当原子所处的位置不对时，难以进行调整，从而难以抑制位错的延伸。当先在三五族材料缓冲层上生长第一量子阱结构层，再在第一量子阱结构层上生长第二量子阱结构层时，将In 0.15Ga 0.85As晶层作为铺垫，再形成In 0.15Al 0.85As晶层，便可以更好的抑制位错，从而在硅基衬底上形成高质量的三五族材料层。
在第二量子阱结构层中，由于Al原子过多时，也会产生一定的位错。因此，该第二量子阱结构层包括依次叠加的In 0.15Al 0.85As晶层和GaAs晶层，可以有效抑制Al原子过多所产生的位错。
在超晶格结构中，依次叠加的Al 0.6Ga 0.4As晶层和GaAs晶层可以使得最终形成的三五族位错过滤层的表面平整光滑，从而得到高质量的衬底基板。
可选的，m＝n＝p＝5，此时，三五族位错过滤层的厚度较薄，且能够实现较好的抑制位错的效果。该m、n和p的值越大，该三五族过滤层抑制位错的效果越好。
第二方面，提供一种硅基衬底，包括：
一面具有周期性的凹槽的子硅基衬底；以及设置在所述凹槽上的硅中间层，所述硅中间层由所述周期性的凸起结构组成；
其中，每个所述凸起结构位于两个相邻凹槽之间的间隔结构上，每两个相邻的所述凸起结构的侧面邻接；
所述硅基衬底具有所述周期性的凸起结构的表面为硅(111)晶面。
可选的，所述子硅基衬底具有所述周期性的凹槽的表面为硅(110)晶面。
第三方面，提供一种衬底基板的制造方法，包括：
制造硅基衬底，所述硅基衬底的一面具有周期性的凸起结构，每个所述凸起结构的侧面与底面存在倾角；
在所述硅基衬底具有所述凸起结构的一面上形成三五族材料层。
采用该制造方法制造得到的衬底基板中，由于硅基衬底的一面不再是硅(100)晶面，而是具有周期性的凸起结构，该凸起结构能够实现位错的自湮灭，将晶格失配以及反相畴所导致的位错限制在硅基衬底这一层，使得三五族材料在该硅基衬底上外延生长时，能够保持整齐的晶体结构。因此，减少了硅基衬底和三五族材料之间的晶格失配和反相畴等问题，提高了三五族材料在该硅基衬底上的良品率。
其中，所述硅基衬底具有所述周期性的凸起结构的表面为硅(111)晶面。
可选的，所述制造硅基衬底，包括：
制造一面具有周期性的凹槽的子硅基衬底；
在所述子硅基衬底具有所述凹槽的一面上形成硅中间层，所述硅中间层由所述周期性的凸起结构组成，且每个所述凸起结构位于两个相邻凹槽之间的间隔结构上，每两个相邻的所述凸起结构邻接。
所述子硅基衬底具有所述周期性的凹槽的表面为硅(110)晶面，此时，所述制造一面具有周期性的凹槽的子硅基衬底，包括：
提供一硅片，所述硅片的表面为硅(100)晶面；
采用深紫外光刻工艺对所述硅片进行刻蚀，得到所述子硅基衬底。
可选的，所述在所述子硅基衬底具有所述凹槽的一面上形成硅中间层，包括：
采用分子束外延生长技术，在所述子硅基衬底具有所述凹槽的一面上形成硅中间层。
所述在所述硅基衬底具有所述凸起结构的一面上形成三五族材料层，包括：采用分子束外延生长技术，在所述硅基衬底具有所述凸起结构的一面上形成三五族材料层。
可选的，可以采用分子束外延生长技术在硅基衬底具有凸起结构的一面上形成三五族材料层，此时，所述采用分子束外延生长技术，在所述硅基衬底具有所述凸起结构的一面上形成三五族材料层，包括：
采用分子束外延生长技术，在所述硅基衬底具有所述凸起结构的一面上形成三五族材料缓冲层；
采用分子束外延生长技术，在所述三五族材料缓冲层上形成三五族位错过滤层；
其中，所述三五族材料缓冲层用于缓冲所述硅基衬底的晶格失配，所述三五族位错过滤层用于过滤所述硅基衬底的位错。
可选的，所述三五族材料缓冲层包括：AlAs晶层和GaAs晶层，所述GaAs晶层包括第一子GaAs晶层和第二子GaAs晶层；
可以通过三步法在硅基衬底具有凸起结构的一面上形成三五族材料缓冲层，此时，所述采用分子束外延生长技术，在所述硅基衬底具有所述凸起结构的一面上形成三五族材料缓冲层，包括：
采用分子束外延生长技术，在350℃至400℃下，在所述硅基衬底具有所述凸起结构的一面上生长厚度为5nm至15nm的AlAs晶层；
采用分子束外延生长技术，在350℃至400℃下，在所述AlAs晶层上生长厚度为20nm至40nm的所述第一子GaAs晶层；
采用分子束外延生长技术，在550℃至600℃下，在所述第一子GaAs晶层上生长厚度为400nm至600nm的所述第二子GaAs晶层。
所述三五族位错过滤层包括：叠加设置的m个周期的第一量子阱结构层，所述第一量子阱结构层包括依次叠加的In 0.15Ga 0.85As晶层和GaAs晶层，m为正整数。
先在低温的生长环境中生长第一子GaAs晶层，可以减慢在硅基衬底具有凸起结构的一面上生长第一子GaAs晶层的速率，进一步能够使得该第一子GaAs晶层的每个原子生长在正确的位置，再在高温的生长环境中，在第一子GaAs晶层上生长高质量的第二子GaAs晶层，能够抑制反相畴所导致的位错，从而在硅基衬底上形成高质量的三五族材料层。
可选的，所述三五族位错过滤层还包括：叠加在所述m个周期的第一量子阱结构层上的n个周期的第二量子阱结构层以及p个周期的超晶格结构，所述n个周期的第二量子阱结构层叠加设置，所述p个周期的超晶格结构叠加设置，n和p为正整数；
每个周期的所述第二量子阱结构层包括依次叠加的In 0.15Al 0.85As晶层和GaAs晶层；
每个周期的所述超晶格结构包括依次叠加的Al 0.6Ga 0.4As晶层和GaAs晶层。
可以采用分子束外延生长技术，先在三五族材料缓冲层上形成m个周期的第一量子阱结构层，再在第一量子阱结构层形成n个周期的第二量子阱结构层，最后在第二量子阱结构层上形成p个周期的超晶格结构，以保证每一层的结构整齐。
可选的，m＝n＝p＝5；
所述第一量子阱结构层的生长温度为460℃至510℃，In 0.15Ga 0.85As晶层和GaAs晶层的厚度均为10nm；所述第二量子阱结构层的生长温度为460℃至510℃，In 0.15Al 0.85As晶层和GaAs晶层的厚度均为10nm；所述超晶格结构的生长温度为550℃至600℃，Al 0.6Ga 0.4As晶层和GaAs晶层的厚度均为2nm。
第四方面，提供一种光电器件，包括：第一方面所述的衬底基板，以及设置在所述衬底基板上的至少一层光学膜层和/或至少一层电学膜层。
可选的，所述光电器件为量子点激光器、探测器、放大器、调制器、互补金属氧化物半导体CMOS电学器件或波导器件。
本申请提供的技术方案至少包括以下有益效果：
本申请提供的硅基衬底、衬底基板及其制造方法、光电器件，由于硅基衬底的一面不再是硅(100)晶面，而是具有周期性的凸起结构，该凸起结构能够实现位错的自湮灭，将晶格失配以及反相畴所导致的位错限制在硅基衬底这一层，使得三五族材料在该硅基衬底上外延生长时，能够保持整齐的晶体结构，因此，减少了硅基衬底和三五族材料之间的晶格失配和反相畴等问题，提高了三五族材料在该硅基衬底上的良品率。
附图说明
图1是本发明实施例提供的一种衬底基板的截面示意图；
图2是本发明实施例提供的另一种衬底基板的截面示意图；
图3是本发明实施例提供的一种衬底基板的局部放大示意图；
图4是本发明实施例提供的一种硅基衬底的截面示意图；
图5是本发明实施例提供的另一种硅基衬底的截面示意图；
图6是本发明实施例提供的一种表面扫描电子显微图的对比示意图；
图7是本发明实施例提供的一种衬底基板的X射线衍射谱示意图；
图8是本发明实施例提供的一种衬底基板的制造方法流程图；
图9是本发明实施例提供的一种硅基衬底的制造方法流程图；
图10是本发明实施例提供的一种子硅基衬底的截面示意图；
图11是本发明实施例提供的一种250nm的硅中间层在子硅基衬底上的生长示意图；
图12是本发明实施例提供的一种形成三五族材料层的方法流程图；
图13是本发明实施例提供的一种形成三五族材料缓冲层的方法流程图；
图14是本发明实施例提供的一种衬底基板的表面原子力显微图。
具体实施方式
本申请实施例涉及对硅基衬底以及基于该硅基衬底制造的衬底基板的改进，硅属于立方晶系，本申请实施例中，涉及多种晶面的硅片，分别为硅(100)晶面的硅片、硅(110)晶面的硅片和硅(111)晶面的硅片，为了便于读者理解，对这些硅片进行如下介绍：
具有硅(100)晶面的硅片也称硅片(100)，[100]是晶向指数，硅(100)晶面的法线与[100]晶向是平行的，也就是说(100)晶面垂直于[100]晶向。
具有硅(110)晶面的硅片也称硅片(110)，[110]是晶向指数，硅(110)晶面的法线与[110]晶向是平行的，也就是说(110)晶面垂直于[110]晶向。
具有硅(111)晶面的硅片也称硅片(111)，[111]是晶向指数，硅(111)晶面的法线与[111]晶向是平行的，也就是说(111)晶面垂直于[111]晶向。
需要说明的是，晶体中各种方向上的原子列叫作晶向。在晶胞上建立坐标系，即晶体立方系，则上述[111]就是方向向量的坐标，即[111]表示过原点和点x＝1，y＝1，z＝1的直线上所经过的原子，如果晶体为体心立方晶胞，则此晶向经过正方体对角线上的原子。
目前，三五族材料(III-Vmaterial)通过外延生长的方式形成在具有硅(100)晶面的硅基衬底上，外延生长技术是指在单晶衬底(也称基片)上生长一层与衬底晶向相同的单晶层的技术，外延生长指的是采用外延生长技术进行单晶层的生长。其中，具有硅(100)晶面的硅基衬底的表面是平面。由于硅和三五族材料的晶格常数不同以及极性和非极性键的差异，会产生晶格失配以及反相畴，从而导致三五族材料在硅基衬底上的外延生长具有大量位错和缺陷，也即是会导致三五族材料的原子在硅基衬底上的局部呈现不规则排列，进一步导致在硅基衬底上难以实现高质量的三五族材料的外延生长。
本申请实施例提供了一种衬底基板，请参考图1，图1为本申请实施例提供的衬底基板的截面示意图，该衬底基板包括：
硅基衬底10和设置在硅基衬底10上的三五族材料层20。
如图1所示，该硅基衬底10的一面具有周期性的凸起结构101，该周期性的凸起结构101指的是多个凸起结构，且在硅基衬底上具有一定的分布周期，每个凸起结构101的侧面W与底面存在倾角，通过该倾角能够实现硅基衬底10的位错的自湮灭，从而将位错抑制在该硅基衬底的凸起结构的侧面W上，该三五族材料层20设置于上述硅基衬底具有凸起结构101的一面上。
综上所述，本申请实施例提供的衬底基板中，由于硅基衬底的一面不再是硅(100)晶面，而是具有周期性的凸起结构，该凸起结构能够实现位错的自湮灭，将晶格失配以及反相畴所导致的位错限制在硅基衬底这一层，使得三五族材料在该硅基衬底上外延生长时，能够保持整齐的晶体结构。因此，减少了硅基衬底和三五族材料之间的晶格失配和反相畴等问题，提高了三五族材料在该硅基衬底上的良品率。
示例的，上述硅基衬底具有周期性的凸起结构101的表面为硅(111)晶面，例如，该凸起结构的侧面W与底面的倾角为60度，此时，上述硅基衬底具有周期性的凸起结构101的表面的截面可以为顶角为60度的等边三角形所连接形成的锯齿形结构。硅(111)晶面能够 有效抑制位错，使位错不再继续向上生长，并且反相畴在60°的晶面上几乎能够全部被抑制，因此更有利于三五族材料的外延生长。
可选的，上述硅基衬底中的凸起结构沿指定方向等距离阵列排布，各个凸起结构的形状和大小可以相同，每两个凸起结构的距离可以为360nm，其中，该指定方向可以为该硅基衬底的行方向或列方向，每个凸起结构的延伸方向可以垂直于该指定方向，且平行于硅基衬底的底面，例如为图1中垂直于纸面的方向，每两个凸起结构的距离指的是在指定方向上该两个凸起结构的指定点(例如中心点)的距离，这样可以实现对位错更好的抑制效果，且每两个相邻的凸起结构之间呈邻接状，(即该多个凸起结构的上表面是连续的表面)，从而实现稳定的硅基衬底结构。需要说明的是，可以根据实验情况以及实际需求设置每两个凸起结构的距离，本申请实施例对此不做限定。
示例的，请参考图2，图2为本申请实施例提供的一种衬底基板的截面示意图，在该衬底基板中，硅基衬底10包括：一面具有周期性的凹槽111的子硅基衬底11，以及设置在子硅基衬底11具有凹槽111的一面上的硅中间层12。该周期性的凹槽111指的是多个凹槽，且在子硅基衬底上具有一定的分布周期，该周期性的凹槽111可以通过对硅片(100)执行掩膜工艺和光刻工艺得到，周期性的凹槽111均为盲槽。
上述硅中间层12由周期性的凸起结构101组成，也即是，该硅中间层12包括多个凸起结构，其中，每个凸起结构位于两个相邻凹槽之间的间隔结构112上，该间隔结构112用于隔开相邻的两个凹槽，例如，该间隔结构可以称为隔档或者挡墙。示例的，请参考图3，图3是该衬底基板的局部放大图，在该衬底基板中，每个凸起结构101位于两个相邻凹槽之间的间隔结构112上，上述凸起结构可以采用外延生长技术生长得到，如图2所示，该周期性的凸起结构101与周期性的间隔结构112的排布周期相同。该每两个相邻的凸起结构101的侧面W邻接，也即是，每两个相邻的凸起结构的侧面相交，这样各个凸起结构之间不存在间隙，可以保证稳定的硅基衬底结构。
如图4和图5所示，图4和图5分别为本申请实施例提供的一种硅基衬底的截面示意图，在一种可选的实现方式中，请参考图4，每个凹槽111的顶部宽度大于底部宽度，例如该凹槽111的截面呈倒梯形。示例的，每个凹槽的顶部宽度可以为100nm至400nm，底部宽度可以为50nm至200nm。进一步的，每个凹槽的顶部宽度可以为120nm至160nm，底部宽度可以为100nm至120nm。在另一种可选的实现方式中，请参考图5，上述子硅基衬底具有周期性的凹槽111的表面为硅(110)晶面，每个凹槽的侧面边界垂直于底面。
如图4和图5所示，在指定方向上，每个凹槽的排布周期可以为200nm至800nm，也即是在指定方向上每两个相邻的凹槽中心的距离可以为200nm至800nm，进一步的，每个凹槽的排布周期可以为300nm至500nm。每个凹槽的深度可以为200nm至1000nm，进一步的，每个凹槽的深度可以为400nm至600nm。每个凹槽的延伸方向可以垂直于该指定方向，且平行于硅基衬底的底面，例如为图4和图5中垂直于纸面的方向，周期性的凹槽可以在硅中间层生长过程中，有效抑制反相畴。
在上述硅基衬底中，当在子硅基衬底上生长硅中间层时，硅中间层以间隔结构为基底向上生长，在硅中间层的生长过程中，每两个相邻的凸起结构由最初的不邻接状态向最终的邻接状态过渡，因此，最终形成的硅基衬底的结构中间构造出了不规则的镂空结构。为了进一 步对该镂空结构进行说明，请参考图4，图4示出了镂空结构的放大示意图，该镂空结构由凹槽111以及每两个凸起结构101之间的间隙M组成，该镂空结构沿指定方向等距离阵列排布，各个镂空结构的形状和大小可以相同，其中，该指定方向可以为该硅基衬底的行方向或列方向，每个镂空结构的延伸方向可以垂直于该指定方向，且平行于硅基衬底的底面，例如为图4中垂直于纸面的方向。晶层在温度变化时会出现热胀冷缩的现象，进一步会产生位错，该镂空结构位于每两个相邻的间隔结构之间，也位于每两个相邻的凸起结构之间，可以将每两个相邻的间隙结构隔开，也可以将每两个相邻的凸起结构隔开，在热胀冷缩时，抵消了一部分应力，从而有效的抑制了硅中间层热胀冷缩所导致的位错，可以减少硅基衬底的热膨胀，进一步提高了最终形成的三五族材料层的质量。其中，应力指的是物体由于外因(受力、湿度、温度场变化等)而变形时，在物体内各部分之间产生的相互作用力，应力用以抵抗外因的作用，并使物体从变形后的位置恢复到变形前的位置，
相关技术中，将三五族材料在具有硅(100)晶面的硅基衬底上外延生长的方式包括：在硅(100)晶面的斜切衬底上实现三五族材料的直接外延生长；或者，在锗硅虚拟衬底(即该衬底不是纯硅基衬底，而是掺杂了锗的硅基衬底)上实现三五族的外延生长；或者，在具有双原子台阶的硅基衬底上实现三五族材料的直接外延生长。其中，在硅(100)晶面的斜切衬底以及具有双原子台阶的硅基衬底上实现三五族材料的直接外延生长，所采用的硅基衬底都无法采用传统的互补金属氧化物半导体(Complementary Metal-Oxide-Semiconductor，CMOS)制造中的相关工艺(例如掩膜工艺和光刻工艺)制造，需要采用复杂工艺制成，因此制造成本较高。
本申请实施例提供的衬底基板，由于上述凹槽可以采用掩膜工艺和光刻工艺制成，凸起结构可以采用外延生长技术制成，因此可以兼容CMOS制造中的相关工艺，制造工艺简单，制造成本较低。
可选的，如图2所示，该硅中间层12的厚度可以为300nm至800nm，该硅中间层12的厚度指的是硅中间层以凹槽111的顶部平台为基准面的厚度，进一步的，该硅中间层12的厚度可以为450nm至650nm。
需要说明的是，本申请实施例仅对上述凹槽与凸起结构的排布周期、凹槽的深度、凹槽的顶部宽度、凹槽的底部宽度以及硅中间层的厚度这类参数的大小做示意性的说明，在实际应用时，可以根据实验情况以及实际需求对这些参数进行调整，以使三五族材料在硅基衬底上达到较好的外延生长效果，本申请实施例对此不做限定。
请参考图2，上述三五族材料层20可以包括在硅基衬底10具有凸起结构101的一面上依次叠加设置的三五族材料缓冲层21和三五族位错过滤层22，该三五族材料缓冲层21用于缓冲硅基衬底10的晶格失配，该三五族位错过滤层22用于过滤硅基衬底10的位错。
示例的，上述三五族材料缓冲层21包括：依次叠加设置在硅基衬底10具有凸起结构101的一面上的砷化铝(Aluminum arsenide，AlAs)晶层210和砷化镓(gallium arsenide，GaAs)晶层211。
由于Al的熔点约为660摄氏度，Ga的熔点约为30摄氏度，AlAs晶层的熔点较GaAs晶层的熔点高，当在凸起结构上直接设置GaAs晶层时，由于Ga的熔点较低，因此GaAs晶层的原子在硅基衬底上会出现移动，进而产生位错，当在凸起结构上设置AlAs晶层时，由于 Al的熔点较高，因此AlAs晶层的原子具有更高的键能，从而在硅基衬底上不会移动，从而避免晶格失配所导致的位错。所以先在硅基衬底的凸起结构上设置AlAs晶层，再在AlAs晶层上设置GaAs晶层，可以有效的避免直接将GaAs晶层设置在硅基衬底上所导致的位错，从而在硅基衬底上形成高质量的三五族材料层。
可选的，该三五族材料缓冲层21的厚度可以为0nm至600nm，进一步的，该三五族材料缓冲层21的厚度可以为200nm至600nm。该GaAs晶层的表面粗糙度可以为0.5nm至1.6nm，进一步的，该GaAs晶层的表面粗糙度可以为0.8nm至1.4nm。表面粗糙度可以表征结构层表面的光滑程度，表面粗糙度的值越小，该结构层的表面越光滑。
需要说明的是，上述三五族材料缓冲层还可以由其他结构组成，只要能够缓冲硅基衬底的晶格失配即可，例如，上述三五族材料缓冲层包括：依次叠加设置在硅基衬底具有凸起结构的一面上的AlAs晶层和磷化镓(galzium phosPhide，GaP)晶层，其中，AlAs晶层的厚度和作用可以与上述三五族材料缓冲层的AlAs晶层相同；又例如，上述三五族材料缓冲层仅包括：设置在硅基衬底具有凸起结构的一面上的AlAs晶层或GaP晶层。
示例的，上述三五族位错过滤层22的厚度可以为0μm至2μm，三五族位错过滤层22的表面粗糙度可以为0.5nm至1.6nm，进一步的，该三五族位错过滤层的厚度可以为0.8μm至1.8μm，三五族位错过滤层的表面粗糙度可以为0.8nm至1.4nm。
如图2所示，该三五族位错过滤层22包括：m个周期的第一量子阱结构层220，该m个周期的第一量子阱结构层220叠加设置，每个周期的第一量子阱结构层220包括依次叠加的In 0.15Ga 0.85As晶层和GaAs晶层，m为正整数。其中，In 0.15Ga 0.85As表示In(铟)的比例为15％，Ga(镓)的比例为85％的InGaAs(砷化铟镓)。
需要说明的是，上述第一量子阱结构层中，由于In 0.15Ga 0.85As的晶格比GaAs的晶格大，因此，当先在三五族材料缓冲层上设置In 0.15Ga 0.85As晶层时，会产生应力，从而形成应力场，In 0.15Ga 0.85As晶层所产生的应力场能够将位错所产生的应力抵消掉，从而抑制位错继续向上延伸。
示例的，该三五族位错过滤层22还可以包括：叠加在m个周期的第一量子阱结构层220上的n个周期的第二量子阱结构层221以及p个周期的超晶格结构222，n个周期的第二量子阱结构层221叠加设置，p个周期的超晶格结构222叠加设置，n和p为正整数。该每个周期的第二量子阱结构层221包括依次叠加的In 0.15Al 0.85As晶层和GaAs晶层，每个周期的超晶格结构222包括依次叠加的Al 0.6Ga 0.4As晶层和GaAs晶层。其中，In 0.15Al 0.85As表示In(铟)的比例为15％，Al(铝)的比例为85％的InGaAs(砷化铟铝)Al 0.6Ga 0.4As表示Al(铝)的比例为60％，Ga(镓)的比例为40％的AlGaAs(砷化铝镓)。
其中，第二量子阱结构层中的In 0.15Al 0.85As晶层抑制位错的效果相比于上述第一量子阱结构层中的In 0.15Ga 0.85As晶层，效果更好，但是由于Al的熔点比Ga高，若直接在三五族材料缓冲层上形成In 0.15Al 0.85As晶层，使Al原子移动较为困难，当原子所处的位置不对时，难以进行调整，从而难以抑制位错的延伸。当先在三五族材料缓冲层上生长第一量子阱结构层，再在第一量子阱结构层上生长第二量子阱结构层时，将In 0.15Ga 0.85As晶层作为铺垫，再形成In 0.15Al 0.85As晶层，便可以更好的抑制位错，从而在硅基衬底上形成高质量的三五族材料层。
需要说明的是，在第二量子阱结构层中，由于Al原子过多时，也会产生一定的位错，因 此，该第二量子阱结构层包括依次叠加的In 0.15Al 0.85As晶层和GaAs晶层，可以有效抑制Al原子过多所产生的位错。
在超晶格结构中，依次叠加的Al 0.6Ga 0.4As晶层和GaAs晶层可以使得最终形成的三五族位错过滤层的表面平整光滑，从而得到高质量的衬底基板。
可选的，上述m＝n＝p＝5，此时，三五族位错过滤层的厚度较薄，且能够实现较好的抑制位错的效果。需要说明的是，该m、n和p的值越大，该三五族过滤层抑制位错的效果越好，本申请在实际应用时，可以根据需要选择合适的第一量子阱结构层、第二量子阱结构层以及超晶格结构层的周期值，本申请实施例对此不做限定。
请参考图6，图6为本申请实施例提供的一种表面扫描电子显微图的对比示意图，在图6中，直线T的左侧区域为相关技术所提供的衬底基板的表面扫描电子显微图，右侧区域为本申请实施例所提供的衬底基板的表面扫描电子显微图，由图6可以看出，相关技术所提供的衬底基板中，三五族材料层和硅基衬底之间存在大量的反相畴和高密度位错，本申请实施例所提供的衬底基板中，硅基衬底上的三五族材料层高度平整、无反相畴和明显位错。
进一步的，请参考图7，图7为本申请实施例提供的衬底基板的X射线衍射谱，在图7中，纵坐标表示X射线的衍射相对强度，横坐标表示X射线的衍射扫描角度Ω(Omega)，Ω的单位为“度”。MQWs指的是衬底基板中的三五族位错过滤层结构。由于X射线衍射谱的半高宽越小，对应的三五族材料层的品质越高。由图7可以看出，衬底基板的X射线衍射谱的半高宽约为硅基衬底的一倍，相较于传统的衬底基板，其X射线衍射谱的半高宽较小，因此，本申请实施例所提供的衬底基板的结构，能够有效减少硅基衬底和三五族材料之间的晶格失配和反相畴等问题，品质较高。
需要说明的是，本申请实施例仅对三五族材料缓冲层的厚度和表面粗糙度以及三五族位错过滤层的厚度和表面粗糙度这类参数的大小做示意性的说明，本申请在实际应用时，可以根据实验情况以及实际需求对这些参数进行调整，以使三五族材料在硅基衬底上达到较好的外延生长效果，本申请实施例对此不做限定。
综上所述，本申请实施例提供的衬底基板中，由于硅基衬底的一面不再是硅(100)晶面，而是具有周期性的凸起结构，该凸起结构能够实现位错的自湮灭，将晶格失配以及反相畴所导致的位错限制在硅基衬底这一层，使得三五族材料在该硅基衬底上外延生长时，能够保持整齐的晶体结构，因此，减少了硅基衬底和三五族材料之间的晶格失配和反相畴等问题，提高了三五族材料在该硅基衬底上的良品率，进而提高了硅基光电器件的寿命以及良品率。并且由于硅基衬底中的凹槽可以采用掩膜工艺和光刻工艺制成，凸起结构可以采用外延生长技术制成，因此可以兼容CMOS制造中的相关工艺，制造工艺简单，制造成本较低。
本申请实施例提供了一种硅基衬底，请参考图4和图5，该硅基衬底包括：
一面具有周期性的凹槽111的子硅基衬底11，以及设置在凹槽111上的硅中间层12，该硅中间层12由周期性的凸起结构101组成，其中，每个凸起结构位于两个相邻凹槽之间的间隔结构上，每两个相邻的凸起结构的侧面邻接，以保证稳定的硅基衬底结构。
示例的，该硅基衬底具有周期性的凸起结构101的表面为硅(111)晶面，该子硅基衬底具有周期性的凹槽111的表面为硅(110)晶面。
综上所述，本申请实施例提供的硅基衬底中，由于硅基衬底的一面不再是硅(100)晶面，而是具有周期性的凸起结构，该凸起结构能够实现位错的自湮灭，将晶格失配以及反相畴所导致的位错限制在硅基衬底这一层，使得三五族材料在该硅基衬底上外延生长时，能够保持整齐的晶体结构。因此，减少了硅基衬底和三五族材料之间的晶格失配和反相畴等问题，提高了三五族材料在该硅基衬底上的良品率。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的硅基衬底的结构，可以参考前述实施例中衬底基板中的硅基衬底，本申请实施例在此不再赘述。
本申请实施例提供了一种衬底基板的制造方法，请参考图8，该制造方法可以包括以下步骤：
在步骤810中，制造硅基衬底。
该硅基衬底的一面具有周期性的凸起结构，每个凸起结构的侧面与底面存在倾角。可选的，请参考图9，上述步骤810中制造硅基衬底的方法可以包括：
在步骤811中，制造一面具有周期性的凹槽的子硅基衬底。
可选的，可以先提供一硅片，该硅片的表面为硅(100)晶面，然后对该硅片依次执行掩膜工艺和光刻工艺，然后去除掩膜，得到一面具有周期性的凹槽的子硅基衬底。
示例的，执行掩膜工艺的过程包括：在硅(100)晶面形成二氧化硅(Silicon dioxide，SiO 2)层，其中，可以先采用化学气相沉积(Chemical Vapor Deposition，CVD)技术或者外延生长技术在该硅(100)晶面形成SiO 2层，CVD技术可以为等离子增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)技术，然后对该SiO 2层执行一次构图工艺(也称图形化工艺)，得到SiO 2掩膜，该构图工艺包括光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。
相应的，执行光刻工艺的过程包括：通过指定光线对形成有SiO 2掩模的硅片进行曝光处理，或者，通过指定电子束对形成有SiO 2掩模的硅片进行轰击处理，前述指定光线可以为紫外光，例如深紫外光，该指定光线的曝光方向(即照射方向)平行于[111]晶向；对处理后的形成有SiO 2掩模的硅片进行刻蚀，得到子硅基衬底，该刻蚀过程可以采用干刻工艺或湿刻工艺，例如通过干刻工艺中的反应离子刻蚀技术对形成有SiO 2掩模的硅片进行刻蚀。
相应的，去除掩膜的过程包括：在一种可实现方式中，通过干刻工艺移除表面SiO 2掩模。在另一种可实现方式中，通过湿刻工艺移除表面SiO 2掩模。例如通过氢氟酸对SiO 2掩模进行刻蚀。
示例的，请参考图10，图10为本申请实施例提供的一种子硅基衬底11的截面示意图，子硅基衬底具有周期性的凹槽111的表面为硅(110)晶面，也即是该凹槽111的侧面边界垂直于底面，本申请在实际实现时，该凹槽的顶部宽度也可以大于底部宽度，例如该凹槽111的截面呈倒梯形。该子硅基衬底的结构可以参考前述实施例所提供的子硅基衬底的结构，本申请实施例对此不做赘述。
在步骤812中，在子硅基衬底具有凹槽的一面上形成硅中间层。
示例的，可以采用分子束外延生长技术，在子硅基衬底具有凹槽的一面上形成硅中间层。其中，分子束外延生长技术是外延生长技术的一种，分子束外延技术指的是在超高真空条件 下，把所需要的结晶材料放入到喷射炉中，将喷射炉加热，使结晶材料形成分子束，并以一定的热运动速度，按一定的比例从喷射炉中喷射到衬底上，以进行晶体外延生长的一种技术。示例的，可以在500℃至700℃的生长环境下形成硅中间层，进一步的，可以在550℃至650℃的生长环境下形成硅中间层，只要能够保证生长出符合需求的硅中间层即可，本申请实施例对生长环境的温度不做限定。
该硅中间层由周期性的凸起结构组成，其中，每个凸起结构位于两个相邻凹槽之间的间隔结构上，每两个相邻的凸起结构邻接，以保证稳定的硅基衬底结构。
示例的，请参考图11和图4，图11和图4为本申请实施例提供的硅中间层在子硅基衬底上的生长过程示意图，本申请实施例以图11和图4为例对硅中间层在子硅基衬底具有凹槽的一面上的生长过程进行说明，其中图11是图4的生长过程的中间过程。图11示出了，在生长温度为600℃时，采用分子束外延生长技术，在表面具有周期性凹槽111的子硅基衬底11上外延生长出250nm的硅中间层12，由图11可以看出，当在子硅基衬底11上生长出250nm的硅中间层12时，硅中间层12的顶部构造出了稳定的硅(111)晶面，也即是硅中间层12的顶部构造出了周期性的凸起结构101。图4示出了在生长温度为600℃时，采用分子束外延生长技术，在表面具有周期性凹槽111的子硅基衬底11上外延生长出500nm的硅中间层12(也即是在图11所示的硅中间层12的基础上又生长了250nm的硅中间层)，由图4可以看出，当在子硅基衬底11上生长出500nm的硅中间层12时，硅中间层12的顶部构造出的硅(111)稳定晶面呈邻接状，也即是硅中间层12的顶部构造出的周期性的凸起结构101呈邻接状，且最终形成的硅基衬底的结构中间构造出了不规则的镂空结构，该镂空结构由凹槽111以及每两个凸起结构101之间的间隙M组成，该镂空结构能够有效抑制热胀冷缩所导致的位错，进一步提高了最终形成的三五族材料层的质量。
在步骤820中，在硅基衬底具有凸起结构的一面上形成三五族材料层。
示例的，可以采用分子束外延生长技术，在硅基衬底具有凸起结构的一面上形成三五族材料层，其中，三五族材料缓冲层用于缓冲硅基衬底的晶格失配，三五族位错过滤层用于过滤硅基衬底的位错。当采用分子束外延生长技术，在硅基衬底具有凸起结构的一面上形成三五族材料层时，请参考图12，上述步骤820可以包括：
在步骤821中，采用分子束外延生长技术，在硅基衬底具有凸起结构的一面上形成三五族材料缓冲层。
该三五族材料缓冲层包括：AlAs晶层和GaAs晶层，GaAs晶层包括第一子GaAs晶层和第二子GaAs晶层。
示例的，可以通过三步法在硅基衬底具有凸起结构的一面上形成三五族材料缓冲层，此时，请参考图13，该形成三五族材料缓冲层的过程可以包括以下步骤：
在步骤8211中，采用分子束外延生长技术，在350℃至400℃下，在硅基衬底具有凸起结构的一面上生长厚度为5nm至15nm的AlAs晶层。
在较低的温度环境下生长AlAs晶层，可以减慢在硅基衬底具有凸起结构的一面上生长AlAs晶层的速率，进一步能够使得该AlAs晶层的每个原子生长在正确的位置，从而抑制AlAs晶层生长过程中的位错，且首先在硅基衬底的凸起结构上生长AlAs晶层，可以有效的避免直接在硅基衬底的凸起结构上生长GaAs晶层所导致的位错，从而在硅基衬底上形成高质量的 三五族材料层。
在步骤8212中，采用分子束外延生长技术，在350℃至400℃下，在AlAs晶层上生长厚度为20nm至40nm的第一子GaAs晶层。
在步骤8213中，采用分子束外延生长技术，在550℃至600℃下，在GaAs晶层上生长厚度为400nm至600nm的第二子GaAs晶层。
上述步骤8212和步骤8213中，先在低温的生长环境中生长第一子GaAs晶层，可以减慢在硅基衬底具有凸起结构的一面上生长第一子GaAs晶层的速率，进一步能够使得该第一子GaAs晶层的每个原子生长在正确的位置，再在高温的生长环境中，在第一子GaAs晶层上生长高质量的第二子GaAs晶层，能够抑制反相畴所导致的位错，从而在硅基衬底上形成高质量的三五族材料层。
在步骤822中，采用分子束外延生长技术，在三五族材料缓冲层上形成三五族位错过滤层。
该三五族位错过滤层包括：叠加的m个周期的第一量子阱结构层，该一量子阱结构层可以包括依次叠加的In 0.15Ga 0.85As晶层和GaAs晶层，m为正整数。该三五族位错过滤层还可以包括：叠加在m个周期的第一量子阱结构层上的n个周期的第二量子阱结构层以及p个周期的超晶格结构，n和p为正整数。该第二量子阱结构层可以包括依次叠加的In 0.15Al 0.85As晶层和GaAs晶层，该超晶格结构可以包括依次叠加的Al 0.6Ga 0.4As晶层和GaAs晶层。
示例的，可以采用分子束外延生长技术，先在三五族材料缓冲层上形成m个周期的第一量子阱结构层，再在第一量子阱结构层形成n个周期的第二量子阱结构层，最后在第二量子阱结构层上形成p个周期的超晶格结构，以保证每一层的结构整齐。
其中，第一量子阱结构层的生长温度可以为460℃至510℃，In 0.15Ga 0.85As晶层和GaAs晶层的厚度均为10nm，第二量子阱结构层的生长温度可以为460℃至510℃，In 0.15Al 0.85As晶层和GaAs晶层的厚度均为10nm，超晶格结构的生长温度为550℃至600℃，Al 0.6Ga 0.4As晶层和GaAs晶层的厚度均为2nm。
例如，当m＝n＝p＝5时，可以采用分子束外延生长技术，在480℃下，在三五族材料缓冲层上依次叠加生长5个周期的厚度均为10nm的In 0.15Ga 0.85As晶层和GaAs晶层，以得到第一量子阱结构层，在一种可选的实现方式中，可以先在550℃至600℃下，在第一量子阱结构层上先生长厚度为150nm至250nm的GaAs隔离层，再在480℃下，在GaAs隔离层上依次叠加生长5个周期的厚度均为10nm的In 0.15Al 0.85As晶层和GaAs晶层，以得到第二量子阱结构层；在另一种可选的实现方式中，可以在480℃下，直接在第一量子阱结构层上依次叠加生长5个周期的厚度均为10nm的In 0.15Al 0.85As晶层和GaAs晶层，以得到第二量子阱结构层，最后在580℃下，在第二量子阱结构层上依次叠加生长5个周期的厚度均为2nm的Al 0.6Ga 0.4As晶层和GaAs晶层，以得到超晶格结构，进一步得到表面粗糙度约为1nm的高质量三五族材料单晶薄膜。
示例的，请参考图14，图14为本申请实施例提供的形成有三五族位错过滤层的衬底基板的表面原子力显微图，在图14中，左侧纵坐标和上部横坐标表示尺寸，该尺寸单位为微米，右侧纵坐标表示表面高度(即表面的平整度)，该表面高度单位为纳米。由图14可以看出，该衬底基板的表面粗糙度为0.8nm左右，其表面形成了高质量三五族材料单晶薄膜。
上述各个晶层外延生长过程的温度仅为示意性说明，本申请在实际实现时，还可以采用其他温度范围来进行外延生长，本申请实施例对此不做限定。
需要说明的是，本申请实施例提供的衬底基板的制造方法步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减。
综上所述，本申请实施例提供的衬底基板的制造方法，由于所形成的硅基衬底的一面不再是硅(100)晶面，而是具有周期性的凸起结构，通过该凸起结构能够实现位错的自湮灭，将晶格失配以及反相畴所导致的位错限制在硅基衬底这一层，使得三五族材料在该硅基衬底上外延生长时，能够保持整齐的晶体结构。因此，减少了硅基衬底和三五族材料之间的晶格失配和反相畴等问题，提高了三五族材料在该硅基衬底上的良品率，进而提高了硅基光电器件的寿命以及良品率。并且由于硅基衬底中的凹槽可以采用掩膜工艺和光刻工艺制成，凸起结构可以采用外延生长技术制成，因此可以兼容CMOS制造中的相关工艺，制造工艺简单，制造成本较低。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的衬底基板的制造方法的过程，可以参考前述实施例中衬底基板的结构，本申请实施例在此不再赘述。
本申请实施例提供了一种硅基衬底的制造方法，该制造方法参考前述步骤810，以及步骤811至812，本申请实施例对此不再赘述。
本申请实施例提供了一种光电器件，该光电器件包括：衬底基板以及设置在衬底基板上的至少一层光学膜层和/或至少一层电学膜层。该衬底基板为本申请实施例提供的任一衬底基板。
在本申请实施例中，光电器件指的是光器件和/或电器件。示例的，该光电器件可以为量子点激光器、探测器、放大器、调制器、CMOS电学器件或波导器件。
综上所述，本申请实施例提供的光电器件中，由于衬底基板中的硅基衬底的一面不再是硅(100)晶面，而是具有周期性的凸起结构，该凸起结构能够实现位错的自湮灭，将晶格失配以及反相畴所导致的位错限制在硅基衬底这一层，使得三五族材料在该硅基衬底上外延生长时，能够保持整齐的晶体结构。因此，减少了硅基衬底和三五族材料之间的晶格失配和反相畴等问题，提高了三五族材料在该硅基衬底上的良品率。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的光电器件中的衬底基板的结构，可以参考前述实施例中衬底基板的结构，本申请实施例在此不再赘述。
本申请中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种衬底基板，其特征在于，包括：
    硅基衬底，所述硅基衬底的一面具有周期性的凸起结构，每个所述凸起结构的侧面与底面存在倾角；
    设置在所述硅基衬底具有所述凸起结构的一面上的三五族材料层。
  2. 根据权利要求1所述的衬底基板，其特征在于，
    所述硅基衬底具有所述周期性的凸起结构的表面为硅(111)晶面。
  3. 根据权利要求2所述的衬底基板，其特征在于，
    所述硅基衬底包括：一面具有周期性的凹槽的子硅基衬底；以及设置在所述子硅基衬底具有所述凹槽的一面上的硅中间层，所述硅中间层由所述周期性的凸起结构组成；
    其中，每个所述凸起结构位于两个相邻凹槽之间的间隔结构上，每两个相邻的所述凸起结构的侧面邻接。
  4. 根据权利要求3所述的衬底基板，其特征在于，
    所述子硅基衬底具有所述周期性的凹槽的表面为硅(110)晶面。
  5. 根据权利要求1至4任一所述的衬底基板，其特征在于，所述三五族材料层包括在所述硅基衬底具有所述凸起结构的一面上依次叠加设置的三五族材料缓冲层和三五族位错过滤层，所述三五族材料缓冲层用于缓冲所述硅基衬底的晶格失配，所述三五族位错过滤层用于过滤所述硅基衬底的位错。
  6. 根据权利要求5所述的衬底基板，其特征在于，
    所述三五族材料缓冲层包括：
    依次叠加设置在所述硅基衬底具有所述凸起结构的一面上的AlAs晶层和GaAs晶层。
  7. 根据权利要求5所述的衬底基板，其特征在于，
    所述三五族位错过滤层包括：叠加设置的m个周期的第一量子阱结构层，每个周期的所述第一量子阱结构层包括依次叠加的In 0.15Ga 0.85As晶层和GaAs晶层，m为正整数。
  8. 根据权利要求7所述的衬底基板，其特征在于，所述三五族位错过滤层还包括：叠加在所述m个周期的第一量子阱结构层上的n个周期的第二量子阱结构层以及p个周期的超晶格结构，所述n个周期的第二量子阱结构层叠加设置，所述p个周期的超晶格结构叠加设置，n和p为正整数；
    每个周期的所述第二量子阱结构层包括依次叠加的In 0.15Al 0.85As晶层和GaAs晶层；
    每个周期的所述超晶格结构包括依次叠加的Al 0.6Ga 0.4As晶层和GaAs晶层。
  9. 根据权利要求8所述的衬底基板，其特征在于，m＝n＝p＝5。
  10. 一种硅基衬底，其特征在于，包括：
    一面具有周期性的凹槽的子硅基衬底；以及设置在所述凹槽上的硅中间层，所述硅中间层由所述周期性的凸起结构组成；
    其中，每个所述凸起结构位于两个相邻凹槽之间的间隔结构上，每两个相邻的所述凸起结构的侧面邻接；
    所述硅基衬底具有所述周期性的凸起结构的表面为硅(111)晶面。
  11. 根据权利要求10所述的硅基衬底，其特征在于，
    所述子硅基衬底具有所述周期性的凹槽的表面为硅(110)晶面。
  12. 一种衬底基板的制造方法，其特征在于，包括：
    制造硅基衬底，所述硅基衬底的一面具有周期性的凸起结构，每个所述凸起结构的侧面与底面存在倾角；
    在所述硅基衬底具有所述凸起结构的一面上形成三五族材料层。
  13. 根据权利要求12所述的方法，其特征在于，
    所述硅基衬底具有所述周期性的凸起结构的表面为硅(111)晶面。
  14. 根据权利要求13所述的方法，其特征在于，
    所述制造硅基衬底，包括：
    制造一面具有周期性的凹槽的子硅基衬底；
    在所述子硅基衬底具有所述凹槽的一面上形成硅中间层，所述硅中间层由所述周期性的凸起结构组成，且每个所述凸起结构位于两个相邻凹槽之间的间隔结构上，每两个相邻的所述凸起结构邻接。
  15. 根据权利要求14所述的方法，其特征在于，
    所述子硅基衬底具有所述周期性的凹槽的表面为硅(110)晶面，
    所述制造一面具有周期性的凹槽的子硅基衬底，包括：
    提供一硅片，所述硅片的表面为硅(100)晶面；
    采用深紫外光刻工艺对所述硅片进行刻蚀，得到所述子硅基衬底。
  16. 根据权利要求14所述的方法，其特征在于，
    所述在所述子硅基衬底具有所述凹槽的一面上形成硅中间层，包括：
    采用分子束外延生长技术，在所述子硅基衬底具有所述凹槽的一面上形成硅中间层。
  17. 根据权利要求12至16任一所述的方法，其特征在于，所述在所述硅基衬底具有所述凸起结构的一面上形成三五族材料层，包括：采用分子束外延生长技术，在所述硅基衬底具有所述凸起结构的一面上形成三五族材料层。
  18. 根据权利要求17所述的方法，其特征在于，
    所述采用分子束外延生长技术，在所述硅基衬底具有所述凸起结构的一面上形成三五族材料层，包括：
    采用分子束外延生长技术，在所述硅基衬底具有所述凸起结构的一面上形成三五族材料缓冲层；
    采用分子束外延生长技术，在所述三五族材料缓冲层上形成三五族位错过滤层；
    其中，所述三五族材料缓冲层用于缓冲所述硅基衬底的晶格失配，所述三五族位错过滤层用于过滤所述硅基衬底的位错。
  19. 根据权利要求18所述的方法，其特征在于，
    所述三五族材料缓冲层包括：AlAs晶层和GaAs晶层，所述GaAs晶层包括第一子GaAs晶层和第二子GaAs晶层；
    所述采用分子束外延生长技术，在所述硅基衬底具有所述凸起结构的一面上形成三五族材料缓冲层，包括：
    采用分子束外延生长技术，在350℃至400℃下，在所述硅基衬底具有所述凸起结构的一面上生长厚度为5nm至15nm的AlAs晶层；
    采用分子束外延生长技术，在350℃至400℃下，在所述AlAs晶层上生长厚度为20nm至40nm的所述第一子GaAs晶层；
    采用分子束外延生长技术，在550℃至600℃下，在所述第一子GaAs晶层上生长厚度为400nm至600nm的所述第二子GaAs晶层。
  20. 根据权利要求18所述的方法，其特征在于，
    所述三五族位错过滤层包括：叠加设置的m个周期的第一量子阱结构层，所述第一量子阱结构层包括依次叠加的In 0.15Ga 0.85As晶层和GaAs晶层，m为正整数。
  21. 根据权利要求20所述的方法，其特征在于，所述三五族位错过滤层还包括：叠加在所述m个周期的第一量子阱结构层上的n个周期的第二量子阱结构层以及p个周期的超晶格结构，所述n个周期的第二量子阱结构层叠加设置，所述p个周期的超晶格结构叠加设置，n和p为正整数；
    每个周期的所述第二量子阱结构层包括依次叠加的In 0.15Al 0.85As晶层和GaAs晶层；
    每个周期的所述超晶格结构包括依次叠加的Al 0.6Ga 0.4As晶层和GaAs晶层。
  22. 根据权利要求20所述的方法，其特征在于，m＝n＝p＝5；
    所述第一量子阱结构层的生长温度为460℃至510℃，In 0.15Ga 0.85As晶层和GaAs晶层的厚度均为10nm；所述第二量子阱结构层的生长温度为460℃至510℃，In 0.15Al 0.85As晶层和GaAs晶层的厚度均为10nm；所述超晶格结构的生长温度为550℃至600℃，Al 0.6Ga 0.4As晶层和GaAs晶层的厚度均为2nm。
  23. 一种光电器件，其特征在于，包括：权利要求1至9任一所述的衬底基板，以及设置在所述衬底基板上的至少一层光学膜层和/或至少一层电学膜层。
  24. 根据权利要求23所述的光电器件，其特征在于，所述光电器件为量子点激光器、探测器、放大器、调制器、互补金属氧化物半导体CMOS电学器件或波导器件。
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