WO2016127675A1 - 光电子器件及其制作方法 - Google Patents

光电子器件及其制作方法 Download PDF

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WO2016127675A1
WO2016127675A1 PCT/CN2015/094197 CN2015094197W WO2016127675A1 WO 2016127675 A1 WO2016127675 A1 WO 2016127675A1 CN 2015094197 W CN2015094197 W CN 2015094197W WO 2016127675 A1 WO2016127675 A1 WO 2016127675A1
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optoelectronic device
dielectric structure
base substrate
dielectric
layer
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PCT/CN2015/094197
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English (en)
French (fr)
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张瑞英
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中国科学院苏州纳米技术与纳米仿生研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

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  • the invention relates to an optoelectronic device and a manufacturing method thereof, and belongs to the technical field of semiconductor manufacturing.
  • Si-based optoelectronic technology Based on the maturity of Si materials in the field of microelectronics, Si-based optoelectronic technology has been valued. And based on SOI technology, Si-based passive photonic devices have achieved unprecedented development, but because Si is an indirect band-stop semiconductor, it is difficult to implement active photonic devices, which directly hinders the development of Si-based optoelectronic devices. Although Si-based lasers are implemented based on Raman excitation, their conversion efficiency is too low. The integration of III-V materials on Si substrates is the best solution to reduce the cost of III-V devices and realize the integration of active passive optoelectronic devices. However, large lattice mismatch and thermal mismatch between the Si substrate and the III-V material are obstacles to accomplishing the above scheme.
  • the strain buffer layer technology is to gradually grow a strain-increasing material on the original base substrate, so that the misfit dislocation is gradually released until the heterogeneous material to be grown.
  • the material grown by this method not only has a limited reduction in dislocation density, but also has a buffer layer growth of several micrometers and a high cost.
  • the lateral epitaxial technique belongs to the secondary epitaxial technology.
  • a thin layer of lattice mismatched seed layer is epitaxially grown on the base substrate, and then a dielectric film layer (thickness of several tens of nanometers) is deposited on the seed layer;
  • the engraving and etching technique forms a strip window having a specific duty cycle on the order of micrometers on the mask, exposing the seed layer material, and finally continuing the extension of the corresponding mismatch material.
  • the method firstly epitaxially mismatches the material on the seed layer by selectively epitaxially in the window region.
  • the mismatch material After the epitaxial material exposes the window region, the mismatch material begins to realize three-dimensional growth, wherein the lateral growth causes the epitaxial layers to eventually merge to form a thin film structure.
  • the lateral epitaxy continues to propagate and slip upward through the bottom of the dielectric mask to block the threading dislocations, and the window region after the lateral growth begins The threading dislocation turns or closes into a loop to achieve dislocation quenching, thereby reducing the dislocation density.
  • this kind of epitaxial method is restricted by the respective crystal orientation speeds of epitaxial growth of large mismatched materials, and is not suitable for III-V semiconductor materials of sphalerite structure. In addition, this method cannot completely eliminate misfit dislocations.
  • the current high aspect ratio dislocation capture technique is similar to the lateral epitaxial technique.
  • a high aspect ratio dielectric mask structure is prepared on a base substrate (the aspect ratio of the dielectric mask structure is at least greater than 1), and the height and width are widened. Exposing the base substrate to the dielectric mask structure, and then epitaxially growing the dislocation suppression layer and the dislocation-free layer on the exposed base substrate until the epitaxial layer is higher than the dielectric mask structure; and then based on the three-dimensional The polymeric layer is grown until adjacent growth faces are interconnected to merge.
  • the threading dislocations generated by the large mismatch epitaxy are generally 60-degree dislocations, so the sidewalls of the dielectric mask structure can completely suppress the dislocation climbing in the medium.
  • a dislocation-free layer can be obtained in the mask structure, but after the dielectric mask, the material continues to grow in three dimensions, and the semiconductor material grown on the dielectric film during the lateral growth polymerization inevitably introduces dislocations, twinning, stacking, etc.
  • the defect makes it difficult to obtain a semiconductor film having a low defect density even after polishing, and after the material is polymerized, the surface is not flat, and further polishing is required to continue the preparation of the optoelectronic device. This brings certain difficulties and hidden dangers to high quality material growth and device preparation.
  • the present invention provides the following technical solutions:
  • Embodiments of the present invention disclose an optoelectronic device including a base substrate, a dielectric structure having a high aspect ratio formed on the base substrate, and a large mismatch semiconductor material system grown in the dielectric structure,
  • the large mismatched semiconductor material system comprises a large misfit dislocation suppression layer, a dislocation-free buffer layer, a core layer and a cladding layer, the layers of the large mismatched semiconductor material system constituting the optoelectronic device material body, from the dielectric structure
  • the base substrate is sequentially grown upward, but does not expose the dielectric structure, and the optoelectronic device further includes a semiconductor contact layer formed on the cladding layer and front and back electrodes.
  • the material of the base substrate is selected from the group consisting of Si, Ge, GaAs, GaN, and sapphire.
  • the material system composed of the base substrate and the large mismatched semiconductor material system comprises Si/GaAs, Si/InP, Si/GaN, Si/AlN, Si/BN, Si/Ge. , Si/InN, Si/SiC, Ge/GaAs, Ge/InP, sapphire/GaN, sapphire/AlN, sapphire/BN, sapphire/InN, sapphire/SiC, Si/ZnO, sapphire/ZnO, GaAs/InP.
  • the dielectric structure trench depth is less than 5 ⁇ m, and the dielectric structure window width is less than 2 ⁇ m.
  • the dielectric structure is a one-dimensional grid structure or a two-dimensional network structure, and the surface of the base substrate is exposed in the window structure of the dielectric structure.
  • the dielectric structural material comprises SiO 2 , SiNO, SiN, TiO 2 and Al 2 O 3 .
  • the dielectric structure forming method comprises dielectric film deposition, electron beam exposure of the structure pattern, nanoimprinting, nanosphere lithography, holographic interference lithography, projection lithography, general lithography.
  • the anodization is obtained and the dielectric structure is obtained by the above-described mask etching.
  • the large misfit dislocation suppression layer, the dislocation-free buffer layer, the core layer and the cladding layer are grown by MOCVD, MBE, HVPE, LPE, or CVD methods.
  • the front and back electrodes are prepared by evaporation or sputtering.
  • an embodiment of the present invention further discloses a method for fabricating an optoelectronic device, wherein a nano-scale resolution pattern is formed on a surface of a dielectric film on a base substrate by using a miniature projection exposure, and then the pattern is transferred to the dielectric film.
  • a dielectric structure having a high aspect ratio is formed, and a dislocation suppression layer, a dislocation-free buffer layer, an optoelectronic device core layer, a cladding layer, and an electrode contact layer are sequentially grown in the trenches of the dielectric structure.
  • the function is strong, the structure of the medium and the structure of the grown semiconductor material constitute a periodic refractive index change structure, and the coupling between each unit can realize a specific function by itself.
  • FIG. 1a to 1h are schematic flowcharts showing the fabrication of an optoelectronic device in the first embodiment of the present invention
  • FIGS. 2a and 2b are schematic views showing the flow of fabricating an optoelectronic device in a second embodiment of the present invention
  • 3a and 3b are schematic views showing the flow of fabricating an optoelectronic device in a third embodiment of the present invention.
  • the invention provides a method for preparing an optoelectronic device on a large mismatched heterogeneous substrate, firstly preparing a high aspect ratio dielectric structure on a base substrate, and then sequentially growing the optoelectronic device by using a high aspect ratio dislocation capture technique in the dielectric structure.
  • the large mismatched heterogeneous material is required. After the material is grown, the corresponding electrodes are prepared on the front side and the back side respectively to form the desired optoelectronic device.
  • the manufacturing method of the optoelectronic device includes:
  • (1) as shown in Figure 1a, provides a basic substrate 10 for heteroepitaxial, the material of the base substrate 10 is Si, Ge, GaAs, GaN, or sapphire, preferably Si;
  • a dielectric film 20 is formed on the base substrate 10 for heteroepitaxial growth.
  • the material of the dielectric film 20 is SiNO, SiN, SiO 2 , Al 2 O 3 or TiO 2 , preferably SiO 2 . .
  • a mask pattern 30 required for the dielectric structure is obtained on the formed dielectric film 20.
  • the dielectric film 20 is etched using the mask pattern 30 as a mask.
  • the etching method includes dry etching and wet etching, and a mixture of the two.
  • the obtained dielectric structure 40 is a one-dimensional grid structure or a two-dimensional network structure, that is, a strip groove structure Or a lattice trench, each trench having an aspect ratio greater than 1, and each trench having a depth of less than 5 ⁇ m, each trench having a width of less than 2 ⁇ m.
  • a dislocation suppression layer 51 and a dislocation-free buffer layer 52 of a large mismatched semiconductor material are sequentially grown in the trenches of the dielectric structure 40.
  • the optoelectronic device core layer 53, the cladding layer 54, and the electrode contact layer 55 are sequentially grown in the trenches of the dielectric structure 40.
  • the material system composed of the base substrate and the large mismatched semiconductor material system includes Si/GaAs, Si/InP, Si/GaN, Si/AlN, Si/InN, Si/CSi, Si/BN, Si/ZnO, Ge. /GaAs, Ge/InP, sapphire/GaN, sapphire/AlN, sapphire/BN, sapphire/InN, sapphire/CSi, sapphire/ZnO, GaAs/InP.
  • the front surface electrode 60 and the back surface electrode 70 are formed on the upper and lower sides of the above device, respectively.
  • the front and back electrodes are prepared by evaporation or sputtering.
  • the large misfit dislocation suppression layer, the dislocation-free buffer layer, the core layer and the cladding layer and the electrode contact layer grown thereon in the dielectric structure all have a large lattice mismatch with the base substrate, but they are The mismatch is small, and it belongs to coherent growth in the traditional film growth, and the system of the above layers is determined according to the requirements of the device.
  • the specific materials of each layer are determined according to the specific requirements of the device, but they must belong to a material system.
  • the large misfit dislocation suppression layer is InP or other materials that are lattice-matched with InP
  • the dislocation-free buffer layer is InP or other materials that match the lattice of InP, photoelectrons.
  • the device core layer is InGaAsP (InGaAlAs, InGaNAs) material
  • the cladding layer is InP material or other material lattice-matched with InP
  • the electrode contact layer is InGaAs or other material satisfying the electrode contact lattice matching with InP
  • the front electrode is based on
  • the contact layer has a Ti/Pb/Au or Au/Ge/Ni structure
  • the back electrode is in contact with Si and is made of Al, Ag or the like.
  • the electrode contact layer is formed in the trench of the dielectric structure and protrudes From the upper surface of the dielectric structure, the fabricated optoelectronic device is shown in Figure 2b.
  • an electrode contact layer is formed over the dielectric structure and in contact with the cladding within the dielectric structure.
  • the fabricated optoelectronic device is shown in Figure 3b.
  • the optoelectronic device described above may also be other optoelectronic devices such as LEDs, solar cells, detectors, lasers, modulators, and the like.

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Abstract

一种光电子器件，包括基础衬底（10），形成于基础衬底上的具有高深宽比的介质结构（40）、高深宽比介质结构内的大失配异质半导体材料以及覆盖于正面和背面的电极（60、70），其中，光电子器件的大失配异质半导体材料至少包括无应变缓冲层（52）、芯层（53）和包覆层（54）均位于介质结构的沟槽内，且半导体材料不突出于介质结构的顶面。此外，该器件结构还包括位于介质沟槽内或者沟槽上的电极接触层（55）以及正面和背面电极。可以完全将失配材料和基础衬底之间的失配位错被介质结构捕获，且光电子器件的半导体材料生长在介质结构内，晶体质量高。

Description

光电子器件及其制作方法 技术领域
本发明涉及一种光电子器件及其制作方法，属于半导体制造技术领域。
背景技术
基于Si材料在微电子技术领域的成熟程度，Si基光电子技术一度受到人们重视。且基于SOI技术，Si基无源光子器件获得了空前发展，但是由于Si是间接禁带半导体，难以实现有源光子器件，从而直接阻碍了Si基光电子器件的发展。尽管基于拉曼受激实现了Si基激光器，但是其转换效率太低。Si衬底上集成III-V材料成为降低III-V器件成本、实现有源无源光电子器件集成的最佳方案。但是Si衬底和III-V材料之间大的晶格失配和热失配成为其完成上述方案的障碍。
目前公认的解决方案有两类，一类是在需要有源器件的部位采用晶片键合方式实现Si基III-V族光电子器件，另一类是在Si衬底上直接生长III-V半导体材料，然后制备光电子器件。但是前者需要分别在不同的衬底上制备有源无源器件，然后对准键合，不仅工序繁、成本高、速度慢，成品率低，而且键合工艺要受到所作有源无源器件上各种材料和结构的制约，局限性大。Si衬底上直接生长III-V半导体材料的方法包括两种：(1)应变缓冲层技术(2)横向外延技术(3)高深宽比位错捕获技术。
其中，应变缓冲层技术是在原有基础衬底上逐步生长应变增加的材料，使得失配位错逐渐释放，直到要生长的异质材料。采用该种方法生长的材料，不仅位错密度降低有限，且缓冲层生长高达数个微米，成本高。
横向外延技术属于二次外延技术，首先在基础衬底上外延生长一薄层晶格失配的种子层，然后再在种子层上沉积介质膜层(厚度为几十个纳米)；然后采用光刻和腐蚀技术在掩模上形成具有微米量级特定占空比的条形窗口，露出种子层材料，最后继续进行相应失配材料外延。该方法首先在窗口区内通过选择外延在种子层上外延失配材料，当外延材料暴露出窗口区后，失配材料开始实现三维生长，其中，横向生长使得外延层最终合并，形成薄膜结构。横向外延通过介质掩模底部阻挡穿透位错向上继续传播和滑移，横向生长开始后窗口区 的穿透位错转向或闭合成环实现位错湮灭，从而降低位错密度。但是该种外延方法受到大失配材料外延生长各个晶向速度的制约，不适合闪锌矿结构的III-V族半导体材料。此外，该方法也不能彻底消除失配位错。
目前的高深宽比位错捕获技术与横向外延技术比较类似，首先在基础衬底上制备高深宽比介质掩模结构(其介质掩模结构的深宽比至少大于1)，并且将该高深宽比的介质掩模结构内暴露出基础衬底，然后在该暴露出的基础衬底上外延生长位错抑制层、无位错层直到外延层高于介质掩模结构；然后在此基础上三维生长聚合层，直到相邻生长面相互连接从而合并。由于绝大多数半导体材料都是立方晶系材料，大失配外延产生的穿透位错一般都是60度位错，因此通过介质掩模结构的侧壁可以完全抑制位错攀移，在介质掩模结构内能获得无位错层，但是高出介质掩模之后，材料继续三维生长，横向生长聚合过程中在介质膜上生长的半导体材料不可避免地引入位错、孪晶、层错等缺陷，使得即使后期抛光也难以获得低缺陷密度的半导体薄膜，而且材料经聚合后，表面不平整，必须经过进一步抛光，才能继续制备光电子器件。这给高质量材料生长和器件制备都带来一定的难度和隐患。
因此，到目前为止，国际上在大失配衬底上制备光电子器件还没有彻底突破，特别是Si基光电子有源器件远没有达到实用化要求。
发明内容
本发明的目的在于提供一种光电子器件及其制作方法，以克服现有技术中的不足。
为实现上述目的，本发明提供如下技术方案：
本发明实施例公开了一种光电子器件，包括基础衬底、形成于所述基础衬底上的具有高深宽比的介质结构、以及生长于介质结构内的大失配半导体材料体系，所述的大失配半导体材料体系包括大失配位错抑制层、无位错缓冲层、芯层和包覆层，所述的大失配半导体材料体系的各层构成光电子器件材料主体，从介质结构内的基础衬底依次向上生长，但不露出介质结构，所述光电子器件还包括形成于所述包覆层之上的半导体接触层以及正面和背面电极。
优选的，在上述的光电子器件中，所述基础衬底的材质选自Si、Ge、GaAs、GaN、蓝宝石。
优选的，在上述的光电子器件中，所述基础衬底与大失配半导体材料体系构成的材料体系包括Si/GaAs、Si/InP、Si/GaN、Si/AlN、Si/BN、Si/Ge、Si/InN、Si/SiC、Ge/GaAs、 Ge/InP、蓝宝石/GaN、蓝宝石/AlN、蓝宝石/BN、蓝宝石/InN、蓝宝石/SiC、Si/ZnO、蓝宝石/ZnO、GaAs/InP。
优选的，在上述的光电子器件中，所述介质结构沟槽深度小于5μm，所述介质结构窗口宽度小于2μm。
优选的，在上述的光电子器件中，所述介质结构为一维栅状结构或者二维网状结构，所述介质结构的窗口结构内暴露出基础衬底表面。
优选的，在上述的光电子器件中，所述介质结构材料包括SiO2、SiNO、SiN、TiO2和Al2O3。
优选的，在上述的光电子器件中，所述介质结构形成方法包括介质膜沉积、结构图案采用电子束曝光、纳米压印、纳球光刻、全息干涉光刻、投影式光刻、普通光刻、阳极氧化获得以及介质结构通过上述掩膜腐蚀获得。
优选的，在上述的光电子器件中，所述大失配位错抑制层、无位错缓冲层、芯层和包覆层采用MOCVD、MBE、HVPE、LPE、或CVD方法生长。
优选的，在上述的光电子器件中，所述正面和背面电极采用蒸发或者溅射的方法制备。
相应地，本发明实施例还公开了一种光电子器件的制作方法，采用微缩投影式曝光在位于基础衬底上的介质膜表面形成纳米级分辨率图案，然后将该图案转移到介质膜上，形成具有高深宽比的介质结构，在所述介质结构的沟槽内依次生长位错抑制层、无位错缓冲层、光电子器件芯层、包覆层和电极接触层。
与现有技术相比，本发明的优点在于：
(1)工艺简单，成本低。无需分别外延III-V族材料、制备相应有源器件、然后与Si芯片键合；
(2)大失配材料晶体质量高。无论是采用应变缓冲层技术、横向外延技术还是现有的高深宽比位错捕获技术，均不可避免地在大失配半导体内形成位错，且往往位错密度超过106，成为光电子器件实现的障碍。而该方案可以将大失配半导体材料和基础衬底之间的失配位错捕获在介质结构的侧壁，且完全利用介质结构内的无位错层制备光电子器件，晶体质量高。
(3)泄漏损耗小。无论是III-V衬底，还是Si衬底，由于同一材料体系的材料折射率都非常接近，以至于单一衬底上形成的光电子器件不可避免地存在一定程度的泄漏损 耗，背反射小，使得光场难以有效重复利用。对本发明形成的光电子器件而言，由于基础衬底和大失配半导体材料的色散关系不一致，因此在基础衬底上制备大失配半导体材料光电子器件，其泄漏损耗势必低于同质衬底上制备的光电子器件，光的利用率提高。
(4)功能性强，介质结构和生长的半导体材料结构构成周期性折射率变化结构，每个单元相互之间的耦合，本身可实现特定功能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a～图1h所示为本发明第一实施例中制作光电子器件的流程示意图；
图2a和图2b所示为本发明第二实施例中制作光电子器件的流程示意图；
图3a和图3b所示为本发明第三实施例中制作光电子器件的流程示意图。
具体实施方式
本发明提供了一种大失配异质衬底上光电子器件制备方法，首先在基础衬底上制备高深宽比介质结构，然后在该介质结构内利用高深宽比位错捕获技术依次生长光电子器件需要的大失配异质材料，材料生长完成后，在正面和背面分别制备相应电极，形成需要的光电子器件。
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
光电子器件的制作方法包括：
(1)、参图1a所示，提供一异质外延用基础衬底10，该基础衬底10的材料为Si、Ge、GaAs、GaN、或蓝宝石，优选为Si；
(2)、参图1b所示，在异质外延用基础衬底10上形成介质膜20，介质膜20的材质为SiNO、SiN、SiO2、Al2O3或TiO2，优选为SiO2。
(3)、参图1c所示，利用电子束曝光、纳米压印、纳球光刻、全息干涉光刻、投影式光刻、普通紫外光刻、阳极氧化、X-ray光刻等工艺，在形成的介质膜20上获得介质结构需要的的掩膜图案30。
(4)、参图1d所示，以上述掩膜图案30为掩膜刻蚀介质膜20。刻蚀方法包括干法刻蚀和湿法腐蚀以及二者的混用。
(5)、参图1e所示，去除掩膜，获得具有高深宽比的介质结构40，其中所获得介质结构40为一维栅状结构或者二维网状结构，即为条形沟槽结构或者格型沟槽，每个沟槽的深宽比大于1，且每个沟槽的深度小于5μm，每个沟槽的宽度小于2μm。
(6)、参图1f所示，在介质结构40的沟槽内依次生长大失配半导体材料的位错抑制层51和无位错缓冲层52。
(7)、参图1g所示，在介质结构40的沟槽内继续依次生长光电子器件芯层53、包覆层54和电极接触层55。
所述基础衬底与大失配半导体材料体系构成的材料体系包括Si/GaAs、Si/InP、Si/GaN、Si/AlN、Si/InN、Si/CSi、Si/BN、Si/ZnO、Ge/GaAs、Ge/InP、蓝宝石/GaN、蓝宝石/AlN、蓝宝石/BN、蓝宝石/InN、蓝宝石/CSi、蓝宝石/ZnO、GaAs/InP。
(8)、参图1h所示，在上述器件的上下两侧分别制作正面电极60和背面电极70。正面和背面电极采用蒸发或者溅射的方法制备。
生长于介质结构内的大失配位错抑制层、无位错缓冲层、芯层和包覆层以及其上的电极接触层均为与基础衬底有着大的晶格失配，但它们之间失配较小，在传统薄膜生长中属于共格生长，且上述各层材料所属体系根据器件需求来定，各层具体材料根据器件具体指标需求来定，但一定属于一个材料体系。如光纤通信器件，选择Si基InP系材料，则大失配位错抑制层为InP或与InP晶格匹配的其他材料,无位错缓冲层为InP或与InP晶格匹配的其他材料，光电子器件芯层为InGaAsP(InGaAlAs、InGaNAs)材料、包覆层为InP材料或与InP晶格匹配的其他材料、电极接触层为InGaAs或与InP晶格匹配的满足电极接触的其他材料、正面电极根据接触层极性为Ti/Pb/Au或者Au/Ge/Ni结构，背面电极与Si接触，为Al、Ag等材料。
在本发明第二实施例中，参图2a所示，电极接触层形成于介质结构的沟槽内并凸伸 出介质结构的上表面，所制作的光电子器件如图2b所示。
在本发明第三实施例中，参图3a所示，电极接触层形成于介质结构上方并与介质结构内的包覆层接触，所制作的光电子器件如图3b所示。
上述的光电子器件还可以为LED、太阳能电池、探测器、激光器、调制器等其他光电子器件。
最后，还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。

Claims (9)

  1. 一种光电子器件，其特征在于，包括基础衬底、形成于所述基础衬底上的具有高深宽比的介质结构、以及生长于介质结构内的大失配半导体材料体系，所述的大失配半导体材料体系包括大失配位错抑制层、无位错缓冲层、芯层和包覆层，所述的大失配半导体材料体系的各层构成光电子器件材料主体，从介质结构内的基础衬底依次向上生长，但不露出介质结构，所述光电子器件还包括形成于所述包覆层之上的半导体接触层以及正面和背面电极。
  2. 根据权利要求1所述的光电子器件，其特征在于：所述基础衬底的材质选自Si、Ge、GaAs、GaN、蓝宝石。
  3. 根据权利要求1所述的光电子器件，其特征在于：所述基础衬底与大失配半导体材料体系构成的材料体系包括Si/GaAs、Si/InP、Si/GaN、Si/AlN、Si/InN、Si/Ge、Si/BN、Si/CSi、Ge/GaAs、Ge/InP、蓝宝石/GaN、蓝宝石/AlN、蓝宝石/BN、蓝宝石/InN、蓝宝石/SiC、蓝宝石/ZnO、GaAs/InP中的至少一种。
  4. 根据权利要求1所述的光电子器件，其特征在于：所述介质结构沟槽深度小于5μm，所述介质结构的窗口宽度小于2μm。
  5. 根据权利要求1所述的光电子器件，其特征在于：所述介质结构为一维栅状结构或者二维网状结构，所述介质结构的窗口结构内暴露出基础衬底表面。
  6. 根据权利要求1所述的光电子器件，其特征在于：所述介质结构材料包括SiO2、SiNO、SiN、TiO2和Al2O3中的至少一种。
  7. 根据权利要求1所述的光电子器件，其特征在于：所述介质结构形成方法包括首先在基础衬底上获得介质膜，然后采用电子束曝光、纳米压印、纳球光刻、全息干涉光刻、投影式光刻、普通光刻、阳极氧化方法中的至少一种形成介质结构图案，最后腐蚀掉部分介质材料，形成介质结构，且在介质结构内暴露出基础衬底表面。
  8. 根据权利要求1所述的光电子器件，其特征在于：所述大失配位错抑制层、无位错缓冲层、芯层、包覆层以及电极接触层采用MOCVD、MBE、HVPE，LPE或CVD方法生长。
  9. 根据权利要求1所述的光电子器件，其特征在于：所述正面和背面电极采用蒸发或者溅射的方法制备。
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