WO2017156803A1 - 一种石墨烯薄膜晶体管的制备方法 - Google Patents

一种石墨烯薄膜晶体管的制备方法 Download PDF

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WO2017156803A1
WO2017156803A1 PCT/CN2016/078391 CN2016078391W WO2017156803A1 WO 2017156803 A1 WO2017156803 A1 WO 2017156803A1 CN 2016078391 W CN2016078391 W CN 2016078391W WO 2017156803 A1 WO2017156803 A1 WO 2017156803A1
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graphene
layer
thin film
film transistor
metal layer
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French (fr)
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王选芸
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to GB1815315.5A priority Critical patent/GB2563365B/en
Priority to JP2018547909A priority patent/JP6719581B2/ja
Priority to EA201800470A priority patent/EA036020B1/ru
Priority to US15/126,584 priority patent/US10128453B2/en
Priority to KR1020187026125A priority patent/KR102173432B1/ko
Publication of WO2017156803A1 publication Critical patent/WO2017156803A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/881—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being a two-dimensional material
    • H10D62/882—Graphene
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H01B1/20—Conductive material dispersed in non-conductive organic material
    • H01B1/24—Conductive material dispersed in non-conductive organic material the conductive material comprising carbon-silicon compounds, carbon or silicon
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/8303—Diamond
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    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2923—Materials being conductive materials, e.g. metallic silicides
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3406—Carbon, e.g. diamond-like carbon
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials

Definitions

  • the present invention relates to the field of thin films, and in particular to a method for preparing a graphene thin film transistor.
  • Graphene is a new type of material with good electrical conductivity and light transmission properties. With the development of touch screen, liquid crystal display and other technologies, and the excellent mechanical strength and flexibility of graphene, it is made on thin film transistors. The application has gradually become a hot topic of research.
  • the method steps for fabricating a graphene thin film transistor mainly include: forming graphene on the surface of the copper foil; coating the surface of the graphene with an organic polymer material, such as polymethyl methacrylate (English name: Polymeric Methyl Methacrylate (PMMA); a film composed of PMMA, graphene and copper foil is placed in a copper etching solution to etch away the copper foil; then PMMA is dissolved, and a source and a drain are formed on the surface of the graphene by photolithography or the like. Thereby forming a complete graphene thin film transistor.
  • an organic polymer material such as polymethyl methacrylate (English name: Polymeric Methyl Methacrylate (PMMA)
  • PMMA Polymeric Methyl Methacrylate
  • Embodiments of the present invention provide a method for preparing a graphene thin film transistor to solve the problem of increased contact resistance caused by residual organic polymer material on the surface of graphene in the prior art preparation method.
  • Embodiments of the present invention provide a method for fabricating a graphene thin film transistor, including:
  • the method further comprises: washing the copper foil in ethanol, acetone, 0.5 mol/L of dilute hydrochloric acid.
  • the metal layer is deposited on the surface of the graphene by electron beam evaporation or magnetron sputtering.
  • the metal layer has a thickness of 5 nm to 50 nm.
  • the metal layer comprises a single metal layer or a composite metal layer.
  • each metal layer has the same thickness.
  • the metal used for the metal layer includes titanium, gold, nickel, palladium or platinum.
  • the density of the support layer is smaller than the density of the copper etching solution.
  • the support layer is a polyurethane material.
  • the target substrate comprises an insulating layer
  • the material of the insulating layer comprises silicon dioxide, silicon carbide, glass or sapphire.
  • Embodiments of the present invention provide a method for preparing a graphene thin film transistor, and the preparation method includes:
  • the method further comprises: washing the copper foil in ethanol, acetone, and 0.5 mol/L of dilute hydrochloric acid.
  • graphene is deposited on the surface of a copper foil by chemical vapor deposition.
  • the metal layer is deposited on the surface of the graphene by electron beam evaporation or magnetron sputtering.
  • the thickness of the metal layer is 5 nm to 50 nm.
  • the metal layer comprises a single metal layer or a composite metal layer.
  • the metal used for the metal layer includes titanium, gold, nickel, palladium or platinum.
  • the density of the support layer is less than the density of the copper etching solution.
  • the support layer is a polyurethane material.
  • the target substrate comprises an insulating layer, wherein the material of the insulating layer comprises silicon dioxide, silicon carbide, glass or sapphire.
  • the graphene layer is protected by depositing a metal layer on the surface of the graphene layer, so that the graphene layer is not in direct contact with the support layer and the photoresist.
  • the source-drain electrode and the graphene layer can be completely contacted, and the contact resistance between the source-drain electrode and the graphene is lowered, thereby solving the existing preparation method due to the graphene layer.
  • the surface remains of PMMA and the photoresist causes a problem that the contact resistance between the source drain electrode and the graphene increases.
  • FIG. 1 is a flow chart of a preferred embodiment of a method of fabricating a graphene thin film transistor of the present invention
  • FIG. 2 is a schematic structural view of a graphene film in a method for preparing a graphene thin film transistor of the present invention
  • FIG 3 is a transfer graph of a back gate of a graphene thin film transistor prepared by the preparation method provided by the present invention.
  • FIG. 1 is a flow chart of a preferred embodiment of a method for fabricating a graphene thin film transistor of the present invention.
  • the preparation method comprises the following steps:
  • the graphene film is placed in a copper etching solution, wherein the supporting layer is partially immersed in the copper etching solution, and the metal layer, the graphene layer and the copper foil are completely immersed in the copper etching solution until the copper foil is completely dissolved. Transferring the graphene film from which the copper foil is removed to the target substrate, and removing the support layer;
  • the cleaning operation is as follows: Ethanol, acetone, and 0.5 mol/L of dilute hydrochloric acid are washed until the impurities on the surface of the copper foil are removed, so that the surface of the copper foil reaches the process requirement for growing graphene.
  • a graphene layer is deposited on the surface of the copper foil by chemical vapor deposition.
  • the graphene prepared by chemical vapor deposition has the advantages of high quality and large growth area, and is the main method for preparing high-quality graphene.
  • the principle is to introduce one or more gaseous substances into a reaction chamber to generate a chemical reaction.
  • a new material is deposited on the surface of the substrate.
  • a metal is deposited on the surface of the graphene layer by a magnetron sputtering technique to form a metal layer on the surface of the graphene layer.
  • a magnetron sputtering technique to form a metal layer on the surface of the graphene layer.
  • other techniques such as electron beam evaporation may be used to deposit the metal on the surface of the graphene layer, which is not specifically limited.
  • the metal layer is a composite metal layer comprising two metal layers, wherein a metal layer near the surface of the graphene layer is a titanium metal layer, and a metal layer away from the surface of the graphene layer is a gold metal.
  • a metal layer near the surface of the graphene layer is a titanium metal layer
  • a metal layer away from the surface of the graphene layer is a gold metal.
  • the metal layer may be a single metal layer, or a composite metal layer of three or four layers, and the metal of the metal layer may also be one of titanium, gold, nickel, palladium or platinum.
  • the number of layers of the metal layer and the kind of the metal are not specifically limited herein.
  • the thickness of the metal layer is generally 5 nm to 50 nm. In the preferred embodiment, the thickness of the metal layer is preferably 10 nm, and titanium. The thickness of the metal layer and the gold metal layer were each 5 nm.
  • a support layer is attached to the surface of the metal layer, and the density of the support layer is smaller than the density of the copper etching solution, wherein the density of the support layer is different from the density of the copper etching solution, and the purpose is to utilize
  • the difference in density between the support layer and the copper etching solution causes the supporting layer to float on the surface of the copper etching liquid, that is, in the subsequent step of dissolving the copper foil, the supporting layer can suspend the metal layer, the graphene layer and the copper foil in the copper etching solution In the middle, do not let it fall into the copper corrosion solution.
  • the support layer provides convenience for subsequently transferring the graphene film from which the copper foil is removed to the target substrate.
  • the support layer is a polyurethane material.
  • other materials having a density lower than that of the copper etching solution may be used, and are not specifically limited herein.
  • FIG. 2 is a schematic structural view of the graphene film in the method for preparing the graphene thin film transistor of the present invention.
  • the graphene film includes, in order from bottom to top, a copper foil 21, a graphene layer 22, a metal layer 23, and a support layer 24.
  • the graphene film is placed in the copper etching solution.
  • the supporting layer floats on the surface of the copper etching liquid, and the metal layer and the graphene layer and The copper foil will be immersed in the copper etching solution.
  • the graphene film from which the copper foil is removed is transferred to the target substrate, and the support layer is removed.
  • the target substrate comprises an insulating layer, and it is known from the common general knowledge that the graphene film is transferred onto the insulating layer of the target substrate.
  • the insulating layer is made of a silicon dioxide material.
  • silicon carbide, glass or sapphire materials may also be used, and are not specifically limited herein.
  • a source-drain pattern is defined on the surface of the metal layer by photolithography, and then gold metal is deposited to a corresponding position of the source-drain pattern by magnetron sputtering or electron beam evaporation, and then dry etching is performed.
  • the technique etches away the metal layer of the channel region to expose the graphene layer of the channel region; at the same time, prepares the gate electrode on the side of the target substrate away from the graphene layer, since the source, drain and gate are prepared.
  • the method steps used for the electrodes are prior art and common knowledge is well known to those skilled in the art, and thus will not be further described in the preferred embodiment.
  • a photolithography technique is used to define a source-drain pattern directly on a graphene layer surface, and then a magnetron sputtering technique or an electron beam evaporation technique in a source-drain pattern.
  • a thin layer of titanium metal and a thick layer of gold metal are deposited at corresponding locations to form a source and drain electrode.
  • the graphene layer is in direct contact with the photoresist used in photolithography to dissolve the photoresist.
  • the photoresist remains on the surface of the graphene layer, the contact between the graphene layer and the source and drain electrodes is incomplete, and the contact resistance between the graphene layer and the source and drain electrodes is increased.
  • the photo-deposition pattern is used to define the source-drain pattern on the surface of the metal layer, so that the graphene layer does not contact the photoresist, and does not appear when the photoresist is dissolved.
  • the graphene is protected by the metal layer, ensuring that the graphene layer and the source and drain electrodes are sufficiently Contact reduces the contact resistance of the graphene layer to the source and drain electrodes.
  • the minimum drain current will appear on the left or right side of 0 volts, which destroys the bipolar symmetry of the graphene field effect device, making graphene and The contact resistance between the source and the drain increases. It can also be seen from the figure that Under certain circumstances, when the drain voltage is continuously increased by 5 mv, the drain current increases by the same magnitude, that is, the drain current and the drain voltage. The positive proportional relationship indicates that the graphene thin film transistor has excellent electrical properties.
  • the graphene layer is not in contact with the support layer and the subsequently used photoresist, thereby avoiding the graphene surface.
  • the problem of residue occurs, so that the source and drain electrodes can completely contact with the graphene layer, the contact resistance between the source and drain electrodes and the graphene is reduced, and the current in the graphene thin film transistor is increased, which solves the existing preparation method.
  • the problem that the contact resistance between the source and drain electrodes and the graphene increases due to the residual PMMA and the photoresist on the surface of the graphene layer.
  • the surface of the graphene layer in the graphene thin film transistor prepared according to the preparation method provided by the preferred embodiment has a undulation of less than 0.1 nm, which is much smaller than the surface of the graphene layer in the graphene thin film transistor prepared by the existing preparation method.
  • the degree of undulation is 1 nm, and it can be seen that the graphene thin film transistor prepared by the preparation method of the preferred embodiment has better electrical properties.

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  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Thin Film Transistor (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Carbon And Carbon Compounds (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

提供一种石墨烯薄膜晶体管的制备方法，其包括：在铜箔（21）表面沉积石墨烯层（22）；在石墨烯层（22）表面沉积金属层（23）；在金属层（23）表面贴合支撑层（24），形成石墨烯膜片；将石墨烯膜片放在腐蚀溶液中，直至铜箔（21）完全溶解掉，将石墨烯膜片转移至目标衬底，去掉支撑层（24）；在金属层（23）表面上定义源漏极图形，制备源漏极电极，在目标衬底上制备栅极电极。

Description

一种石墨烯薄膜晶体管的制备方法 技术领域
本发明涉及薄膜领域，特别是涉及一种石墨烯薄膜晶体管的制备方法。
 背景技术
石墨烯，是一种具有良好的电导性能和透光性能的新型材料，随着触摸屏、液晶显示等技术的发展，以及石墨烯表现出来的优秀的机械强度和柔韧性，使得其在薄膜晶体管上的应用逐渐成为人们研究的热点。
目前制作石墨烯薄膜晶体管的方法步骤主要包括：在铜箔表面生成石墨烯；在石墨烯表面涂覆有机高分子材料，例如聚甲基丙烯酸甲酯 (英文名称：Polymeric Methyl Methacrylate，简称：PMMA)；将PMMA、石墨烯和铜箔组成的膜片放在铜腐蚀液中腐蚀掉铜箔；再将PMMA溶掉，通过光刻等技术在石墨烯表面制作源漏极，从而形成一个完整的石墨烯薄膜晶体管。然而，在现有的制备石墨烯薄膜晶体管的方法中，由于PMMA以及光刻技术所采用的光刻胶均与石墨烯直接接触，在溶掉PMMA和光刻胶的时候，就会出现PMMA和光刻胶残留在石墨烯表面的问题，在后续制作源漏极的时候，由于残留的PMMA和光刻胶的存在，使得源漏极与石墨烯表面的接触不够完全，从而增加了源漏极与石墨烯的接触电阻，限制了电荷的传输，使得薄膜晶体管中的电流减小，导致驱动能力降低。
因此，有必要提供一种石墨烯薄膜晶体管的制备方法，以解决现有制备方法中因石墨烯表面残留有机高分子材料而导致的接触电阻增加的问题。
 技术问题
本发明实施例提供一种石墨烯薄膜晶体管的制备方法，以解决现有制备方法中因石墨烯表面残留有机高分子材料而导致的接触电阻增加的问题。
 技术解决方案
本发明实施例提供一种石墨烯薄膜晶体管的制备方法，其包括：
S1、以甲烷作为碳源，采用化学气相沉积法，在铜箔表面沉积石墨烯层；
S2、在所述石墨烯层表面沉积金属层；
S3、在所述金属层表面贴合支撑层，从而形成石墨烯膜片；
S4、将所述石墨烯膜片放置在铜腐蚀液中，其中所述支撑层部分沉浸在铜腐蚀液中，而所述金属层、石墨烯层和铜箔完全沉浸在铜腐蚀液中，直至所述铜箔完全溶解掉，再将去掉铜箔的石墨烯膜片转移至目标衬底，去掉所述支撑层；
S5、在所述金属层表面上定义源漏极图形，制备源漏极电极，并在目标衬底上远离石墨烯层的一侧制备栅极电极，从而获得石墨烯薄膜晶体管。
在本发明的石墨烯薄膜晶体管的制备方法中，其中在S1之前，还包括：将所述铜箔依次在乙醇、丙酮、0.5mol/L的稀盐酸中进行清洗。
在本发明的石墨烯薄膜晶体管的制备方法中，其中所述金属层采用电子束蒸发或者磁控溅射技术沉积在所述石墨烯表面。
在本发明的石墨烯薄膜晶体管的制备方法中，其中所述金属层的厚度为5nm~50nm。
在本发明的石墨烯薄膜晶体管的制备方法中，其中所述金属层包括单层金属层或复合层金属层。
在本发明的石墨烯薄膜晶体管的制备方法中，其中当所述金属层为复合层金属层时，每种金属层的厚度相同。
在本发明的石墨烯薄膜晶体管的制备方法中，其中所述金属层采用的金属包括钛、金、镍、钯或铂。
在本发明的石墨烯薄膜晶体管的制备方法中，其中所述支撑层的密度小于所述铜腐蚀液的密度。
在本发明的石墨烯薄膜晶体管的制备方法中，其中所述支撑层为聚氨酯材料。
在本发明的石墨烯薄膜晶体管的制备方法中，其中所述目标衬底包括绝缘层，其中，绝缘层的材料包括二氧化硅、碳化硅、玻璃或蓝宝石。
本发明实施例提供一种石墨烯薄膜晶体管的制备方法，所述制备方法包括：
S1、在铜箔表面沉积石墨烯层；
S2、在石墨烯层表面沉积金属层；
S3、在金属层表面贴合支撑层，从而形成石墨烯膜片；
S4、将石墨烯膜片放置在铜腐蚀液中，其中支撑层部分沉浸在铜腐蚀液中，而金属层、石墨烯层和铜箔完全沉浸在铜腐蚀液中，直至铜箔完全溶解掉，再将去掉铜箔的石墨烯膜片转移至目标衬底，去掉支撑层；
S5、在金属层表面上定义源漏极图形，制备源漏极电极，并在目标衬底上远离石墨烯层的一侧制备栅极电极，从而获得石墨烯薄膜晶体管。
在本发明的石墨烯薄膜晶体管的制备方法中，在S1之前，还包括：将铜箔依次在乙醇、丙酮、0.5mol/L的稀盐酸中进行清洗。
在本发明的石墨烯薄膜晶体管的制备方法中，石墨烯采用化学气相沉积法沉积在铜箔表面上。
在本发明的石墨烯薄膜晶体管的制备方法中，金属层采用电子束蒸发或者磁控溅射技术沉积在石墨烯表面。
在本发明的石墨烯薄膜晶体管的制备方法中，金属层的厚度为5nm~50nm。
在本发明的石墨烯薄膜晶体管的制备方法中，金属层包括单层金属层或复合层金属层。
在本发明的石墨烯薄膜晶体管的制备方法中，金属层采用的金属包括钛、金、镍、钯或铂。
在本发明的石墨烯薄膜晶体管的制备方法中，支撑层的密度小于所述铜腐蚀液的密度。
在本发明的石墨烯薄膜晶体管的制备方法中，支撑层为聚氨酯材料。
在本发明的石墨烯薄膜晶体管的制备方法中，目标衬底包括绝缘层，其中，绝缘层的材料包括二氧化硅、碳化硅、玻璃或蓝宝石。
 有益效果
与现有技术相比，本发明的石墨烯薄膜晶体管的制备方法中，通过在石墨烯层表面沉积金属层，将石墨烯层保护起来，使得石墨烯层不与支撑层和光刻胶直接接触，从而避免石墨烯表面出现残留物的问题，使得源漏极电极与石墨烯层可以完全接触，降低源漏极电极与石墨烯间的接触电阻，从而解决现有制备方法中，因石墨烯层表面残留PMMA和光刻胶而引起源漏极电极与石墨烯间的接触电阻增大的问题。
 附图说明
图1为本发明的石墨烯薄膜晶体管的制备方法的优选实施例的流程图；
图2为本发明的石墨烯薄膜晶体管的制备方法中石墨烯膜片的结构示意图；
图3为根据本发明提供的制备方法制备出的石墨烯薄膜晶体管的背栅的转移曲线图。
 本发明的最佳实施方式
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面对实施例中所需要使用的附图作简单的介绍。下面描述中的附图仅为本发明的部分实施例，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
请参照图1，图1为本发明的石墨烯薄膜晶体管的制备方法的优选实施例的流程图。该制备方法包括以下几个步骤：
S101、在铜箔表面沉积石墨烯层；
S102、在石墨烯层表面沉积金属层；
S103、在金属层表面贴合支撑层，从而形成石墨烯膜片；
S104、将石墨烯膜片放置在铜腐蚀液中，其中支撑层部分沉浸在铜腐蚀液中，而金属层、石墨烯层和铜箔完全沉浸在铜腐蚀液中，直至铜箔完全溶解掉，再将去掉铜箔的石墨烯膜片转移至目标衬底，去掉支撑层；
S105、在金属层表面上定义源漏极图形，制备源漏极电极，并在目标衬底上远离石墨烯层的一侧制备栅极电极，从而获得石墨烯薄膜晶体管。
在S101中，在铜箔表面沉积石墨烯层之前，还需要对铜箔表面的油污、氧化物等杂质进行清洁操作，在本优选实施例中，所采用的清洁操作为：将铜箔依次在乙醇、丙酮、0.5mol/L的稀盐酸中进行清洗，直至铜箔表面的杂质去除干净为止，从而使得铜箔表面达到生长石墨烯的工艺要求。
在本优选实施例中，将采用化学气相沉积法在铜箔表面沉积石墨烯层。化学气相沉积法制备的石墨烯具有质量高、生长面积大等优点，是目前制备高质量石墨烯的主要方法，其原理是将一种或多种气态物质导入到一个反应腔内发生化学反应，生成一种新的材料沉积在衬底表面。
在采用化学气相沉积法沉积石墨烯层时，我们选用氢气作为非氧化性气体通入到反应腔内，以去除反应腔内的氧化性气体，当然也可以采用氩气等其他气体作为非氧化性气体，在此不做具体限定。我们采用甲烷作为碳源，碳源也可以为其他含碳物质，如一氧化碳、乙炔等等，在此不做具体限制。在高温低压的环境下，完成在铜箔表面沉积石墨烯层的步骤。
在S102中，采用磁控溅射技术将金属沉积在石墨烯层表面，在石墨烯层表面形成金属层。在其他的实施例中，也可以采用电子束蒸发技术等其他技术将金属沉积在石墨烯层表面，在此不做具体限制。
在本优选实施例中，金属层为复合金属层，其包括两层金属层，其中靠近石墨烯层表面的一层金属层为钛金属层，远离石墨烯层表面的一层金属层为金金属层，将钛金属层设置在更靠近石墨烯层的好处是，钛金属与石墨烯之间容易发生键和，可进一步降低钛金属层与石墨烯层之间的接触电阻。
当然，在其他的实施例中，金属层可以为单层金属层，也可以为三层、四层等复合金属层，金属层的金属也可以为钛、金、镍、钯或铂中的一种或几种，在此不对金属层的层数以及金属的种类做具体限制。
在石墨烯层表面沉积金属层时，需要控制金属的注入量，即控制金属层的厚度，金属层的厚度过小，则对石墨烯层起不到很好的保护作用，金属层的厚度过大，则在后续溶解铜箔的过程会使得支撑层无法将金属层、石墨烯层和铜箔悬浮于铜腐蚀液中，即容易使得支撑层、金属层、石墨烯层和铜箔一起掉进铜腐蚀液中，对后续的工序造成不便，因此金属层的厚度要有一定的限制，一般金属层的厚度为5nm~50nm，在本优选实施例中，金属层的厚度优选为10nm，且钛金属层和金金属层的厚度各为5nm。
在S103中，在金属层的表面贴合一支撑层，且该支撑层的密度要小于铜腐蚀液的密度，其中支撑层的密度与铜腐蚀液的密度相差的越大越好，其目的是利用支撑层与铜腐蚀液间的密度差，来使得支撑层漂浮在铜腐蚀液表面，即在后续溶解铜箔的步骤中，支撑层可以将金属层、石墨烯层以及铜箔悬浮在铜腐蚀液中，不让其掉入铜腐蚀液中。支撑层除了上述作用外，其还给后续将去掉铜箔的石墨烯膜片转移至目标衬底上提供方便。
在本优选实施例里，支撑层为聚氨酯材料，在其他实施例中，也可以为其他密度小于铜腐蚀液密度的材料，在此不做具体限定。
为了进一步清晰描述石墨烯膜片的结构，下面将给出石墨烯膜片的结构示意图，请参加图2，图2为本发明的石墨烯薄膜晶体管的制备方法中石墨烯膜片的结构示意图。石墨烯膜片从下至上依次包括：铜箔21、石墨烯层22、金属层23和支撑层24。
在S104中，将石墨烯膜片放置在铜腐蚀液中，此时，由于支撑层的密度小于铜腐蚀液的密度，支撑层会漂浮在铜腐蚀液表面上，而金属层、石墨烯层以及铜箔将沉浸在铜腐蚀液中。当铜箔完全腐蚀掉后，将去掉铜箔的石墨烯膜片转移至目标衬底上，再将支撑层去掉。
在本优选实施例中，目标衬底包括绝缘层，根据公知常识可知，石墨烯膜片转移至目标衬底的绝缘层上。其中，绝缘层采用二氧化硅材料，当然也可以采用碳化硅、玻璃或蓝宝石材料，在此不做具体限定。
在S105中，在金属层表面上采用光刻技术定义源漏极图形，再通过磁控溅射技术或者电子束蒸发技术将金金属沉积到源漏极图形的相应位置，再采用干法刻蚀技术将沟道区域的金属层刻蚀掉，露出沟道区域的石墨烯层；同时，在目标衬底上远离石墨烯层的一侧制备栅极电极，由于制备源极、漏极和栅极电极所采用的方法步骤为现有技术，为本领域技术人员公知的常识，因此在本优选实施例中不再做赘述。完成S105步骤后，即可以得到具有低接触电阻的石墨烯薄膜晶体管。
在现有的制备石墨烯薄膜晶体管的方法中，采用光刻技术定义源漏极图形是在石墨烯层表面直接进行的，再通过磁控溅射技术或者电子束蒸发技术在源漏极图形的相应位置沉积一层薄的钛金属和一层厚的金金属，从而形成源漏极电极，在整个过程中，石墨烯层与光刻技术所采用的光刻胶直接接触，在溶解光刻胶时，就会出现光刻胶残留在石墨烯层表面的问题，使得石墨烯层与源漏极电极的接触不完全，引起石墨烯层与源漏极电极的接触电阻变大。
而本优选实施例提供的制备方法中，采用光刻技术定义源漏极图形是在金属层表面进行的，这样石墨烯层与光刻胶不会接触，在溶解光刻胶时也不会出现光刻胶残留在石墨烯层表面的问题；同时，金属层采用了源漏极的目标金属钛金属和金金属，在后续采用磁控溅射技术或者电子束蒸发技术将金金属沉积到源漏极所对应的位置时，也不需要去除相应位置的金属层，因此，在整个制备石墨烯薄膜晶体管的过程中，石墨烯均受到金属层的保护，确保石墨烯层与源漏极电极充分地接触，降低石墨烯层与源漏极电极的接触电阻。
在制备完成石墨烯薄膜晶体管后，我们测试了石墨烯薄膜晶体管的背栅的转移曲线，请参见图3，图中纵坐标为漏极电流 ，单位为毫安，横坐标为栅极电压 ，单位为伏特，在测试背栅的转移曲线时，将源极接地。从图中可以看出，在不同的漏极电压 下，漏极电流最小值均出现在 等于0的位置，这说明石墨烯薄膜晶体管沟道区域的石墨烯没有掺杂，即在石墨烯层表面没有残留任何杂质，本征特性良好；而现有技术制备的石墨烯薄膜晶体管，其由于在石墨烯表面残留有PMMA和光刻胶等杂质，漏极电流的最小值将出现在0伏特的左侧或者右侧，即破坏了石墨烯场效应器件的双极对称性，使得石墨烯与源漏极间的接触电阻增大。从图中还可以看出，在 一定的情况下，漏极电压 以5mv的幅度不断地增加时，漏极电流 增加的幅度基本相同，即漏极电流 与漏极电压 成正比例关系，说明石墨烯薄膜晶体管的电学性能优良。
本优选实施例提供的石墨烯薄膜晶体管的制备方法中，通过在石墨烯层表面沉积10nm厚的金属层，使得石墨烯层与支撑层以及后续使用的光刻胶不接触，从而避免石墨烯表面出现残留物的问题，使得源漏极电极与石墨烯层可以完全接触，降低源漏极电极与石墨烯间的接触电阻，增加了石墨烯薄膜晶体管中的电流，解决了现有制备方法中，因石墨烯层表面残留PMMA和光刻胶而引起源漏极电极与石墨烯间的接触电阻增大的问题。
另外，根据本优选实施例提供的制备方法制备出的石墨烯薄膜晶体管中的石墨烯层表面的起伏度小于0.1nm，远小于现有制备方法制备出的石墨烯薄膜晶体管中的石墨烯层表面起伏度1nm，可见本优选实施例制备方法制备出的石墨烯薄膜晶体管具有更好的电学性能。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种石墨烯薄膜晶体管的制备方法，其包括：
    S1、以甲烷作为碳源，采用化学气相沉积法，在铜箔表面沉积石墨烯层；
    S2、在所述石墨烯层表面沉积金属层；
    S3、在所述金属层表面贴合支撑层，从而形成石墨烯膜片；
    S4、将所述石墨烯膜片放置在铜腐蚀液中，其中所述支撑层部分沉浸在铜腐蚀液中，而所述金属层、石墨烯层和铜箔完全沉浸在铜腐蚀液中，直至所述铜箔完全溶解掉，再将去掉铜箔的石墨烯膜片转移至目标衬底，去掉所述支撑层；
    S5、在所述金属层表面上定义源漏极图形，制备源漏极电极，并在目标衬底上远离石墨烯层的一侧制备栅极电极，从而获得石墨烯薄膜晶体管。
  2. 根据权利要求1所述的石墨烯薄膜晶体管的制备方法，其中在S1之前，还包括：将所述铜箔依次在乙醇、丙酮、0.5mol/L的稀盐酸中进行清洗。
  3. 根据权利要求1所述的石墨烯薄膜晶体管的制备方法，其中所述金属层采用电子束蒸发或者磁控溅射技术沉积在所述石墨烯表面。
  4. 根据权利要求1所述的石墨烯薄膜晶体管的制备方法，其中所述金属层的厚度为5nm~50nm。
  5. 根据权利要求4所述的石墨烯薄膜晶体管的制备方法，其中所述金属层包括单层金属层或复合层金属层。
  6. 根据权利要求5所述的石墨烯薄膜晶体管的制备方法，其中当所述金属层为复合层金属层时，每种金属层的厚度相同。
  7. 根据权利要求5所述的石墨烯薄膜晶体管的制备方法，其中所述金属层采用的金属包括钛、金、镍、钯或铂。
  8. 根据权利要求1所述的石墨烯薄膜晶体管的制备方法，其中所述支撑层的密度小于所述铜腐蚀液的密度。
  9. 根据权利要求8所述的石墨烯薄膜晶体管的制备方法，其中所述支撑层为聚氨酯材料。
  10. 根据权利要求1所述的石墨烯薄膜晶体管的制备方法，其中所述目标衬底包括绝缘层，其中，绝缘层的材料包括二氧化硅、碳化硅、玻璃或蓝宝石。
  11. 一种石墨烯薄膜晶体管的制备方法，其包括：
    S1、在铜箔表面沉积石墨烯层；
    S2、在所述石墨烯层表面沉积金属层；
    S3、在所述金属层表面贴合支撑层，从而形成石墨烯膜片；
    S4、将所述石墨烯膜片放置在铜腐蚀液中，其中所述支撑层部分沉浸在铜腐蚀液中，而所述金属层、石墨烯层和铜箔完全沉浸在铜腐蚀液中，直至所述铜箔完全溶解掉，再将去掉铜箔的石墨烯膜片转移至目标衬底，去掉所述支撑层；
    S5、在所述金属层表面上定义源漏极图形，制备源漏极电极，并在目标衬底上远离石墨烯层的一侧制备栅极电极，从而获得石墨烯薄膜晶体管。
  12. 根据权利要求11所述的石墨烯薄膜晶体管的制备方法，其中在S1之前，还包括：将所述铜箔依次在乙醇、丙酮、0.5mol/L的稀盐酸中进行清洗。
  13. 根据权利要求11所述的石墨烯薄膜晶体管的制备方法，其中所述石墨烯采用化学气相沉积法沉积在所述铜箔表面上。
  14. 根据权利要求11所述的石墨烯薄膜晶体管的制备方法，其中所述金属层采用电子束蒸发或者磁控溅射技术沉积在所述石墨烯表面。
  15. 根据权利要求11所述的石墨烯薄膜晶体管的制备方法，其中所述金属层的厚度为5nm~50nm。
  16. 根据权利要求15所述的石墨烯薄膜晶体管的制备方法，其中所述金属层包括单层金属层或复合层金属层。
  17. 根据权利要求16所述的石墨烯薄膜晶体管的制备方法，其中所述金属层采用的金属包括钛、金、镍、钯或铂。
  18. 根据权利要求11所述的石墨烯薄膜晶体管的制备方法，其中所述支撑层的密度小于所述铜腐蚀液的密度。
  19. 根据权利要求18所述的石墨烯薄膜晶体管的制备方法，其中所述支撑层为聚氨酯材料。
  20. 根据权利要求11所述的石墨烯薄膜晶体管的制备方法，其中所述目标衬底包括绝缘层，其中，绝缘层的材料包括二氧化硅、碳化硅、玻璃或蓝宝石。
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