WO2019100427A1 - 一种柔性阵列基板的制作方法及柔性阵列基板 - Google Patents

一种柔性阵列基板的制作方法及柔性阵列基板 Download PDF

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WO2019100427A1
WO2019100427A1 PCT/CN2017/113697 CN2017113697W WO2019100427A1 WO 2019100427 A1 WO2019100427 A1 WO 2019100427A1 CN 2017113697 W CN2017113697 W CN 2017113697W WO 2019100427 A1 WO2019100427 A1 WO 2019100427A1
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insulating layer
layer
array substrate
flexible array
substrate
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PCT/CN2017/113697
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English (en)
French (fr)
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刘翔
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/743,281 priority Critical patent/US10411206B2/en
Publication of WO2019100427A1 publication Critical patent/WO2019100427A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a flexible array substrate and a flexible array substrate.
  • Thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, referred to as TFT-LCD, has a small size, low power consumption, no radiation, and has a dominant position in the current flat panel display market.
  • TFT-LCD Generally, it includes a backlight, an upper and lower polarizer, a liquid crystal cell, a driving and control IC, and the like, wherein the core component is a liquid crystal cell.
  • the liquid crystal cell generally uses an array substrate and a color film substrate to be filled into the liquid crystal (Liquid Made from Crystal, LC).
  • the invention provides a method for fabricating a flexible array substrate, the preparation method comprising:
  • the substrate is a transparent glass substrate or a plastic substrate.
  • the first insulating layer includes a third insulating layer and a fourth insulating layer on the third insulating layer, wherein the third insulating layer is made of an organic resin, and the fourth insulating layer is made of a material. It is an oxide, a nitride or an oxynitride.
  • the metal oxide semiconductor layer has a thickness of 50 angstroms - 2000. Between the ang.
  • the material of the second insulating layer is an organic resin.
  • the thickness of the second insulating layer is between 4000 ⁇ and 30,000. Between the ang.
  • the metal oxide semiconductor layer is amorphous indium gallium zinc oxide.
  • the first graphene layer and the second graphene layer may be deposited by a chemical vapor deposition method or a spin coating method.
  • the invention also provides a method for fabricating a flexible array substrate, the preparation method comprising:
  • the substrate is a transparent glass substrate or a plastic substrate.
  • the first insulating layer includes a third insulating layer and a fourth insulating layer on the third insulating layer, wherein the third insulating layer is made of a material
  • the organic resin is made of an oxide, a nitride or an oxynitride.
  • the metal oxide semiconductor layer has a thickness of 50 angstroms - 2000. Between the ang.
  • the material of the second insulating layer is an organic resin.
  • the thickness of the second insulating layer is between 4000 ⁇ and 30,000. Between the ang.
  • the metal oxide semiconductor layer is amorphous indium gallium zinc oxide.
  • the first graphene layer and the second graphene layer may be deposited by a chemical vapor deposition method or a spin coating method.
  • a flexible array substrate comprising:
  • a substrate a gate and a scan line disposed on the substrate, a first insulating layer disposed on the gate and the scan line, a conductive channel disposed on the first insulating layer, and the conductive layer disposed a source, a drain, and a data line on the channel, a second insulating layer disposed on the source, the drain, and the data line, and a pixel electrode disposed on the second insulating layer, and the conductive trench a channel is connected to the source and the drain, and the pixel electrode is connected to the drain through a via hole;
  • the gate and scan lines after the first graphene layer is patterned Forming the gate and scan lines after the first graphene layer is patterned; the conductive channel is formed by patterning a metal oxide semiconductor layer; and the source, drain, and data lines are passed through the second graphene A layer patterning process is formed; the pixel electrode is formed by patterning a carbon nanotube layer.
  • the substrate is a transparent glass substrate or a plastic substrate.
  • the first insulating layer includes a third insulating layer and a fourth insulating layer on the third insulating layer, wherein the third insulating layer is made of an organic resin.
  • the fourth insulating layer is made of an oxide, a nitride or an oxynitride.
  • the metal oxide semiconductor layer has a thickness of between 50 ⁇ and 2,000 ⁇ .
  • the material of the second insulating layer is an organic resin.
  • the second insulating layer has a thickness of between 4,000 angstroms and 30,000 angstroms.
  • the method for fabricating the flexible array substrate and the flexible array substrate of the invention adopts a graphene material to form a gate, a scan line, a source, a drain and a data line, thereby effectively reducing the delay of the image signal and improving the display quality; and using the metal
  • the oxide semiconductor is made into a conductive channel to have good light transmittance and flexibility.
  • FIG. 1 is a flow chart of a method for fabricating a flexible array substrate according to a preferred embodiment of the present invention
  • 2A-2L are schematic diagrams showing specific steps of a method for fabricating an array substrate according to a preferred embodiment of the present invention.
  • the graphene used in the method for fabricating the array substrate of the present invention is a hexagonal type composed of carbon atoms and sp2 hybrid orbital.
  • the planar film of the crystal lattice which is a two-dimensional material with a thickness of one carbon atom, is the thinnest but hardest nano material in the world, and is almost completely transparent. For example, the thickness is 0.34
  • the nano-single-layer graphene film absorbs only 2.3% of light and has a high light transmittance.
  • its thermal conductivity is as high as 5300 W/m ⁇ K , which is higher than that of carbon nanotubes and diamonds; and its electron mobility exceeds at room temperature.
  • the method for fabricating the array substrate of the present invention uses a graphene material to form a gate, a scan line, a source, a drain, and a data line, thereby reducing image signals on the gate, the scan line, the source, the drain, and the data line.
  • the delay which in turn improves the display quality, and has good light transmission and flexibility.
  • the method for fabricating the array substrate of the present invention further uses a metal oxide semiconductor material to form a conductive channel
  • the metal oxide semiconductor material may be: amorphous indium gallium zinc oxide, which has high carrier mobility and can improve the film.
  • the charge-discharge rate of the transistor to the pixel electrode improves the response speed of the pixel, and the uniformity is good, which can better satisfy the large-scale flexibility. TFT-LCD requirements.
  • FIG. 1 A flowchart of a method of fabricating a flexible array substrate provided by a preferred embodiment of the present invention. As shown in FIG. 1 , a preferred embodiment of the present invention provides a method for fabricating a flexible array substrate, the method comprising the following steps:
  • Step S101 providing a substrate
  • Step S102 Depositing a first graphene layer on the substrate, patterning the first graphene layer to form a gate electrode and a scan line;
  • Step S103 forming a first insulating layer on the substrate, the gate, and the scan line;
  • Step S104 Depositing a metal oxide semiconductor layer on the first insulating layer, and patterning the metal oxide semiconductor layer to form a conductive channel;
  • Step S105 Depositing a second graphene layer on the conductive channel and the first insulating layer, and patterning the second graphene layer to form a source, a drain, and a data line, wherein the conductive channel Connected to the source and the drain;
  • Step S106 forming a second insulating layer on the substrate, the source, the drain, and the data line;
  • Figure 2A-2L A schematic diagram of specific steps of a method for fabricating an array substrate provided by a preferred embodiment of the present invention.
  • a substrate 201 is provided. It should be noted that the substrate 201 It can be a transparent glass substrate or a plastic substrate. If a transparent substrate is used, the thickness of the transparent glass substrate should be less than 0.1 mm. If a plastic substrate is used, the material of the plastic substrate can be polyimide.
  • step S102 as shown in FIG. 2B, a first graphene layer 202 is deposited on the substrate 201, first on the substrate. A layer of graphene material is coated on the 201 by chemical vapor deposition or spin coating. Subsequently, as shown in FIG. 2C, a gate electrode 2021 and a scan line 2022 are formed by a patterning process. a pattern of the first graphene layer.
  • a first insulating layer 203 is formed on the first graphene layer 202, and the first insulating layer 203 Used to isolate the first graphene layer 202.
  • the first insulating layer 203 includes a third insulating layer 2031 and a fourth insulating layer 2032 on the third insulating layer 2031.
  • the third insulating layer 2031 is made of an organic resin
  • the fourth insulating layer 2032 is made of an oxide, a nitride or an oxynitride.
  • the third insulating layer 2031 is first coated on the first graphene layer 202 by spin coating. Subsequently, a fourth insulating layer 2032 is deposited on the third insulating layer 2031 by chemical vapor deposition, wherein the fourth insulating layer 2032 has a thickness of between 100 ⁇ and 1000 ⁇ .
  • a metal oxide semiconductor layer 204 is deposited on the first insulating layer.
  • the metal oxide semiconductor layer 204 may be formed by a sputtering method, and the metal oxide semiconductor layer 204 has a thickness of between 50 ⁇ and 2000 ⁇ .
  • the metal oxide semiconductor layer 204 may be amorphous indium gallium zinc oxide; subsequently, as shown in Fig. 2F, a conductive channel 2041 is formed by a patterning process.
  • a second graphene layer 205 is deposited on the metal oxide semiconductor layer 204.
  • a layer of graphene material is coated on the metal oxide semiconductor layer 204 by chemical vapor deposition or spin coating.
  • a source 2051 and a drain are formed by a patterning process. 2052.
  • a second insulating layer 206 is formed on the second graphene layer 205.
  • the material of the second insulating layer 206 is an organic resin, and the thickness of the second insulating layer 206 is between 4000 angstroms and 30,000 angstroms.
  • step S107 a carbon nanotube layer 207 is deposited on the second insulating layer 206, and a pixel electrode is formed by a patterning process. 2071, wherein the pixel electrode 2071 is connected to the drain 2052 through the through hole 2072.
  • a through hole 2072 is first formed on the second insulating layer 206; subsequently, as shown in FIG. 2K As shown, a carbon nanotube layer 207 is deposited on the second insulating layer 206; finally, as shown in FIG. 2L, a pixel electrode 2071 is formed by a patterning process, wherein the pixel electrode 2071 passes through the via hole 2072 is connected to drain 2052.
  • a flexible array substrate can be obtained by the above method.
  • the method for fabricating the flexible array substrate of the preferred embodiment uses the graphene material to form the gate, the scan line, the source, the drain, and the data line, thereby effectively reducing the delay of the image signal and improving the display quality; and using the metal oxide
  • the semiconductor is made into a conductive channel to provide good light transmission and flexibility.
  • the present invention also provides a flexible array substrate, which is fabricated by the method for fabricating the flexible array substrate in the above preferred embodiment, and specifically refers to the flexibility made in the method for fabricating the flexible array substrate in the above preferred embodiment.
  • the related description of the array substrate will not be described herein.
  • the method for fabricating the flexible array substrate and the flexible array substrate of the invention adopts a graphene material to form a gate, a scan line, a source, a drain and a data line, thereby effectively reducing the delay of the image signal and improving the display quality; and using the metal
  • the oxide semiconductor is made into a conductive channel to have good light transmittance and flexibility.

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Abstract

本发明提供一种柔性阵列基板的制作方法及柔性阵列基板，其包括：基板、设置在基板上的栅极和扫描线、设置在栅极和扫描线上的第一绝缘层、设置在第一绝缘层上的导电沟道、设置在导电沟道上的源极、漏极和数据线、设置在源极、漏极和数据线上的第二绝缘层、及设置在第二绝缘层上的像素电极。

Description

一种柔性阵列基板的制作方法及柔性阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种柔性阵列基板的制作方法及柔性阵列基板。
背景技术
薄膜晶体管液晶显示器（ Thin Film Transistor Liquid Crystal Display ，简称 TFT-LCD ）具有体积小、功耗低、无辐射等特点，在当前的平板显示器市场中占据了主导地位。 TFT-LCD 一般包括背光源、上下偏光片、液晶盒、驱动与控制 IC 等部分，其中，核心部件是液晶盒。液晶盒一般采用阵列基板与彩膜基板对盒后灌入液晶（ Liquid Crystal ， LC ）制成。
然而，随着 TFT-LCD 的飞速发展， TFT-LCD 的尺寸不断增大、分辨率不断提高，进而造成图像信号的延迟越来越严重。图像信号的延迟主要由 T=RC 决定，其中 R 为信号电阻， C 为相关电容， R 一般与栅极、扫描线、数据线等阵列配线的材料有关；现有的阵列基板的制作方法中，一般采用化学性质稳定、电阻率高的金属材料制成栅极、扫描线、数据线等阵列配线，且随着 TFT-LCD 的飞速发展， TFT-LCD 的尺寸不断增大、分辨率不断提高，从而使得图像信号的延迟更加严重。另外，随着人们对显示技术需求的不断提高，未来的显示装置向柔性、透明方向发展，但是现有的用于形成栅极、扫描线、数据线等阵列配线的材料具有不可透光性、且在弯曲时性能恶化，不能满足透明、柔性器件的需求。
故，有必要提供一种柔性阵列基板的制作方法，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种柔性阵列基板的制作方法，能有效减弱图像信号的延迟，进而提高显示质量，并且具有良好的透光性和柔性。
技术解决方案
本发明提供一种柔性阵列基板的制作方法，所述制备方法包括：
提供一基板；
在所述基板上沉积第一石墨烯层，对所述第一石墨烯层进行图案化处理，形成栅极、扫描线；
在所述基板、栅极、扫描线上形成第一绝缘层；
在所述第一绝缘层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行图案化处理，形成导电沟道；
在所述导电沟道、第一绝缘层上沉积第二石墨烯层，对所述第二石墨烯层进行图案化处理，形成源极、漏极、数据线，其中，所述导电沟道与所述源极、所述漏极相连接；
在所述基板、源极、漏极、数据线上形成第二绝缘层；以及
在所述第二绝缘层上沉积碳纳米管层，对所述碳纳米管层进行图案化处理，形成像素电极，所述像素电极通过通孔与所述漏极相连接；
所述基板为透明玻璃基板或塑料基板。
所述第一绝缘层包括第三绝缘层以及位于所述第三绝缘层上的第四绝缘层，其中，所述第三绝缘层采用的材料为有机树脂，所述第四绝缘层采用的材料为氧化物、氮化物或氮氧化合物。
在本发明的柔性阵列基板的制作方法中，所述金属氧化物半导体层的厚度介于 50 埃 -2000 埃之间。
在本发明的柔性阵列基板的制作方法中，所述第二绝缘层的材料为有机树脂。
在本发明的柔性阵列基板的制作方法中，所述第二绝缘层的厚度介于 4000 埃 -30000 埃之间。
在本发明的柔性阵列基板的制作方法中，所述金属氧化物半导体层为非晶铟镓锌氧化物。
在本发明的柔性阵列基板的制作方法中，可通过化学气相沉积法或旋涂法沉积所述第一石墨烯层和所述第二石墨烯层。
本发明还提供一种柔性阵列基板的制作方法，所述制备方法包括：
提供一基板；
在所述基板上沉积第一石墨烯层，对所述第一石墨烯层进行图案化处理，形成栅极、扫描线；
在所述基板、栅极、扫描线上形成第一绝缘层；
在所述第一绝缘层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行图案化处理，形成导电沟道；
在所述导电沟道、第一绝缘层上沉积第二石墨烯层，对所述第二石墨烯层进行图案化处理，形成源极、漏极、数据线，其中，所述导电沟道与所述源极、所述漏极相连接；
在所述基板、源极、漏极、数据线上形成第二绝缘层；以及
在所述第二绝缘层上沉积碳纳米管层，对所述碳纳米管层进行图案化处理，形成像素电极，所述像素电极通过通孔与所述漏极相连接。
在本发明的柔性阵列基板的制作方法中，所述基板为透明玻璃基板或塑料基板。
在本发明的柔性阵列基板的制作方法中，所述第一绝缘层包括第三绝缘层以及位于所述第三绝缘层上的第四绝缘层，其中，所述第三绝缘层采用的材料为有机树脂，所述第四绝缘层采用的材料为氧化物、氮化物或氮氧化合物。
在本发明的柔性阵列基板的制作方法中，所述金属氧化物半导体层的厚度介于 50 埃 -2000 埃之间。
在本发明的柔性阵列基板的制作方法中，所述第二绝缘层的材料为有机树脂。
在本发明的柔性阵列基板的制作方法中，所述第二绝缘层的厚度介于 4000 埃 -30000 埃之间。
在本发明的柔性阵列基板的制作方法中，所述金属氧化物半导体层为非晶铟镓锌氧化物。
在本发明的柔性阵列基板的制作方法中，可通过化学气相沉积法或旋涂法沉积所述第一石墨烯层和所述第二石墨烯层。
依据本发明的上述目的，还提供一种柔性阵列基板，包括：
基板、设置在所述基板上的栅极和扫描线、设置在所述栅极和扫描线上的第一绝缘层、设置在所述第一绝缘层上的导电沟道、设置在所述导电沟道上的源极、漏极和数据线、设置在所述源极、漏极和数据线上的第二绝缘层、及设置在所述第二绝缘层上的像素电极，且所述导电沟道与所述源极、所述漏极连接，所述像素电极通过通孔与所述漏极相连接；其中，
所述栅极和扫描线经第一石墨烯层图案化处理后形成；所述导电沟道经金属氧化物半导体层图案化处理形成；所述源极、漏极和数据线经第二石墨烯层图案化处理形成；所述像素电极经碳纳米管层图案化处理形成。
在本发明的柔性阵列基板中，所述基板为透明玻璃基板或塑料基板。
在本发明的柔性阵列基板中，所述第一绝缘层包括第三绝缘层以及位于所述第三绝缘层上的第四绝缘层，其中，所述第三绝缘层采用的材料为有机树脂，所述第四绝缘层采用的材料为氧化物、氮化物或氮氧化合物。
在本发明的柔性阵列基板中，所述金属氧化物半导体层的厚度介于 50 埃 -2000 埃之间。
在本发明的柔性阵列基板中，所述第二绝缘层的材料为有机树脂。
在本发明的柔性阵列基板中，所述第二绝缘层的厚度介于 4000 埃 -30000 埃之间。
 有益效果
本发明的柔性阵列基板的制作方法及柔性阵列基板，采用石墨烯材料制成栅极、扫描线、源极、漏极以及数据线，有效减弱了图像信号的延迟，提高显示质量；且采用金属氧化物半导体制成导电沟道，使其具有良好的透光性和柔性。
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图 1 为本发明优选实施例提供的柔性阵列基板的制作方法的流程图；
图 2A-2L 为本发明优选实施例提供的阵列基板的制作方法的具体步骤示意图。
 本发明的最佳实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
下面对石墨烯材料以及金属氧化物半导体材料在本发明的阵列基板的制作方法中的应用做进一步的说明。
本发明的阵列基板的制作方法中采用的石墨烯是一种由 碳原子 以 sp2杂化 轨道组成六角型呈 蜂巢 晶格的平面 薄膜 ，只有一个碳原子厚度的 二维 材料，是目前世界上最薄却也是最坚硬的纳米材料，近乎是完全透明的。例如厚度为 0.34 纳米的单层石墨烯薄膜只吸收 2.3% 的光，透光率高。另外，其导热系数高达 5300W/m · K ，高于碳纳米管和金刚石 ；且常温下其电子迁移率超过 15000cm2/ （ V · s ），比纳米碳管或晶体硅高；而电阻率只有约 6 ～ 10 Ω· cm ，比铜或银等金属更低，为目前世界上电阻率最小的材料。因此，石墨烯作为一种透明、柔性的导体，可以满足大尺寸柔性 TFT-LCD 的需求。本发明的阵列基板的制作方法，采用石墨烯材料制成栅极、扫描线、源极、漏极以及数据线，从而减弱图像信号在栅极、扫描线、源极、漏极和数据线上的延迟，进而提高显示质量，且具有良好的透光性和柔性。
另外，本发明的阵列基板的制作方法还采用金属氧化物半导体材料制作导电沟道，该金属氧化物半导体材料可为：非晶铟镓锌氧化物，其载流子迁移率高，可以提高薄膜晶体管对像素电极的充放电速率，提高像素的响应速度，且均一性良好，可以更好的满足大尺寸柔性 TFT-LCD 的需求。
下面对本发明的阵列基板的制作方法进行详细的描述。参阅图 1 ，图 1 为本发明优选实施例提供的柔性阵列基板的制作方法的流程图。如图 1 所示，本发明优选实施例提供一种柔性阵列基板的制作方法，该方法包括以下步骤：
步骤 S101 ，提供一基板；
步骤 S102 ，在所述基板上沉积第一石墨烯层，对所述第一石墨烯层进行图案化处理，形成栅极、扫描线；
步骤 S103 ，在所述基板、栅极、扫描线上形成第一绝缘层；
步骤 S104 ，在所述第一绝缘层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行图案化处理，形成导电沟道；
步骤 S105 ，在所述导电沟道、第一绝缘层上沉积第二石墨烯层，对所述第二石墨烯层进行图案化处理，形成源极、漏极、数据线，其中，所述导电沟道与所述源极、所述漏极相连接；
步骤 S106 ，在所述基板、源极、漏极、数据线上形成第二绝缘层；
步骤 S107 ，在所述第二绝缘层上沉积碳纳米管层，对所述碳纳米管层进行图案化处理，形成像素电极，所述像素电极通过通孔与所述漏极相连接。
下面结合图 2A-2L 对本优选实施例的具体步骤进行详细说明。图 2A-2L 为本发明优选实施例提供的阵列基板的制作方法的具体步骤示意图。
如图 2A 所示，在步骤 S101 中，提供一基板 201 ，需要说明的是，该基板 201 可为透明玻璃基板或塑料基板，其中，若选用透明基板，应保证该透明玻璃基板的厚度小于 0.1 毫米；若选用塑料基板，该塑料基板的材料可为聚酰亚胺。
在步骤 S102 中，如图 2B 所示，在基板 201 上沉积第一石墨烯层 202 ，首先在基板 201 上利用化学气相沉积法或者旋涂法涂覆一层石墨烯材料。随后，如图 2C 所示，通过构图工艺形成包括栅极 2021 、扫描线 2022 的第一石墨烯层的图案。
在步骤 S103 中，在第一石墨烯层 202 上形成第一绝缘层 203 ，该第一绝缘层 203 用于隔离第一石墨烯层 202 。具体的，该第一绝缘层 203 包括包括第三绝缘层 2031 以及位于第三绝缘层 2031 上的第四绝缘层 2032 ，其中，第三绝缘层 2031 采用的材料为有机树脂，第四绝缘层 2032 采用的材料为氧化物、氮化物或氮氧化合物。
具体的，如图 2D 所示，首先在第一石墨烯层 202 上通过旋涂法涂覆第三绝缘层 2031 ；随后，在第三绝缘层 2031 上通过化学气相沉积法沉积第四绝缘层 2032 ，其中第四绝缘层 2032 的厚度介于 100 埃 -1000 埃之间。
在步骤 S104 中，如图 2E 所示，在第一绝缘层上沉积金属氧化物半导体层 204 ，其中，可通过溅射法形成该金属氧化物半导体层 204 ，该金属氧化物半导体层 204 的厚度介于 50 埃 -2000 埃之间，优选的，该金属氧化物半导体层 204 可为非晶铟镓锌氧化物；随后，如图 2F 所示，通过构图工艺形成导电沟道 2041 。
在步骤 S105 中，如图 2G 所示，在金属氧化物半导体层 204 上沉积第二石墨烯层 205 ，首先在金属氧化物半导体层 204 上利用化学气相沉积法或者旋涂法涂覆一层石墨烯材料。随后，如图 2H 所示，通过构图工艺形成包括源极 2051 、漏极 2052 、数据线 2053 的第二石墨烯层的图案，其中，导电沟道 2041 与源极 2051 、漏极 2052 相连接。
在步骤 S106 中，如图 2I 所示，在第二石墨烯层 205 上形成第二绝缘层 206 ，其中该第二绝缘层 206 的材料为有机树脂，且该第二绝缘层 206 的厚度介于 4000 埃 -30000 埃之间。
在步骤 S107 中，在第二绝缘层 206 上沉积碳纳米管层 207 ，并通过构图工艺形成像素电极 2071 ，其中，像素电极 2071 通过通孔 2072 与漏极 2052 相连接。
具体的，如图 2J 所示，首先在在第二绝缘层 206 上形成一通孔 2072 ；随后，如图 2K 所示，在第二绝缘层 206 上沉积碳纳米管层 207 ；最后，如图 2L 所示，通过构图工艺形成像素电极 2071 ，其中，像素电极 2071 通过通孔 2072 与漏极 2052 相连接。
通过上述方法可制得柔性阵列基板。
本优先实施例的柔性阵列基板的制作方法，采用石墨烯材料制成栅极、扫描线、源极、漏极以及数据线，有效减弱了图像信号的延迟，提高显示质量；且采用金属氧化物半导体制成导电沟道，使其具有良好的透光性和柔性。
本发明还提供一种柔性阵列基板，该柔性阵列基板通过上述优选实施例中的柔性阵列基板的制作方法制成，具体可参照上述优选实施例中的柔性阵列基板的制作方法中制成的柔性阵列基板的相关描述，在此不做赘述。
本发明的柔性阵列基板的制作方法及柔性阵列基板，采用石墨烯材料制成栅极、扫描线、源极、漏极以及数据线，有效减弱了图像信号的延迟，提高显示质量；且采用金属氧化物半导体制成导电沟道，使其具有良好的透光性和柔性。
综上，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种柔性阵列基板的制作方法，其中，所述制备方法包括：
    提供一基板；
    在所述基板上沉积第一石墨烯层，对所述第一石墨烯层进行图案化处理，形成栅极、扫描线；
    在所述基板、栅极、扫描线上形成第一绝缘层；
    在所述第一绝缘层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行图案化处理，形成导电沟道；
    在所述导电沟道、第一绝缘层上沉积第二石墨烯层，对所述第二石墨烯层进行图案化处理，形成源极、漏极、数据线，其中，所述导电沟道与所述源极、所述漏极相连接；
    在所述基板、源极、漏极、数据线上形成第二绝缘层；以及
    在所述第二绝缘层上沉积碳纳米管层，对所述碳纳米管层进行图案化处理，形成像素电极，所述像素电极通过通孔与所述漏极相连接；
    所述基板为透明玻璃基板或塑料基板。
    所述第一绝缘层包括第三绝缘层以及位于所述第三绝缘层上的第四绝缘层，其中，所述第三绝缘层采用的材料为有机树脂，所述第四绝缘层采用的材料为氧化物、氮化物或氮氧化合物。
  2. 根据权利要求 1 所述的柔性阵列基板的制作方法，其中，所述金属氧化物半导体层的厚度介于 50 埃 -2000 埃之间。
  3. 根据权利要求 1 所述的柔性阵列基板的制作方法，其中，所述第二绝缘层的材料为有机树脂。
  4. 根据权利要求 3 所述的柔性阵列基板的制作方法，其中，所述第二绝缘层的厚度介于 4000 埃 -30000 埃之间。
  5. 根据权利要求 1 所述的柔性阵列基板的制作方法，其中，所述金属氧化物半导体层为非晶铟镓锌氧化物。
  6. 根据权利要求 1 所述的柔性阵列基板的制作方法，其中，可通过化学气相沉积法或旋涂法沉积所述第一石墨烯层和所述第二石墨烯层。
  7. 一种柔性阵列基板的制作方法，其中，所述制备方法包括：
    提供一基板；
    在所述基板上沉积第一石墨烯层，对所述第一石墨烯层进行图案化处理，形成栅极、扫描线；
    在所述基板、栅极、扫描线上形成第一绝缘层；
    在所述第一绝缘层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行图案化处理，形成导电沟道；
    在所述导电沟道、第一绝缘层上沉积第二石墨烯层，对所述第二石墨烯层进行图案化处理，形成源极、漏极、数据线，其中，所述导电沟道与所述源极、所述漏极相连接；
    在所述基板、源极、漏极、数据线上形成第二绝缘层；以及
    在所述第二绝缘层上沉积碳纳米管层，对所述碳纳米管层进行图案化处理，形成像素电极，所述像素电极通过通孔与所述漏极相连接。
  8. 根据权利要求 7 所述的柔性阵列基板的制作方法，其中，所述基板为透明玻璃基板或塑料基板。
  9. 根据权利要求 7 所述的柔性阵列基板的制作方法，其中，所述第一绝缘层包括第三绝缘层以及位于所述第三绝缘层上的第四绝缘层，其中，所述第三绝缘层采用的材料为有机树脂，所述第四绝缘层采用的材料为氧化物、氮化物或氮氧化合物。
  10. 根据权利要求 9 所述的柔性阵列基板的制作方法，其中，所述金属氧化物半导体层的厚度介于 50 埃 -2000 埃之间。
  11. 根据权利要求 7 所述的柔性阵列基板的制作方法，其中，所述第二绝缘层的材料为有机树脂。
  12. 根据权利要求 11 所述的柔性阵列基板的制作方法，其中，所述第二绝缘层的厚度介于 4000 埃 -30000 埃之间。
  13. 根据权利要求 7 所述的柔性阵列基板的制作方法，其中，所述金属氧化物半导体层为非晶铟镓锌氧化物。
  14. 根据权利要求 7 所述的柔性阵列基板的制作方法，其中，可通过化学气相沉积法或旋涂法沉积所述第一石墨烯层和所述第二石墨烯层。
  15. 一种柔性阵列基板，其包括：基板、设置在所述基板上的栅极和扫描线、设置在所述栅极和扫描线上的第一绝缘层、设置在所述第一绝缘层上的导电沟道、设置在所述导电沟道上的源极、漏极和数据线、设置在所述源极、漏极和数据线上的第二绝缘层、及设置在所述第二绝缘层上的像素电极，且所述导电沟道与所述源极、所述漏极连接，所述像素电极通过通孔与所述漏极相连接；其中，
    所述栅极和扫描线经第一石墨烯层图案化处理后形成；所述导电沟道经金属氧化物半导体层图案化处理形成；所述源极、漏极和数据线经第二石墨烯层图案化处理形成；所述像素电极经碳纳米管层图案化处理形成。
  16. 根据权利要求 15 所述的柔性阵列基板，其中，所述基板为透明玻璃基板或塑料基板。
  17. 根据权利要求 15 所述的柔性阵列基板，其中，所述第一绝缘层包括第三绝缘层以及位于所述第三绝缘层上的第四绝缘层，其中，所述第三绝缘层采用的材料为有机树脂，所述第四绝缘层采用的材料为氧化物、氮化物或氮氧化合物。
  18. 根据权利要求 17 所述的柔性阵列基板，其中，所述金属氧化物半导体层的厚度介于 50 埃 -2000 埃之间。
  19. 根据权利要求 15 所述的柔性阵列基板，其中，所述第二绝缘层的材料为有机树脂。
  20. 根据权利要求 19 所述的柔性阵列基板，其中，所述第二绝缘层的厚度介于 4000 埃 -30000 埃之间。
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