WO2013139040A1 - 液晶显示面板以及其制造方法 - Google Patents

液晶显示面板以及其制造方法 Download PDF

Info

Publication number
WO2013139040A1
WO2013139040A1 PCT/CN2012/072962 CN2012072962W WO2013139040A1 WO 2013139040 A1 WO2013139040 A1 WO 2013139040A1 CN 2012072962 W CN2012072962 W CN 2012072962W WO 2013139040 A1 WO2013139040 A1 WO 2013139040A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
pixel electrode
opening
thin film
film transistor
Prior art date
Application number
PCT/CN2012/072962
Other languages
English (en)
French (fr)
Inventor
姜佳丽
杜鹏
林师勤
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/502,742 priority Critical patent/US20150009441A1/en
Publication of WO2013139040A1 publication Critical patent/WO2013139040A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance

Definitions

  • the present invention relates to a liquid crystal display panel and a method of fabricating the same, and, in particular, to a liquid crystal display panel capable of reducing a parasitic capacitance value and a method of fabricating the same.
  • LCD monitors have become widely used in a variety of electronic devices such as televisions, mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook screens.
  • PDAs personal digital assistants
  • a display with a high resolution color screen is a display with a high resolution color screen.
  • Thin film transistor liquid crystal displays have gradually become the mainstream in the market due to their high image quality, good space utilization efficiency, low power consumption, and no radiation. At present, the market's performance requirements for liquid crystal displays are toward high contrast (High Contrast Ratio), fast response and large viewing angle.
  • FIG. 1 is a design diagram of a CS07 pixel capable of reducing color shift.
  • the CS07 pixel 10 employs a design of two sub-pixel electrodes 11, 12.
  • the wires of the transistor 14 of the conventional CS07 pixel 10 and the two sub-pixel electrodes 11, 12 form a parasitic capacitance Cgs_main, Cgs_sub, Cgs_cx between the scanning line 15 and the control voltage line 16. So if you design a pixel design that reduces parasitic capacitance, the signal-driven RC delay can be reduced.
  • An object of the present invention is to provide a liquid crystal display panel and a method of fabricating the same, in which a scan line and a control voltage line are disposed between a first sub-pixel electrode and a second sub-pixel electrode, because the transparent conductive layer of the present invention is used as a scan
  • the first metal layer of the line is separated by an insulating layer and a protective layer, and the conventional transparent conductive layer and the second metal layer as the data line are separated only by an insulating layer, so the wire and the scanning line and the control voltage of the present invention
  • the parasitic capacitance formed by the line is small, which reduces the RC delay.
  • a liquid crystal display panel includes a glass substrate and a thin film transistor, the thin film transistor including a gate, a source, and a drain;
  • the display panel further includes: a first sub-pixel electrode and a second sub-pixel electrode electrically connected to the thin film transistor, and each of the thin film transistors is formed of a transparent conductive layer;
  • a scan line is formed by a first metal layer and located at the On the glass substrate, the scan line is coupled to the gate of the thin film transistor and used to transmit a scan signal;
  • a control voltage line is formed by the first metal layer and located on the glass substrate.
  • the first sub-pixel electrode is electrically connected to the drain of the thin film transistor through the first opening, and the second sub-pixel electrode passes through the second opening Electrically connected to the drain of the thin film transistor.
  • the thin film transistor further includes a first wire, a second wire and a third wire, the source is directly connected to the data line through the first wire, and the drain passes The second wire and the first opening are directly connected to the first sub-pixel electrode, and the drain is directly connected to the second sub-pixel electrode through the third wire and the second opening.
  • the first opening and the second opening are projected on the glass substrate at a position where the scan line and the control voltage line are projected on the glass substrate. between.
  • the material of the transparent conductive layer is indium tin oxide.
  • the thin film transistor, the scan line and the control voltage line are located between the first sub-pixel electrode and the second sub-pixel electrode.
  • the invention further discloses a flat display panel, a method for manufacturing a liquid crystal display panel, the manufacturing method comprising: providing a glass substrate; forming a first metal layer on the glass substrate; etching the first metal layer Forming a gate of a thin film transistor, a control voltage line, and a scan line; forming an insulating layer on a gate of the first thin film transistor, the control voltage line, and the scan line; forming a second a metal layer, and etching the second metal layer to form a source and a drain of the thin film transistor and a data line; forming a protective layer over the second metal layer; etching the protective layer to form a first opening and a second opening, wherein the first opening and the second opening are both located between the scan line and the control voltage line; forming a transparent conductive layer and etching The transparent conductive layer is formed to form a first sub-pixel electrode and a second sub-pixel electrode, wherein the first sub-pixel electrode is electrically connected to the drain of the thin film transistor through
  • a first wire, a second wire and a third wire are simultaneously formed, so that the transparent conductive layer is etched to form the first The sub-pixel electrode and the second sub-pixel electrode, the source is directly connected to the data line through the first wire, and the drain is directly connected through the second wire and the first opening The first sub-pixel electrode is directly connected to the second sub-pixel electrode through the third wire and the second opening.
  • the first opening and the second opening are projected on the glass substrate at a position where the scan line and the control voltage line are projected on the glass substrate. between.
  • the material of the transparent conductive layer is indium tin oxide.
  • the thin film transistor, the scan line and the control voltage line are located between the first sub-pixel electrode and the second sub-pixel electrode.
  • the liquid crystal display panel of the present invention Compared with the prior art, the liquid crystal display panel of the present invention and a method of fabricating the same, the first opening for connecting the drains of the first sub-pixel electrode and the thin film transistor, and the second sub-pixel electrode and the A second opening of the drain of the thin film transistor is disposed between the scan line and the control voltage line.
  • the wires crossing the scan line and the control voltage line are transparent conductive layers as the first sub-pixel electrode and the second sub-pixel electrode.
  • the prior art wires that span the scan line and the control voltage line are the second metal layer that serves as the data line.
  • the transparent conductive layer of the present invention is separated from the first metal layer as a scan line by an insulating layer and a protective layer, and the conventional transparent conductive layer and the second metal layer as a data line are separated by an insulating layer. Therefore, the parasitic capacitance formed by the wire of the present invention and the scanning line and the control voltage line is small, and the RC delay can be reduced.
  • Figure 1 is a design diagram of a CS07 pixel that can reduce color shift.
  • FIG. 2 is a simplified schematic view of a liquid crystal display panel of the present invention.
  • 3 to 6 are schematic views showing a method of forming a flat display panel of the present invention.
  • FIG. 2 is a simplified schematic diagram of the liquid crystal display panel 300 of the present invention.
  • the liquid crystal display panel 300 includes a plurality of data lines, a plurality of scanning lines, a plurality of control voltage lines, a plurality of thin film transistors, and a plurality of pixel units.
  • Each of the thin film transistors is electrically connected to a scan line and a data line, and each of the pixel units includes a first sub-pixel electrode 331 and a second sub-pixel electrode 332.
  • the data line 302 the scan line 301, the control voltage line 307, and the thin film transistor 303 are shown.
  • the gate of the thin film transistor 303 is coupled to the scan line 301, and the source of the thin film transistor 303 is coupled to the data line 302.
  • the drain of the thin film transistor 303 is coupled to the first sub-pixel electrode 331 and the second sub-pixel electrode 332.
  • Control voltage line 307 is used to provide a control signal.
  • the driving method of the liquid crystal display panel 300 is as follows: a scan signal output from a gate driver (not shown) is input through the scan line 301, so that the thin film transistors 303 connected to the scan lines 301 are sequentially turned on, and the source driver (not shown) And outputting a corresponding data signal, which is input to the thin film transistor 303 through the data line 302, and the thin film transistor 303 transmits the data signal to the first sub-pixel electrode 331 and the second sub-pixel electrode 332 to be charged to a desired voltage. .
  • the liquid crystal above the first sub-pixel electrode 331 and the second sub-pixel electrode 332 is twisted according to the voltage difference of the data signal, thereby displaying different gray scales.
  • the gate driver outputs a scan signal row by row through a plurality of scan lines to turn on the thin film transistor 303 of each row, and then the first sub-pixel electrode 331 and the second sub-pixel electrode 332 of each row are charged by the source driver. Discharge. In this way, the complete display of the liquid crystal display panel 300 can be completed.
  • FIG. 3 to FIG. 6 are schematic diagrams showing a method of forming the liquid crystal display panel 300 of the present invention.
  • a glass substrate 350 is provided as a lower substrate, and then a metal thin film deposition process is performed to form a first metal layer (not shown) on the surface of the glass substrate 350, and a first mask is used.
  • the film is subjected to a first lithography etching to etch the gate 371 of the thin film transistor 303, the control voltage line 307, and the scan line 301.
  • the gate 371 is substantially a portion of the scan line 301.
  • an insulating layer 351 made of silicon nitride (SiNx) is deposited to cover the gate electrode 371, the control voltage line 307, and the scan line 301. Continuous deposition of amorphous silicon on the insulating layer 351 (a-Si, Amorphous) Si) layer and a high electron doping concentration of N+ amorphous silicon layer. And then an amorphous silicon layer and a high electron doping concentration of N+ The amorphous silicon layer is covered with a second metal layer (not shown).
  • the semiconductor layer 372 includes an amorphous silicon layer 372a as a channel of the thin film transistor 303 and an ohmic contact layer for reducing impedance (Ohmic) Contact Layer) 372b.
  • the data line 302 is connected to the source 373 through the first wire 381, and the second wire 382 and the third wire 383 are connected to the drain 374 of the thin film transistor 303.
  • FIG. 4 does not identify data line 302, those skilled in the art will appreciate that source 373 is substantially part of data line 302.
  • the structure of FIG. 4 is to simultaneously etch the amorphous silicon layer with a second mask, N+ An amorphous silicon layer and a second metal layer.
  • an amorphous silicon layer and an N+ amorphous silicon layer may be formed on the insulating layer 351, and the amorphous silicon layer is first etched by the second mask, N+.
  • An amorphous silicon layer is formed to form the semiconductor layer 372; thereafter, a second metal layer is formed over the semiconductor layer 372 and the insulating layer 351, and the second metal layer is etched by another mask to form a source 373 and a drain of the thin film transistor 303.
  • FIG. 5 Please refer to Figure 5, followed by deposition of a protective layer of silicon nitride (passivation) Layer 375, and covering source 373, drain 374 and data line 302, and then using a third mask for third lithography etching to remove a portion of the protective layer 375 over the drain 374 until the drain 374
  • the surface is such that a first opening (Via) 531 and a second opening 532 are formed above the drain 374.
  • the first opening 531 and the second opening 532 are projected on the glass substrate 350 at a position where the scanning line 301 / the control voltage line 307 is projected on the glass substrate 350 (see FIG. 2).
  • FIG. 6 is also a cross-sectional view of the liquid crystal display panel 300 shown in FIG. 2 along the line segment A-A'.
  • Indium tin is formed on the protective layer 375
  • the oxide, ITO is a transparent conductive layer of the material, and then the transparent conductive layer is etched by a fourth mask to form the first sub-pixel electrode 331 and the second sub-pixel electrode 332.
  • the first sub-pixel electrode 331 is electrically connected to the second wire 382 and the drain 374 of the thin film transistor 303 through the first opening 531 formed in advance.
  • the second sub-pixel electrode 332 is electrically connected to the third wire 383 and the drain 374 of the thin film transistor 303 through the second opening 532 formed in advance.
  • the first opening 531 and the second opening 532 of the liquid crystal display panel 300 of the present embodiment are projected on the glass substrate 350 , and the scanning line 301 and the control voltage line 307 are projected on the glass substrate 350 .
  • the parasitic capacitances Cgs_main, Cgs_sub, Cgs_cx between the second wire 382 and the third wire 383 and the scanning line 301/control voltage line 307 are also relatively small. According to the test, the parasitic capacitance Cgs_sub is reduced by about 3.9%, the parasitic capacitance Cgs_main is reduced by about 32.7%, and the parasitic capacitance Cgs_cx is reduced by about 3.9%.
  • the second wire 382 and the third wire 383 are composed of a transparent conductive layer made of indium tin oxide, and the second wire 382 and the third wire 383 and the scanning line 301 / control voltage line 307 (ie, the first The metal layer is separated by an insulating layer 351 and a protective layer 375. Since the capacitance value is inversely proportional to the distance between the two conductors, the parasitic capacitance formed by the second wire 382 and the third wire 383 and the scanning line 301 / control voltage line 307 is smaller than the prior art parasitic capacitance shown in FIG.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种液晶显示面板（300）和其制造方法，在第一子像素电极（331）及第二子像素电极（332）之间设置有扫描线（301）和控制电压线（307）。将用于连接第一子像素电极（331）和薄膜晶体管（303）的漏极（374）的第一开孔（531），以及用于连接第二子像素电极（332）和该薄膜晶体管（303）的漏极（374）的第二开孔（532），都设置在该扫描线（301）和该控制电压线（307）之间。如此，跨越该扫描线（301）和该控制电压线（307）的导线就是作为第一子像素电极（331）和第二子像素电极（332）的透明导电层，而非作为数据线（302）的第二金属层。因为透明导电层与作为扫描线（301）的第一金属层之间隔着绝缘层（351）和保护层（375），相对于传统的透明导电层与做为数据线的第二金属层之间只隔着绝缘层，透明导电层与扫描线（301）和控制电压线（307）所形成的寄生电容较小，可降低RC延迟。

Description

液晶显示面板以及其制造方法 技术领域
本发明涉及一种液晶显示面板以及其制造方法，特别是涉及一种可以降低寄生电容值的液晶显示面板以及其制造方法。
 背景技术
功能先进的显示器渐成为现今消费电子产品的重要特色，其中液晶显示器已经逐渐成为各种电子设备如电视、行动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记型计算机屏幕所广泛应用具有高分辨率彩色屏幕的显示器。
薄膜晶体管液晶显示器由于具有高画质、空间利用效率佳、低消耗功率、无辐射等优越特性，因而已逐渐成为市场之主流。目前，市场对于液晶显示器的性能要求是朝向高对比度(High Contrast Ratio)、快速反应与大视角等特性。
但是当使用者在大视角下观看液晶面板时，画面显示的色彩会偏离其原本应该呈现出来的色彩，而使观看到的画面失真。为了解决降低色偏的影响，目前有许多种类的像素结构被开发出来。请参阅图1，图1是一种可以降低色偏的CS07像素的设计图。CS07像素10采用了两子像素电极11、12的设计。但是传统的CS07像素10的晶体管14与两子像素电极11、12连接的导线会在扫描线15和控制电压线16之间形成寄生电容Cgs_main、Cgs_sub、Cgs_cx。因此如果设计一种减少寄生电容的像素设计，那么信号驱动的RC延迟也可以减少。
 技术问题
本发明的目的是提供一种液晶显示面板和其制造方法，在第一子像素电极及第二子像素电极之间设置有扫描线和控制电压线，因为本发明的透明导电层与做为扫描线的第一金属层之间隔着绝缘层和保护层，而传统的透明导电层与做为数据线的第二金属层之间只隔着绝缘层，所以本发明的导线与扫描线和控制电压线所形成的寄生电容较小，可降低RC延迟。以解决现有技术的问题。
 技术解决方案
根据本发明的实施例，本发明揭露一种液晶显示面板，所述液晶显示面板包括一玻璃基板以及一薄膜晶体管，所述薄膜晶体管包含一栅极、一源极以及一漏极；所述液晶显示面板另包含：一第一子像素电极以及一第二子像素电极，电性连接所述薄膜晶体管，且皆由一透明导电层构成；一扫描线，由一第一金属层构成且位于所述玻璃基板上，所述扫描线耦接至所述薄膜晶体管的所述栅极并用于传输一扫描信号；一控制电压线，由所述第一金属层构成且位于所述玻璃基板上，用来传输一控制信号；一绝缘层，位于所述扫描线和所述控制电压线之上；一数据线，由一第二金属层构成且位于所述绝缘层之上，耦接于所述薄膜晶体管的所述源极；一保护层，位于所述第二金属层之上；以及一第一开孔和一第二开孔，皆开设于所述保护层中，且位在所述扫描线和所述控制电压线之间，使得所述第一子像素电极通过所述第一开孔与所述薄膜晶体管的漏极电性连接，以及所述第二子像素电极通过所述第二开孔与所述薄膜晶体管的漏极电性连接。
根据本发明的实施例，所述薄膜晶体管另包含一第一导线、一第二导线及一第三导线，所述源极通过所述第一导线直接连接所述数据线，所述漏极通过所述第二导线和所述第一开孔直接连接所述第一子像素电极，所述漏极通过所述第三导线和所述第二开孔直接连接所述第二子像素电极。
根据本发明的实施例，所述第一开孔和所述第二开孔投射于所述玻璃基板上的位置，位于所述扫描线和所述控制电压线投射于所述玻璃基板的位置之间。
根据本发明的实施例，所述透明导电层的材料是氧化铟锡。
根据本发明的实施例，所述薄膜晶体管、所述扫描线和所述控制电压线位于所述第一子像素电极以及所述第二子像素电极之间。
本发明又揭露一种平面显示面板，一种液晶显示面板的制造方法，所述制造方法包含：提供一玻璃基板；形成一第一金属层于所述玻璃基板上；蚀刻所述第一金属层，以形成一薄膜晶体管的栅极、一控制电压线以及一扫描线；在所述第一薄膜晶体管的栅极、所述控制电压线以及所述扫描线上形成一绝缘层；形成一第二金属层，并蚀刻所述第二金属层，以形成所述薄膜晶体管的源极和漏极以及一数据线；形成一保护层于所述第二金属层之上；蚀刻所述保护层以形成一第一开孔和一第二开孔，其中所述第一开孔和所述第二开孔皆位在所述扫描线和所述控制电压线之间；形成一透明导电层，并蚀刻所述透明导电层以形成一第一子像素电极以及一第二子像素电极，其中所述第一子像素电极通过所述第一开孔与所述薄膜晶体管的漏极电性连接，以及所述第二子像素电极通过所述第二开孔与所述薄膜晶体管的漏极电性连接。
根据本发明的实施例，在蚀刻所述第二金属层的步骤时，同时形成一第一导线、一第二导线及一第三导线，使得在蚀刻所述透明导电层以形成所述第一子像素电极以及所述第二子像素电极时，所述源极通过所述第一导线直接连接所述数据线，所述漏极通过所述第二导线和所述第一开孔直接连接所述第一子像素电极，所述漏极通过所述第三导线和所述第二开孔直接连接所述第二子像素电极。
根据本发明的实施例，所述第一开孔和所述第二开孔投射于所述玻璃基板上的位置，位于所述扫描线和所述控制电压线投射于所述玻璃基板的位置之间。
根据本发明的实施例，所述透明导电层的材料是氧化铟锡。
根据本发明的实施例，所述薄膜晶体管、所述扫描线和所述控制电压线位于所述第一子像素电极以及所述第二子像素电极之间。
 有益效果
相较于现有技术，本发明的液晶显示面板以及其制造方法将用于连接第一子像素电极和薄膜晶体管的漏极的第一开孔，以及用于连接第二子像素电极和所述薄膜晶体管的漏极的第二开孔，都设置在扫描线和控制电压线之间。另外，跨越所述扫描线和所述控制电压线的导线就是做为第一子像素电极和第二子像素电极的透明导电层。相较之下，现有技术跨越该扫描线和该控制电压线的导线是做为数据线的第二金属层。因为导线和其所跨越的扫描线和控制电压线之间会形成寄生电容效应，所以导线和其所跨越的扫描线和控制电压线的距离越远，则寄生电容越小。因为本发明的透明导电层与做为扫描线的第一金属层之间隔着绝缘层和保护层，而传统的透明导电层与做为数据线的第二金属层之间只隔着绝缘层，所以本发明的导线与扫描线和控制电压线所形成的寄生电容较小，可降低RC延迟。
 附图说明
图1是一种可以降低色偏的CS07像素的设计图。
图2是本发明液晶显示面板的简易示意图。
图3至图6为形成本发明平面显示面板的方法示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施之特定实施例。本发明所提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”、“顶”、“底”、“水平”、“垂直”等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参阅图2，图2是本发明液晶显示面板300的简易示意图。液晶显示面板300包含数条数据线、数条扫描线、数条控制电压线、数个薄膜晶体管和数个像素单元。每一薄膜晶体管电性连接一扫描线和一数据线，每一像素单元包含一第一子像素电极331以及一第二子像素电极332。为简化图式，在以下实施例中，仅绘示数据线302、扫描线301、控制电压线307及薄膜晶体管303。薄膜晶体管303的栅极耦接到扫描线301，薄膜晶体管303的源极则耦接至数据线302。此外，薄膜晶体管303的漏极耦接至第一子像素电极331以及第二子像素电极332。控制电压线307用来提供一控制信号。
液晶显示面板300的驱动方式如下所述：栅极驱动器(图未示)输出的扫描信号通过扫描线301输入，使得连接扫描线301的薄膜晶体管303依序开启，同时源极驱动器(未图示)则输出对应的数据信号，通过数据线302输入至薄膜晶体管303，而薄膜晶体管303则将数据信号传递至第一子像素电极331以及第二子像素电极332，使其充电到所需的电压。第一子像素电极331以及第二子像素电极332上方的液晶就是依据该数据信号的电压差扭转(twist)，进而显示出不同的灰阶。栅极驱动器会通过数条扫描线一行接一行地输出扫描信号以将每一行的薄膜晶体管303打开，再由源极驱动器对每一行的第一子像素电极331以及第二子像素电极332进行充放电。如此依序下去，便可完成液晶显示面板300的完整显示。
在以下的揭露之中，将解说本发明液晶显示面板300的制程方式。在此请参阅图3至图6，图3至图6为形成本发明液晶显示面板300的方法示意图。
在此请先参阅图3，首先提供一个玻璃基板350当作下基板，接着进行一金属薄膜沉积制程，以于玻璃基板350表面形成一第一金属层（未显示），并利用一第一掩膜来进行第一微影蚀刻，以蚀刻得到薄膜晶体管303的栅极371、控制电压线307以及扫描线301。本领域的技术人员可以了解栅极371实质上是扫描线301的一部分。
接着请参阅图2和图4，接着沉积以氮化硅(SiNx)为材质的绝缘层351而覆盖栅极371、控制电压线307以及扫描线301。于绝缘层351上连续沉积非晶硅(a－Si，Amorphous Si)层以及一高电子掺杂浓度的N+ 非晶硅层。再于非晶硅层以及一高电子掺杂浓度的N+ 非晶硅层上覆盖第二金属层(未绘示于图中)。接着利用第二掩膜以蚀刻非晶硅层以及N+ 非晶硅层以构成半导体层372，同时蚀刻该第二金属层以形成薄膜晶体管303的源极373、漏极374、第一导线381(绘示于图2)、第二导线382、第三导线383以及数据线302(绘示于图2)。半导体层372包含作为薄膜晶体管303通道的非晶硅层372a以及用来降低阻抗的欧姆接触层(Ohmic contact layer)372b。数据线302是通过第一导线381连接到源极373，第二导线382和第三导线383则连接到薄膜晶体管303的漏极374。虽然图4并未标示出数据线302，但本领域的技术人员可以了解源极373实质上是数据线302的一部分。
除此之外，在本实施例中，图4的结构是用第二掩膜同时蚀刻非晶硅层、N+ 非晶硅层和第二金属层。另一实施例中，可以先形成非晶硅层、N+ 非晶硅层于绝缘层351之上，先以第二掩膜蚀刻非晶硅层、N+ 非晶硅层以形成半导体层372；之后，形成第二金属层于半导体层372和绝缘层351之上，以另一掩膜蚀刻该第二金属层以形成薄膜晶体管303的源极373、漏极374以及数据线302。
请参阅图5，接着沉积以氮化硅为材质的保护层(passivation layer)375，并覆盖源极373、及漏极374和数据线302，再利用第三掩膜来进行第三微影蚀刻用以去除漏极374上方的部份保护层375，直至漏极374表面，以于漏极374上方形成第一开孔(Via)531和第二开孔532。第一开孔531和第二开孔532投射于玻璃基板350上的位置，位于扫描线301/控制电压线307投射于玻璃基板350的位置之间(请参见图2)。
请参阅图6，图6也是图2所示的液晶显示面板300沿线段A-A’的剖面图。在保护层375上形成以氧化铟锡物(Indium tin oxide，ITO)为材质的透明导电层，接着利用一第四掩膜蚀刻该透明导电层以形成第一子像素电极331和第二子像素电极332。第一子像素电极331通过预先形成的第一开孔531与第二导线382和薄膜晶体管303的漏极374电性连接。第二子像素电极332通过预先形成的第二开孔532与第三导线383和薄膜晶体管303的漏极374电性连接。
如图2所示，本实施例的液晶显示面板300的第一开孔531和第二开孔532投射于玻璃基板350上的位置，是位于扫描线301和控制电压线307投射于玻璃基板350的位置之间。而且第二导线382和第三导线383与扫描线301/控制电压线307之间的寄生电容Cgs_main、Cgs_sub、Cgs_cx也会比较小。根据测试，寄生电容Cgs_sub减少约3.9%、寄生电容Cgs_main减少约32.7%、寄生电容Cgs_cx减少约3.9%。这是因为第二导线382和第三导线383是由氧化铟锡物为材质的透明导电层构成，且第二导线382和第三导线383与扫描线301/控制电压线307(亦即第一金属层)之间隔有绝缘层351和保护层375。由于电容值与两导电体的距离成反比，因此第二导线382和第三导线383与扫描线301/控制电压线307形成的寄生电容会比图1所示的现有技术的寄生电容小。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
序列表自由内容

Claims (10)

  1. 一种液晶显示面板，其包含：
    一玻璃基板；
    一薄膜晶体管，包含一栅极、一源极以及一漏极；
    一第一子像素电极以及一第二子像素电极，电性连接所述薄膜晶体管，且皆由一透明导电层构成；
    一扫描线，由一第一金属层构成且位于所述玻璃基板上，所述扫描线耦接至所述薄膜晶体管的所述栅极并用于传输一扫描信号；
    一控制电压线，由所述第一金属层构成且位于所述玻璃基板上，用来传输一控制信号；
    一绝缘层，位于所述扫描线和所述控制电压线之上；
    一数据线，由一第二金属层构成且位于所述绝缘层之上，耦接于所述薄膜晶体管的所述源极；
    一保护层，位于所述第二金属层之上；以及
    一第一开孔和一第二开孔，皆开设于所述保护层中，且位在所述扫描线和所述控制电压线之间，使得所述第一子像素电极通过所述第一开孔与所述薄膜晶体管的漏极电性连接，以及所述第二子像素电极通过所述第二开孔与所述薄膜晶体管的漏极电性连接。
  2. 根据权利要求1所述的液晶显示面板，其中所述薄膜晶体管另包含一第一导线、一第二导线及一第三导线，所述源极通过所述第一导线直接连接所述数据线，所述漏极通过所述第二导线和所述第一开孔直接连接所述第一子像素电极，所述漏极通过所述第三导线和所述第二开孔直接连接所述第二子像素电极。
  3. 根据权利要求2所述的液晶显示面板，其中所述第一开孔和所述第二开孔投射于所述玻璃基板上的位置，位于所述扫描线和所述控制电压线投射于所述玻璃基板的位置之间。
  4. 根据权利要求1所述的液晶显示面板，其中所述透明导电层的材料是氧化铟锡。
  5. 根据权利要求1所述的液晶显示面板，其中所述薄膜晶体管、所述扫描线和所述控制电压线位于所述第一子像素电极以及所述第二子像素电极之间。
  6. 一种液晶显示面板的制造方法，其包含：
    提供一玻璃基板；
    形成一第一金属层于所述玻璃基板上；
    蚀刻所述第一金属层，以形成一薄膜晶体管的栅极、一控制电压线以及一扫描线；
    在所述第一薄膜晶体管的栅极、所述控制电压线以及所述扫描线上形成一绝缘层；
    形成一第二金属层，并蚀刻所述第二金属层，以形成所述薄膜晶体管的源极和漏极以及一数据线；
    形成一保护层于所述第二金属层之上；
    蚀刻所述保护层以形成一第一开孔和一第二开孔，所述第一开孔和所述第二开孔皆位在所述扫描线和所述控制电压线之间；
    形成一透明导电层，并蚀刻所述透明导电层以形成一第一子像素电极以及一第二子像素电极，其中所述第一子像素电极通过所述第一开孔与所述薄膜晶体管的漏极电性连接，以及所述第二子像素电极通过所述第二开孔与所述薄膜晶体管的漏极电性连接。
  7. 根据权利要求6所述的制造方法，其中在蚀刻所述第二金属层的步骤时，同时形成一第一导线、一第二导线及一第三导线，使得在蚀刻所述透明导电层以形成所述第一子像素电极以及所述第二子像素电极时，所述源极通过所述第一导线直接连接所述数据线，所述漏极通过所述第二导线和所述第一开孔直接连接所述第一子像素电极，所述漏极通过所述第三导线和所述第二开孔直接连接所述第二子像素电极。
  8. 根据权利要求6所述的制造方法，其中所述第一开孔和所述第二开孔投射于所述玻璃基板上的位置，位于所述扫描线和所述控制电压线投射于所述玻璃基板的位置之间。
  9. 根据权利要求6所述的制造方法，其中所述透明导电层的材料是氧化铟锡。
  10. 根据权利要求6所述的制造方法，其中所述薄膜晶体管、所述扫描线和所述控制电压线位于所述第一子像素电极以及所述第二子像素电极之间。
PCT/CN2012/072962 2012-03-22 2012-03-23 液晶显示面板以及其制造方法 WO2013139040A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/502,742 US20150009441A1 (en) 2012-03-22 2012-03-23 Lcd panel and a method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2012100789846A CN102608815A (zh) 2012-03-22 2012-03-22 液晶显示面板以及其制造方法
CN201210078984.6 2012-03-22

Publications (1)

Publication Number Publication Date
WO2013139040A1 true WO2013139040A1 (zh) 2013-09-26

Family

ID=46526292

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/072962 WO2013139040A1 (zh) 2012-03-22 2012-03-23 液晶显示面板以及其制造方法

Country Status (3)

Country Link
US (1) US20150009441A1 (zh)
CN (1) CN102608815A (zh)
WO (1) WO2013139040A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9025102B2 (en) 2012-10-22 2015-05-05 Shenzhen China Star Optoelectronics Technology Co., Ltd Drive circuit of liquid crystal panel
CN102879967B (zh) * 2012-10-22 2015-02-04 深圳市华星光电技术有限公司 液晶面板的驱动电路
CN104680994B (zh) * 2015-03-09 2017-09-15 深圳市华星光电技术有限公司 一种液晶显示器的驱动方法及驱动装置
KR102483956B1 (ko) 2016-03-31 2023-01-03 삼성디스플레이 주식회사 디스플레이 장치
US11889706B2 (en) * 2018-09-28 2024-01-30 Samsung Display Co., Ltd. Display device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1573479A (zh) * 2003-05-20 2005-02-02 三星电子株式会社 液晶显示器及其薄膜晶体管阵列板
CN101504503A (zh) * 2009-04-10 2009-08-12 友达光电股份有限公司 像素阵列、液晶显示面板以及光电装置
US20100253869A1 (en) * 2009-04-02 2010-10-07 Au Optronics Corporation Pixel array, liquid crystal display panel, and electro-optical apparatus
CN101958318A (zh) * 2009-07-14 2011-01-26 三星电子株式会社 显示面板和包括该显示面板的显示装置
CN102023420A (zh) * 2009-09-16 2011-04-20 三星电子株式会社 液晶显示器
CN102289117A (zh) * 2010-06-16 2011-12-21 三星电子株式会社 液晶显示器及其驱动方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4438665B2 (ja) * 2005-03-29 2010-03-24 シャープ株式会社 液晶表示装置
US8259249B2 (en) * 2009-10-12 2012-09-04 Samsung Electronics Co., Ltd. Display substrate, method of manufacturing the display substrate and display device having the display substrate
TWI424234B (zh) * 2009-10-26 2014-01-21 Au Optronics Corp 畫素陣列、聚合物穩定配向液晶顯示面板以及光電裝置
KR101833498B1 (ko) * 2010-10-29 2018-03-02 삼성디스플레이 주식회사 액정 표시 장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1573479A (zh) * 2003-05-20 2005-02-02 三星电子株式会社 液晶显示器及其薄膜晶体管阵列板
US20100253869A1 (en) * 2009-04-02 2010-10-07 Au Optronics Corporation Pixel array, liquid crystal display panel, and electro-optical apparatus
CN101504503A (zh) * 2009-04-10 2009-08-12 友达光电股份有限公司 像素阵列、液晶显示面板以及光电装置
CN101958318A (zh) * 2009-07-14 2011-01-26 三星电子株式会社 显示面板和包括该显示面板的显示装置
CN102023420A (zh) * 2009-09-16 2011-04-20 三星电子株式会社 液晶显示器
CN102289117A (zh) * 2010-06-16 2011-12-21 三星电子株式会社 液晶显示器及其驱动方法

Also Published As

Publication number Publication date
CN102608815A (zh) 2012-07-25
US20150009441A1 (en) 2015-01-08

Similar Documents

Publication Publication Date Title
US9659978B2 (en) Array substrate, method for manufacturing the same, and display device
WO2013086746A1 (zh) 液晶显示面板以及其制造方式
US10217778B2 (en) Array substrate and manufacturing method thereof
JP6370003B2 (ja) 画素構造及びその製造方法
WO2012136010A1 (zh) 芯片扇出设计、其形成方法及使用所述设计的液晶显示器
TWI532154B (zh) 顯示面板及顯示裝置
WO2013056460A1 (zh) 液晶显示面板及形成液晶显示面板的方法
TWI676837B (zh) 畫素陣列基板
WO2013139040A1 (zh) 液晶显示面板以及其制造方法
TWI388014B (zh) 薄膜電晶體之製造方法
US10381384B2 (en) Array substrate, method for manufacturing array substrate, display panel and display device
CN108732840A (zh) 阵列基板及其制作方法
KR101689462B1 (ko) 디스플레이 장치
WO2013143064A1 (zh) 液晶显示面板以及其制造方法
US20130161612A1 (en) Display device and image display system employing the same
US20140175448A1 (en) Array substrate, manufacturing method thereof and display device
TWI656386B (zh) 顯示裝置及其形成方法
TW201743118A (zh) 顯示面板
US11107842B2 (en) Pixel array substrate
TWI695367B (zh) 畫素陣列基板
TW201901267A (zh) 陣列基板及液晶顯示面板
WO2013063814A1 (zh) 液晶显示面板及其制造方法
US7847875B2 (en) Anti-interference wiring assembly for liquid crystal display device and method for reducing interference
CN221201180U (zh) 一种边缘器件区优化设计的tft阵列基板
CN113690257B (zh) 阵列基板及其制作方法和显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12871699

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12871699

Country of ref document: EP

Kind code of ref document: A1