WO2013063814A1 - 液晶显示面板及其制造方法 - Google Patents

液晶显示面板及其制造方法 Download PDF

Info

Publication number
WO2013063814A1
WO2013063814A1 PCT/CN2011/081845 CN2011081845W WO2013063814A1 WO 2013063814 A1 WO2013063814 A1 WO 2013063814A1 CN 2011081845 W CN2011081845 W CN 2011081845W WO 2013063814 A1 WO2013063814 A1 WO 2013063814A1
Authority
WO
WIPO (PCT)
Prior art keywords
display panel
data line
liquid crystal
crystal display
layer
Prior art date
Application number
PCT/CN2011/081845
Other languages
English (en)
French (fr)
Inventor
陈虹瑞
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/379,568 priority Critical patent/US20130106679A1/en
Publication of WO2013063814A1 publication Critical patent/WO2013063814A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G02F2201/501—Blocking layers, e.g. against migration of ions
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/103—Materials and properties semiconductor a-Si

Definitions

  • the present invention relates to a liquid crystal display panel and a method of fabricating the same, and more particularly to an amorphous silicon layer between a data line and a scan line to enhance the insulation effect between the data line and the scan line.
  • a liquid crystal display panel that avoids leakage between a data line and a scan line and a method of manufacturing the same.
  • a liquid crystal display panel of a conventional liquid crystal display includes a plurality of pixels, and each pixel includes three pixel units respectively representing three primary colors of red, green and blue (RGB).
  • the scan signal outputted by the gate driver is input through the scan line, the thin film transistors of the pixel units of each row are sequentially turned on, and the source driver outputs a corresponding data signal, which is input to the thin film transistor through the data line, and the thin film transistor is
  • the data signals are passed to the pixel electrodes, causing them to be charged to their respective desired voltages, thereby causing the pixels to exhibit different gray levels.
  • the gate driver outputs the scan signals row by row to turn on the thin film transistors of the pixel cells of each row, and then the source drivers charge and discharge the pixel electrodes of each row. In this way, the complete display of the liquid crystal display panel can be completed.
  • the present invention provides a liquid crystal display panel and a method of fabricating the same, in which an overlap region between a data line and a scan line is insulated by an insulating layer between the data line and the scan line, and the insulating layer is An amorphous silicon layer is additionally formed between the data lines to enhance the insulation between the data lines and the scan lines, thereby reducing the leakage current.
  • a liquid crystal display panel includes a glass substrate and a thin film transistor, the thin film transistor including a gate, a source, and a drain;
  • the display panel further includes: a scan line on the glass substrate, the scan line is coupled to the gate of the thin film transistor; an insulating layer is located above the scan line; a data line is located The insulating layer is coupled to the source of the thin film transistor, wherein the data line and the scan line overlap a coincident region; and a semiconductor layer is located at the gate insulating layer and Between the data lines, a position of the semiconductor layer corresponds to the overlapping area, and an area of the semiconductor layer is larger than the overlapping area to strengthen between the data line and the scan line by the semiconductor layer Insulation effect.
  • the present invention further provides a method for fabricating a liquid crystal display panel, comprising the steps of: providing a glass substrate; forming a first metal layer on the glass substrate; and etching the first metal a layer to form a gate of a thin film transistor and a scan line; forming an insulating layer on the gate of the first thin film transistor and the scan line; forming a semiconductor layer on the insulating layer; etching the semiconductor a layer to form a channel region of the thin film transistor and a first region; and forming a second metal layer, and etching the second metal layer to form a source and a drain of the thin film transistor, and a data a line; wherein the data line and the scan line overlap with a coincident region, the coincident region corresponds to a position of the first region, and an area of the first region is larger than the coincident region.
  • the semiconductor layer is an amorphous silicon layer, and the semiconductor layer further comprises a high electron doping concentration of N+ Amorphous silicon layer.
  • a distance between one side of the first region and the data line and the scan line is greater than 1.5 micrometers ( ⁇ m)
  • the liquid crystal display panel of the present invention and the manufacturing method thereof are in the overlap region of the data line and the scan line, except that a gate insulating layer is used to insulate between the data line and the scan line, and the gate is insulated from the gate and the scan line.
  • An amorphous silicon layer is additionally formed between the pole insulating layer and the data line to enhance the insulation effect between the data line and the scan line, thereby reducing the leakage condition.
  • the present invention can achieve the foregoing structure without increasing the mask process. Therefore, the liquid crystal display panel of the present invention and the method of manufacturing the same can effectively reduce the leakage of the data lines and the scan lines without additional cost.
  • FIG. 1 is a simplified schematic view of a liquid crystal display panel of the present invention.
  • FIG. 2 is a schematic structural view of the liquid crystal display panel of FIG. 1.
  • FIG. 3 to FIG. 6 are schematic diagrams showing the manufacturing process of the liquid crystal display panel of the present invention.
  • FIG. 1 is a simplified schematic diagram of a liquid crystal display panel 100 of the present invention.
  • the liquid crystal display panel 100 includes a plurality of data lines, a plurality of scanning lines, and a plurality of common voltage lines (Common Line), several thin film transistors and several pixel electrodes.
  • Each thin film transistor is electrically connected to a scan line and a data line.
  • the gate of the thin film transistor 120 is coupled to the scan line 111, and the source of the thin film transistor 120 is coupled to the data line 101.
  • the drain of the thin film transistor 120 is coupled to the pixel electrode 130.
  • the common voltage line 105 is used to provide a common voltage signal.
  • the driving manner of the liquid crystal display panel 100 is as follows: a scan signal output from a gate driver (not shown) is input through the scan line 111, so that the thin film transistors 120 connected to the scan lines 111 are sequentially turned on, and the source driver (not shown) Then, the corresponding data signal is output, input to the thin film transistor 120 through the data line 101, and the thin film transistor 120 transmits the data signal to the pixel electrode 130 to be charged to a desired voltage.
  • the liquid crystal above the pixel electrode 130 is twisted according to the voltage difference between the data signal and the common voltage signal supplied from the common voltage line 105, thereby displaying different gray levels.
  • the gate driver outputs a scan signal one by one through a plurality of scan lines to turn on the thin film transistor 120 of each row, and then the source driver charges and discharges the pixel electrode 130 of each row. In this way, the complete display of the liquid crystal display panel 100 can be completed.
  • FIG. 2 is a schematic structural diagram of the liquid crystal display panel 100 of FIG. 2 is a cross-sectional view of the liquid crystal display panel 100 of FIG. 1 taken along A-A' and B-B'. 2, in the liquid crystal display panel 100, in addition to the insulating layer 510 which has been formed in the overlap region 220 of the data line 101 and the scan line 111, the present invention further establishes a semiconductor between the insulating layer 510 and the data line 101.
  • the first region 513 covered by the semiconductor layer 512 is larger than the overlap region of the data line 101 and the scan line 111.
  • the area of the first region 513 is larger than the area 220. Taking the first region 513 in the upper right corner of FIG. 1 as an example, the distance D1 between the edge of the coincident region 220 and the edge of the first region 513 is greater than 1.5 micrometers ( ⁇ m), and the distance D2 from the data line 101 is 1.5 ⁇ m. Basically, in order to ensure that the semiconductor layer 512 of the first region 513 can positively separate the scan lines 111 and the data lines 101, the area of the first regions 513 must be larger than the overlap regions. Further, according to the experimental results, the distance between the first region 513 and the scanning line 111 and the data line 101 preferably needs to be larger than 1.5 ⁇ m, so that the leakage effect of the scanning line 111 and the data line 101 can be surely reduced.
  • a glass substrate 500 is first provided as a lower substrate, and then a metal thin film deposition process is performed to form a first metal layer (not shown) on the surface of the glass substrate 500, and a first mask is used.
  • PEP Photo Etching Process
  • an insulating layer 510 made of silicon nitride (SiNx) is then deposited to cover the gate 501 and the scan line 111.
  • the second lithography is performed using the second mask to form the semiconductor layers 511, 512.
  • the semiconductor layer 511 includes an amorphous silicon layer 511a as a thin film transistor 120 channel and an ohmic contact layer for reducing impedance (Ohmic) Contact Layer) 511b.
  • the semiconductor layer 512 includes an amorphous silicon layer 512a and an N+ amorphous silicon layer 512b.
  • the semiconductor layer 512 is located in the first region 513, and its efficacy is as described above for assisting the insulating layer 510 to enhance the insulating effect of the data line 101 and the scan line 111.
  • a second metal layer (not shown) is formed on the insulating layer 510, and a third mask is used to perform a third lithography process to define the thin film transistor 120, respectively.
  • the data lines and the scan lines overlap the overlapping area 220, and the area of the first area 513 is larger than the area 220.
  • the boundary of the first region 513 needs to be larger than the boundary of the data line 101 (or the scan line 111), and the distance D2 (or D1) More than 1.5 ⁇ m.
  • a protective layer of silicon nitride (SiNx) is deposited (passivation). a layer 530, and covering the source 521, the drain 522 and the insulating layer 510, and then performing a fourth lithography etching on the fourth mask to remove a portion of the protective layer 530 above the drain 522 until the drain 522
  • the surface is such that a connection hole (Via) 531 is formed over the drain electrode 522.
  • FIG. 2 is also a schematic structural diagram of the liquid crystal display panel 100 shown in FIG. 1 in the first region 513 and the thin film transistor 120.
  • Indium tin oxide is formed on the protective layer 530 (Indi ⁇ m Tin Oxide, ITO) is a transparent conductive layer of the material, and then the transparent conductive layer is etched by a fifth mask to form the transparent conductive layer 130.
  • the transparent electrode layer 130 is electrically connected to the drain 522 of the thin film transistor 120 through a connection hole 531 formed in advance and is connected to the pixel capacitor to be used as a pixel electrode.
  • the liquid crystal display panel 100 of the present invention is completed.
  • the gate 501 of the thin film transistor 120 is formed by a first metal layer
  • the source 521 and the drain 522 are formed by a second metal layer
  • the channel is formed by an amorphous silicon layer 511. .
  • the scan line 111 is also formed by the first metal layer for transmitting a scan signal transmitted from the gate driver
  • the data line 101 is also formed by the second metal layer for transmitting from the source driver. The data signal coming over.
  • a semiconductor layer 512 is formed between the scan line 111 and the data line 101 in addition to the insulating layer 510 which is formed by a conventional liquid crystal display panel.
  • the semiconductor layer 512 increases the distance between the scan line 111 and the data line 101, and also enhances the insulation effect between the scan line 111 and the data line 101, thereby preventing leakage between the data line 101 and the scan line 111.
  • the area of the semiconductor layer 512 must be larger than the overlap area 220 where the scan line 111 overlaps the data line 101. As shown in FIG. 2, the first area 513 where the semiconductor layer 512 is located is larger than the overlap area 220, and the distance is greater than 1.5 ⁇ m. The semiconductor layer 512 can surely separate the data line 101 from the scan line 111 to avoid leakage between the data line 101 and the scan line 111.
  • the present invention utilizes the original five mask process to form an amorphous silicon layer in the first region 513.
  • the distance from the scanning line 111 is increased to enhance the insulation effect between the data line 101 and the scanning line 111, thereby preventing leakage between the data line 101 and the scanning line 111.
  • the amorphous silicon layer 512 additionally constructed by the present invention is used to prevent leakage between the data line 101 and the scanning line 111, however, such an application is not a limitation of the present invention.
  • the semiconductor layer 512 can also be disposed between the common voltage line 105 and the data line 101, that is, the second region 514 additionally covered by the semiconductor layer 512 is substantially coincident with the overlap region of the data line 101 and the common voltage line 105. Therefore, the semiconductor layer 512 can also enhance the insulation effect between the common voltage line 105 and the data line 101, and such a corresponding change does not deviate from the spirit of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种液晶显示面板（100）和其制造方法，于数据线（101）与扫描线（111）的重合区域，除了于数据线（101）与扫描线（111）之间利用一绝缘层（510）来绝缘，还在所述绝缘层（510）与数据线（101）之间另建置一非晶硅层（512）来加强数据线（101）与扫描线（111）之间的绝缘效果，进而降低漏电的状况。此外，可以在不增加掩膜制程的条件下，达成前述的结构，因此，所述液晶显示面板（100）和其制造方法无须增加额外的成本，便可有效减少数据线（101）与扫描线（111）漏电的情况。

Description

液晶显示面板及其制造方法 技术领域
本发明是有关一种液晶显示面板及其制造方法，特别是指一种在数据线与扫描线之间另建置一非晶硅层，以增强数据线与扫描线之间的绝缘效果，进而避免数据线与扫描线之间漏电情况的液晶显示面板及其制造方法。
 背景技术
传统液晶显示器的液晶显示面板包含数个像素(pixel)，而每一个像素包含三个分别代表红绿蓝(RGB)三原色的像素单元构成。当栅极驱动器输出的扫描信号通过扫描线输入，使得每一行的像素单元的薄膜晶体管依序开启，同时源极驱动器则输出对应的数据信号，通过数据线输入至薄膜晶体管，而薄膜晶体管则将数据信号传递至像素电极，使其充电到各自所需的电压，进而使像素显示出不同的灰阶。栅极驱动器会一行接一行地输出扫描信号以将每一行的像素单元的薄膜晶体管打开，再由源极驱动器对每一行的像素电极进行充放电。如此依序下去，便可完成液晶显示面板的完整显示。
然而，传统液晶显示面板的制程上，每个数据线与扫描线的交接处(cross over)都会设置一绝缘层(insulating layer)以隔绝数据线与扫描线之间的电性连接。但是，由于绝缘层容易出现绝缘不佳的问题，使得数据线与扫描线之间产生漏电的现象，如此会使数据线与扫描线传递的信号不稳定，因此影响液晶显示面板的显示效果。
因此，业界须提出解决方式，以提升液晶显示面板的效能。
 技术问题
有鉴于此，本发明提供一种液晶显示面板及其制造方法，其于数据线与扫描线的重合区域，除了于数据线与扫描线之间利用一绝缘层来绝缘，并于所述绝缘层与数据线之间另建置一非晶硅层来加强数据线与扫描线之间的绝缘效果，进而降低漏电的状况。
 技术解决方案
依据本发明的实施例，本发明提供一种液晶显示面板，所述液晶显示面板包括一玻璃基板以及一薄膜晶体管，所述薄膜晶体管包含一栅极、一源极以及一漏极；所述液晶显示面板另包含：一扫描线，位于所述玻璃基板上，所述扫描线耦接至所述薄膜晶体管的所述栅极；一绝缘层，位于所述扫描线之上；一数据线，位于所述绝缘层之上，耦接于所述薄膜晶体管的所述源极，其中所述数据线与所述扫描线重叠于一重合区域；以及一半导体层，位于所述栅极绝缘层以及所述数据线之间，所述半导体层之位置对应所述重合区域，且所述半导体层之面积之大于所述重合区域，以通过所述半导体层来加强所述数据线与扫描线之间的绝缘效果。
依据本发明的一实施例，本发明另提供一种液晶显示面板的制作方法，其包括下列步骤：提供一玻璃基板；形成一第一金属层于所述玻璃基板上；蚀刻所述第一金属层，以形成一薄膜晶体管的栅极以及一扫描线；在所述第一薄膜晶体管的栅极以及所述扫描在线形成一绝缘层；形成一半导体层于所述绝缘层上；蚀刻所述半导体层，以形成所述薄膜晶体管的通道区域以及一第一区域；以及形成一第二金属层，并蚀刻所述第二金属层，以形成所述薄膜晶体管的源极和漏极、以及一数据线；其中所述数据线与所述扫描线重叠于一重合区域，所述重合区域与所述第一区域的位置对应，且所述第一区域的面积大于所述重合区域。
依据本发明的实施例，所述半导体层为一非晶硅层，所述半导体层另包含一高电子掺杂浓度的N+ 非晶硅层。
依据本发明的实施例，所述第一区域之一边与所述数据线与所述扫描线的距离大于1.5微米(µm)
 有益效果
相较于现有技术，本发明的液晶显示面板和其制造方法于数据线与扫描线的重合区域，除了于数据线与扫描线之间利用一栅极绝缘层来绝缘，并于所述栅极绝缘层与数据线之间另建置一非晶硅层来加强数据线与扫描线之间的绝缘效果，进而降低漏电的状况。此外，本发明可以在不增加掩膜制程的条件下，达成前述的结构，因此，本发明液晶显示面板和其制造方法无须增加额外的成本，便可有效减少数据线与扫描线漏电的情况。
 附图说明
图1是本发明液晶显示面板的简易示意图。
图2是图1的液晶显示面板的结构示意图。
图3至图6为本发明液晶显示面板的制程方式示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施之特定实施例。本发明所提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”、“顶”、“底”、“水平”、“垂直”等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参阅图1，图1是本发明液晶显示面板100的简易示意图。液晶显示面板100包含数条数据线、数条扫描线、数条公共电压线(Common line)、数个薄膜晶体管和数个像素电极。每一薄膜晶体管电性连接一扫描线和一数据线。为简化图式，在以下实施例中，仅绘示数据线101、扫描线111、公共电压线105及薄膜晶体管120。薄膜晶体管120的栅极耦接到扫描线111，薄膜晶体管120的源极则耦接至数据线101。此外，薄膜晶体管120的漏极耦接至像素电极130。公共电压线105用来提供一公共电压信号。
液晶显示面板100的驱动方式如下所述：栅极驱动器(图未示)输出的扫描信号通过扫描线111输入，使得连接扫描线111的薄膜晶体管120依序开启，同时源极驱动器(未图示)则输出对应的数据信号，通过数据线101输入至薄膜晶体管120，而薄膜晶体管120则将数据信号传递至像素电极130，使其充电到所需的电压。而像素电极130上方的液晶就是依据该数据信号以及公共电压线105提供的公共电压信号间的电压差扭转(twist)，进而显示出不同的灰阶。栅极驱动器会通过数条扫描线一行接一行地输出扫描信号以将每一行的薄膜晶体管120打开，再由源极驱动器对每一行的像素电极130进行充放电。如此依序下去，便可完成液晶显示面板100的完整显示。
请一并参阅图1和图2，图2是图1的液晶显示面板100的结构示意图。图2所绘示的是图1的液晶显示面板100沿A-A’和B-B’的截面图。图2于液晶显示面板100中，除了于数据线101与扫描线111的重合区域220本已建置的绝缘层510之外，本发明另于绝缘层510与数据线101之间建置一半导体层512。半导体层512覆盖的第一区域513大于数据线101与扫描线111重合区域。通过半导体层512的建置，可以增强数据线101与扫描线111间的绝缘效果，进而防止数据线101与扫描线111间漏电的发生。
第一区域513的面积比重合区域220更大。以图1右上角的第一区域513为例，重合区域220的边缘与第一区域513的边缘之间的距离D1大于1.5微米(µm)，且距离数据线101的距离D2为1.5µm。基本上为了确保第一区域513的半导体层512能够确实地隔开扫描线111以及数据线101，第一区域513的面积必须大于重合区域。此外，根据实验结果，第一区域513与扫描线111以及数据线101的距离，较佳地必须大于1.5µm，如此方能确实降低扫描线111与数据线101的漏电效应。
在以下的揭露中，将说明本发明液晶显示面板100的制程方式。
请参阅图3，首先提供一个玻璃基板500当作下基板，接着进行一金属薄膜沉积制程，以于玻璃基板500表面形成一层第一金属层（未显示），并利用一第一掩膜来进行第一微影蚀刻（Photo Etching Process，PEP），以蚀刻得到薄膜晶体管120的栅极501以及扫描线111。
接着请参阅图4，接着沉积以氮化硅(SiNx)为材质的绝缘层510而覆盖栅极501以及扫描线111。于绝缘层510上连续沉积非晶硅(a－Si，Amorphous Si)层以及一高电子掺杂浓度的N+ 非晶硅层。利用第二掩膜来进行第二微影蚀刻以构成半导体层511、512。半导体层511包含作为薄膜晶体管120通道的非晶硅层511a以及用来降低阻抗的欧姆接触层(Ohmic contact layer)511b。半导体层512包含非晶硅层512a以及N+非晶硅层512b。半导体层512是位于第一区域513，而其功效如前述，用来辅助绝缘层510，以加强数据线101与扫描线111的绝缘效果。
请参阅图5，接着在绝缘层510上形成一全面覆盖的第二金属层(未绘示于图中)，并利用第三掩膜来进行第三微影蚀刻以分别定义出薄膜晶体管120的源极521及漏极522以及数据线101。如图4亦可知，数据线与扫描线重叠于一重合区域220，而第一区域513的面积比重合区域220更大。较佳地，第一区域513的边界需大于数据线101(或扫描线111)的边界，其距离D2(或D1) 大于1.5µm。
请参阅图6，如图6所示，接着沉积以氮化硅(SiNx)为材质的保护层(passivation layer)530，并覆盖源极521、及漏极522和绝缘层510，再利用第四掩膜来进行第四微影蚀刻用以去除漏极522上方的部份保护层530，直至漏极522表面，以于漏极522上方形成连接孔(Via)531。
请再参阅图2，图2也是图1所示的液晶显示面板100在第一区域513和薄膜晶体管120的结构示意图。在保护层530上形成以氧化铟锡物(Indiµm tin oxide，ITO)为材质的透明导电层，接着利用一第五掩膜蚀刻所述透明导电层以形成透明导电层130。透明电极层130通过预先形成的连接孔531与薄膜晶体管120的漏极522电性连接且连接至像素电容，以作为像素电极使用。至此，便完成本发明所述液晶显示面板100。
如图2所示，薄膜晶体管120的栅极501以一第一金属层作成，其源极521与漏极522以一第二金属层制成，而其通道则以一非晶硅层511作成。
此外，扫描线111亦以所述第一金属层作成，用来传递自栅极驱动器传递过来的扫描信号，而数据线101亦以所述第二金属层作成，用来传递自源极驱动器传递过来的数据信号。
在此请注意，扫描线111与数据线101之间，除了传统液晶显示面板便会建置的绝缘层510之外，另形成了半导体层512。半导体层512使扫描线111与数据线101之间的距离加大，亦增强了扫描线111与数据线101间的绝缘效果，进而避免数据线101与扫描线111间的漏电。
此外，半导体层512的面积必须大于扫描线111与数据线101重叠的重合区域220，如图2所示，半导体层512所在的第一区域513大于重合区域220，且其距离大于1.5µm，如此便可半导体层512确实隔开数据线101与扫描线111，避免数据线101与扫描线111间的漏电。
在此请注意，由于在传统的液晶屏幕制程之中，便已经有非晶硅层的沉积与微影蚀刻，但是，在传统的制程之中，非晶硅层仅仅作为薄膜晶体管120的通道使用，而并未有其它用途。因此，本发明利用原本的五道掩膜制程，将非晶硅层另形成于所述第一区域513，如此一来，本发明无须增加额外的成本与掩膜制程，便可将数据线101与扫描线111的距离拉大，以加强数据线101与扫描线111之间的绝缘效果，进而避免数据线101与扫描线111之间的漏电产生。
请继续参阅图1。在此请注意，虽然于前述的实施例中，本发明另建置的非晶硅层512是用来防止数据线101与扫描线111间的漏电状况，然而，如此的应用并非本发明的限制。在实际应用中，由于公共电压线105与扫描线111均是由第一金属层制成，且公共电压线105与数据线101亦会相互重叠。因此，半导体层512也可用设置于公共电压线105与数据线101之间，也就是说半导体层512另外覆盖的第二区域514，是大致上符合数据线101与公共电压线105的重合区域。因此半导体层512也可以加强公共电压线105与数据线101间的绝缘效果，如此的相对应变化，亦不违背本发明的精神。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
序列表自由内容

Claims (11)

  1. 一种液晶显示面板，所述液晶显示面板包括一玻璃基板以及一薄膜晶体管，所述薄膜晶体管包含一栅极、一源极以及一漏极；其特征在于：所述液晶显示面板另包含：
    一扫描线，位于所述玻璃基板上，所述扫描线耦接至所述薄膜晶体管的所述栅极；
    一绝缘层，位于所述扫描线之上；
    一数据线，位于所述绝缘层之上，耦接于所述薄膜晶体管的所述源极，其中所述数据线与所述扫描线重叠于一重合区域；以及
    一半导体层，位于所述栅极绝缘层以及所述数据线之间，所述半导体层的位置对应所述重合区域，且所述半导体层的面积大于所述重合区域，以通过所述半导体层来加强所述数据线与所述扫描线之间的绝缘效果。
  2. 根据权利要求1所述的液晶显示面板，其特征在于：所述半导体层为一非晶硅层。
  3. 根据权利要求2所述的液晶显示面板，其特征在于：所述非晶硅层距的边缘与所述重合区域的边缘之间的距离大于1.5微米。
  4. 根据权利要求2所述的液晶显示面板，其特征在于：所述半导体层另包含一高电子掺杂浓度的N+ 非晶硅层。
  5. 一种液晶显示面板，所述液晶显示面板包括一玻璃基板以及一薄膜晶体管，所述薄膜晶体管包含一栅极、一源极以及一漏极；其特征在于：所述液晶显示面板另包含：
    一公共电压线，位于所述玻璃基板上，用来传递一公共电压至所述液晶显示面板；
    一绝缘层，位于所述公共电压线之上；
    一数据线，位于所述绝缘层之上，耦接于所述薄膜晶体管的所述源极，所述数据线与所述公共电压线重叠于一重合区域；以及
    一半导体层，位于所述栅极绝缘层以及所述数据线之间，所述半导体层的位置对应所述重合区域，且所述半导体层的面积大于所述重合区域，以通过所述半导体层来加强所述数据线与所述公共电压线之间的绝缘效果。
  6. 根据权利要求5所述的液晶显示面板，其特征在于：所述半导体层为一非晶硅层。
  7. 根据权利要求6所述的液晶显示面板，其特征在于：所述半导体层另包含一高电子掺杂浓度的N+ 非晶硅层。
  8. 根据权利要求6所述的液晶显示面板，其特征在于：所述非晶硅层距的边缘与所述重合区域的边缘之间的距离大于1.5微米。
  9. 一种液晶显示面板的制造方法，其特征在于，所述制造方法包含：
    提供一玻璃基板；
    形成一第一金属层于所述玻璃基板上；
    蚀刻所述第一金属层，以形成一薄膜晶体管的栅极以及一扫描线；
    在所述第一薄膜晶体管的栅极以及所述扫描线上形成一绝缘层；
    形成一半导体层于所述绝缘层上；
    蚀刻所述半导体层，以形成所述薄膜晶体管的通道区域以及一第一区域；以及
    形成一第二金属层，并蚀刻所述第二金属层，以形成所述薄膜晶体管的源极和漏极以及一数据线，其中所述数据线与所述扫描线重叠于一重合区域，所述重合区域与所述第一区域的位置对应，且所述第一区域的面积大于所述重合区域。
  10. 根据权利要求9所述的制造方法，其特征在于：所述半导体层为一非晶硅层。
  11. 根据权利要求10所述的制造方法，其特征在于：所述第一区域的边缘与所述重合区域的边缘之间的距离大于1.5微米。
PCT/CN2011/081845 2011-11-02 2011-11-07 液晶显示面板及其制造方法 WO2013063814A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/379,568 US20130106679A1 (en) 2011-11-02 2011-11-07 Lcd panel and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110341153.9 2011-11-02
CN2011103411539A CN102636926A (zh) 2011-11-02 2011-11-02 液晶显示面板及其制造方法

Publications (1)

Publication Number Publication Date
WO2013063814A1 true WO2013063814A1 (zh) 2013-05-10

Family

ID=46621366

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/081845 WO2013063814A1 (zh) 2011-11-02 2011-11-07 液晶显示面板及其制造方法

Country Status (2)

Country Link
CN (1) CN102636926A (zh)
WO (1) WO2013063814A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104299972B (zh) * 2014-09-12 2018-07-27 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制造方法、液晶显示器
CN114141794A (zh) * 2021-12-08 2022-03-04 武汉华星光电技术有限公司 显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05341313A (ja) * 1992-06-05 1993-12-24 Toshiba Corp アクティブマトリクス型液晶表示素子
CN1680861A (zh) * 2004-12-03 2005-10-12 友达光电股份有限公司 薄膜晶体管液晶显示器、叠层储存电容器及其形成方法
CN101140938A (zh) * 2006-09-07 2008-03-12 中华映管股份有限公司 薄膜晶体管阵列基板及其制造方法
CN102053435A (zh) * 2009-11-10 2011-05-11 乐金显示有限公司 液晶显示设备及其制造方法
CN102184966A (zh) * 2011-04-15 2011-09-14 福州华映视讯有限公司 晶体管数组基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05341313A (ja) * 1992-06-05 1993-12-24 Toshiba Corp アクティブマトリクス型液晶表示素子
CN1680861A (zh) * 2004-12-03 2005-10-12 友达光电股份有限公司 薄膜晶体管液晶显示器、叠层储存电容器及其形成方法
CN101140938A (zh) * 2006-09-07 2008-03-12 中华映管股份有限公司 薄膜晶体管阵列基板及其制造方法
CN102053435A (zh) * 2009-11-10 2011-05-11 乐金显示有限公司 液晶显示设备及其制造方法
CN102184966A (zh) * 2011-04-15 2011-09-14 福州华映视讯有限公司 晶体管数组基板

Also Published As

Publication number Publication date
CN102636926A (zh) 2012-08-15

Similar Documents

Publication Publication Date Title
US10177170B2 (en) Display device and method for manufacturing same
WO2017166392A1 (zh) 阵列基板及其制造方法、显示面板和显示装置
US9612487B2 (en) Array substrate, manufacturing method thereof and display device
WO2012136010A1 (zh) 芯片扇出设计、其形成方法及使用所述设计的液晶显示器
WO2013056460A1 (zh) 液晶显示面板及形成液晶显示面板的方法
WO2013086746A1 (zh) 液晶显示面板以及其制造方式
WO2013071493A1 (zh) 平面显示面板及其修复方法
WO2013056617A1 (zh) 像素单元、阵列基板、液晶面板及阵列基板的制造方法
JPH09162412A (ja) 薄膜トランジスタおよび薄膜トランジスタアレイ
WO2010111848A1 (zh) 像素电极结构
CN103309100B (zh) 液晶显示装置及其制造方法
JP6370003B2 (ja) 画素構造及びその製造方法
WO2019080613A1 (zh) 阵列基板、显示面板、显示装置、以及制造阵列基板的方法
WO2015192595A1 (zh) 阵列基板及其制备方法、显示装置
CN103309101A (zh) 布线构造及具备它的薄膜晶体管阵列基板以及显示装置
WO2023217261A1 (zh) 显示面板和显示装置
WO2013139040A1 (zh) 液晶显示面板以及其制造方法
WO2021227122A1 (zh) 阵列基板和显示面板
WO2020134957A1 (zh) 显示面板、显示面板的制造方法和显示装置
WO2013143064A1 (zh) 液晶显示面板以及其制造方法
WO2015096374A1 (zh) 阵列基板及其制作方法、显示装置和薄膜晶体管
WO2013063814A1 (zh) 液晶显示面板及其制造方法
WO2013020318A1 (zh) Tft像素单元
WO2013155724A1 (zh) 显示面板的布线结构及像素结构
KR20040017637A (ko) 액정표시소자의 콘택 배선 및 그 형성방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13379568

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11874949

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11874949

Country of ref document: EP

Kind code of ref document: A1