WO2013020318A1 - Tft像素单元 - Google Patents

Tft像素单元 Download PDF

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Publication number
WO2013020318A1
WO2013020318A1 PCT/CN2011/079557 CN2011079557W WO2013020318A1 WO 2013020318 A1 WO2013020318 A1 WO 2013020318A1 CN 2011079557 W CN2011079557 W CN 2011079557W WO 2013020318 A1 WO2013020318 A1 WO 2013020318A1
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electrode
semiconductor layer
disposed
insulating layer
pixel unit
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PCT/CN2011/079557
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English (en)
French (fr)
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康志聪
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深圳市华星光电技术有限公司
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Priority to US13/376,594 priority Critical patent/US20130038517A1/en
Publication of WO2013020318A1 publication Critical patent/WO2013020318A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to a pixel unit of a liquid crystal panel, and more particularly to a TFT pixel unit having a longitudinal structure.
  • FIG. 1 is a conventional TFT (thin-film transistor, Schematic diagram of a thin film transistor) pixel unit.
  • the TFT pixel unit includes a scan line 90, a data line 91, a pixel electrode (not shown), and a switch unit 93.
  • the switch unit 93 includes a gate 930, a semiconductor layer 931, a drain 932, and a source 933.
  • the gate 930 is part of the scan line 90.
  • the semiconductor layer 931 is disposed on the gate 930.
  • the drain electrode 932 extends from the side of the data line 91 and is disposed on the semiconductor layer 931.
  • the source electrode 933 is disposed on the semiconductor layer 931 and connected to the pixel electrode.
  • an electron channel can be formed in the semiconductor layer 931, and a conduction state is formed between the drain 932 and the source 933 to achieve the function of the switch. At this time, the pixel electrode connected to the source electrode 933 is Can be charged. As can be seen from FIG. 1, the drain 932 and the source 933 are disposed on the top surface of the semiconductor layer 931.
  • Fast charging capability and high aperture ratio is a design requirement for a pixel unit of a general TFT liquid crystal display.
  • the charging capability of the pixel unit can generally be improved by reducing the channel width (such as C in FIG. 1) or increasing the channel range between the source and the drain.
  • the invention provides a TFT pixel unit, comprising:
  • a first insulating layer disposed on the scan line and covering the inner side surface
  • drain segment extending from a side of the data line and disposed on the first insulating layer
  • a source segment disposed on a top surface of the semiconductor layer, the drain segment, the semiconductor layer and the source segment being adjacent to an inner side of the scan line;
  • a pixel electrode is disposed in the pixel region and connected to the source segment.
  • the width of the source segment is equal to the width of the semiconductor layer.
  • the TFT pixel unit further includes a common electrode line and a second electrode, wherein the common electrode line is disposed under the pixel electrode insulatively across the first insulating layer, And being parallel to the scan line and insulated from the data line; the second electrode is disposed on the first insulating layer corresponding to the position of the common electrode line, and is connected to the pixel electrode.
  • the TFT pixel unit further includes a second insulating layer, wherein the second insulating layer covers the source segment, the semiconductor layer, the drain segment, and the a second electrode having a first via corresponding to the source segment, the pixel electrode connecting the source segment through the first via.
  • the second insulating layer further has a second through hole corresponding to the second electrode, and the pixel electrode is connected to the second electrode through the second through hole.
  • the semiconductor layer comprises an amorphous silicon layer and an n-type amorphous silicon layer.
  • the invention mainly comprises forming the TFT switch of the longitudinal stack structure by the data line, the drain section, the semiconductor layer and the source section, thereby reducing the loss of the aperture ratio.
  • 1 is a partial plan view of a conventional TFT pixel unit.
  • Figure 2 is a partial plan view showing a preferred embodiment of the TFT pixel unit of the present invention.
  • Figure 3 is a cross-sectional view taken along line A-A' of Figure 2;
  • FIG. 2 and FIG. 3 are respectively a partial plan view and a cross-sectional view of a TFT pixel unit according to a preferred embodiment of the present invention.
  • the TFT pixel unit of the present invention is applied to a thin film transistor liquid crystal display, comprising a scan line 10, a first insulating layer 11, a data line 12, a drain segment 13, a semiconductor layer 14, a source segment 15 and a Pixel electrode 16.
  • the scan line 10 is made of a conductive material and has an inner side 100.
  • the first insulating layer 11 is disposed on the scan line 10 by a deposition method and covers the inner side surface 100.
  • the first insulating layer 11 is preferably a silicon nitride (SiNx) or silicon oxide (SiOx) film.
  • the data line 12 and the scan line 10 are insulated from each other by the first insulating layer 11 , and the data line 12 and the scan line 10 define a pixel area together.
  • the drain segment 13 extends from the side of the data line 12 and is disposed on the first insulating layer 11 .
  • the drain segment 13 extends in a direction parallel to the scan line 10, and is adjacent to the inner side surface 100 of the scan line 10 via the first insulating layer 11.
  • the semiconductor layer 14 is disposed on a top surface of the drain segment 13 . Similarly, the semiconductor layer 14 extends in a direction parallel to the scan line 10, and the inner side surface 100 of the scan line 10 is adjacent to the first insulating layer 11 .
  • the semiconductor layer 14 preferably comprises an amorphous silicon layer 14a (Amorphus Silicon, a-Si) and n-type amorphous silicon layer 14b.
  • the source segment 15 is disposed on a top surface of the semiconductor layer 14. Similarly, the source segment 15 extends in a direction parallel to the scan line 10, and the inner side surface 100 of the scan line 10 is adjacent to the first insulating layer 11 .
  • the width of the source segment 15 is preferably equal to the width of the semiconductor layer 14.
  • the pixel electrode 16 is disposed in the pixel region and connected to the source segment 15.
  • the TFT pixel unit of the present invention further includes a common electrode line 17, a second electrode 18 and a second insulating layer 19.
  • the common electrode line 17 is disposed under the pixel electrode 16 insulatively across the first insulating layer 11 and is parallel to the scanning line 10 and is also insulatively interleaved with the data line 12.
  • the second electrode 18 is disposed on the first insulating layer 11 corresponding to the position of the common electrode line 17 and is connected to the pixel electrode 16.
  • the second electrode 18 and the common electrode line 17 form a storage capacitor capable of storing a pixel voltage.
  • the second insulating layer 19 covers the drain segment 13 , the semiconductor layer 14 , the source segment 15 , and the second electrode 18 . Furthermore, the second insulating layer 19 has a first via 200 corresponding to the source segment 15 such that the pixel electrode 16 can be connected to the source segment 15 through the first via 200. The second insulating layer 19 further has a second through hole 201 corresponding to the second electrode 18, so that the pixel electrode 16 can be connected to the second electrode 18 through the second through hole 201.
  • the structure in which the drain segment 13, the semiconductor layer 14 and the source segment 15 are stacked is formed with a vertical overlap with respect to the scan line 10 via the first insulating layer 11.
  • the TFT switch architecture wherein the scan line 10 is a gate terminal.
  • the semiconductor layer 14 forms an electron channel between the drain segment 13 and the source segment 15.
  • the semiconductor layer 14 can achieve the required film thickness by a deposition process, thereby generating a small-channel high-current charging function.
  • the drain section 13, the semiconductor layer 14 and the source section 15 of the TFT pixel unit of the present invention form a vertically stacked TFT compared to the source of the conventional TFT pixel unit disposed on the top surface of the semiconductor layer.
  • the switch architecture reduces the loss of aperture ratio and helps to improve the picture quality of the liquid crystal display.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供一种TFT像素单元，其包含扫描线、第一绝缘层、资料线、源极段、半导体层、漏极段及像素电极。所述第一绝缘层设于扫描线上并包覆其内侧面。资料线与扫描线彼此绝缘交错而共同定义一像素区。漏极段自资料线一侧延伸出而配置于第一绝缘层上。半导体层设置于漏极段的顶面。源极段设置于所述半导体层的顶面。漏极段、半导体层与源极段邻近扫描线的内侧面。像素电极设置像素区内并连接源极段。所述资料线、漏极段、半导体层与源极段构成一纵向堆叠结构的TFT开关，减少了开口率的损失。

Description

TFT像素单元 技术领域
本发明是有关于一种液晶面板的像素单元，特别是有关于一种具有纵向结构的TFT像素单元。
 背景技术
请参考图1所示，是现有TFT(thin-film transistor, 薄膜晶体管)像素单元的结构示意图。一般来说，TFT像素单元包含扫描线90、资料线91、像素电极(图中未示)及开关单元93，所述开关单元93包含栅极930、半导体层931、漏极932以及源极933。所述栅极930是所述扫描线90的一部分。所述半导体层931设置于所述栅极930上。所述漏极932则自所述资料线91一侧延伸出而配置于所述半导体层931上。所述源极933则配置于所述半导体层931上并连接所述像素电极。对栅极930施加适当电压，即可在半导体层931形成电子通道，而使漏极932与源极933之间形成导通状态，达到开关的作用，此时，连接源极933的像素电极即可被充电。从图1可知，所述漏极932与所述源极933是配置于所述半导体层931的顶面。
快速的充电能力及高开口率(aperture ratio)是一般TFT液晶显示器对像素单元的设计需求。就现有技术而言，一般可藉由减少通道宽度(如图1的C)或者增大源极与漏极之间的通道范围，来提高像素单元的充电能力。
然而，减少通道宽度通常需要辅以特殊光罩及光阻的配合，制作设计困难。而增大通道范围则会造成开口率的损失，使TFT液晶显示器的光穿透率下降。
故，有必要提供一种TFT像素单元，以解决现有技术所存在的问题。
 技术问题
有鉴于现有技术的缺点，本发明的主要目的在于提供一种TFT像素单元，其通过纵向的TFT像素结构，减少了开口率的损失。
 技术解决方案
本发明提供一种TFT像素单元，包含：
一扫描线，具有一内侧面；
一第一绝缘层，设于所述扫描线上并包覆所述内侧面；
一资料线，与所述扫描线彼此绝缘交错而共同定义一像素区；
一漏极段，自所述资料线一侧延伸出而配置于第一绝缘层上；
一半导体层，设置于所述源极段的顶面；
一源极段，设置于所述半导体层的顶面，所述漏极段、半导体层与所述源极段邻近所述扫描线的内侧面；以及
一像素电极，设置所述像素区内并连接所述源极段。
在本发明的一实施例中，所述源极段的宽度与所述半导体层的宽度相等。
在本发明的一实施例中，所述TFT像素单元还包含一共电极线与一第二电极，其中所述共电极线是隔着所述第一绝缘层绝缘地配置于所述像素电极底下，并与所述扫描线平行，且与所述资料线绝缘交错；所述第二电极是对应所述共电极线的位置而设于所述第一绝缘层上，并连接所述像素电极。
在本发明的一实施例中，所述TFT像素单元还包含一第二绝缘层，其中所述第二绝缘层是覆盖所述源极段、所述半导体层、所述漏极段及所述第二电极，并具有一对应所述源极段的第一穿孔，所述像素电极是通过所述第一穿孔连接所述源极段。
在本发明的一实施例中，所述第二绝缘层还具有一对应所述第二电极的第二穿孔，所述像素电极是通过所述第二穿孔连接所述第二电极。
在本发明的一实施例中，所述半导体层包含非晶硅层及n型非晶硅层。
 有益效果
本发明主要是将所述资料线、漏极段、半导体层与源极段构成一纵向堆叠结构的TFT开关，减少了开口率的损失。
附图说明
图1是现有TFT像素单元的局部平面图。
图2是本发明TFT像素单元一较佳实施例的局部平面图。
图3是图2沿A-A’的剖视图。
 本发明的最佳实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参考图2及图3所示，图2及图3分别为本发明TFT像素单元一较佳实施例的局部平面图及剖视图。本发明的TFT像素单元是应用于薄膜晶体管液晶显示器，包含有一扫描线10、一第一绝缘层11、一资料线12、一漏极段13、一半导体层14、一源极段15以及一像素电极16。
所述扫描线10是导电材料所构成，具有一内侧面100。
所述第一绝缘层11是通过沉积方式设于所述扫描线10上并包覆所述内侧面100。所述第一绝缘层11优选是氮化硅(SiNx)或氧化硅(SiOx)薄膜。
所述资料线12与所述扫描线10是利用所述第一绝缘层11而彼此绝缘交错，且所述资料线12与所述扫描线10共同定义一像素区。
所述漏极段13自所述资料线12一侧延伸出而配置于第一绝缘层上11。更详细地，所述漏极段13是沿着与所述扫描线10平行的方向延伸，而隔着所述第一绝缘层11邻近所述扫描线10的内侧面100。
所述半导体层14是设置于所述漏极段13的顶面。同样的，所述半导体层14是沿着与所述扫描线10平行的方向延伸，而隔着所述第一绝缘层上11邻近所述扫描线10的内侧面100。所述半导体层14优选是包含非晶硅层14a(Amorphus Silicon, a-Si)及n型非晶硅层14b。
所述源极段15是设置于所述半导体层14的顶面。同样的，所述源极段15是沿着与所述扫描线10平行的方向延伸，而隔着所述第一绝缘层上11邻近所述扫描线10的内侧面100。所述源极段15的宽度优选是与所述半导体层14的宽度相等。
所述像素电极16是设置所述像素区内并连接所述源极段15。
本实施例中，本发明TFT像素单元还包含一共电极线17、一第二电极18及一第二绝缘层19。
所述共电极线17是隔着所述第一绝缘层11绝缘地配置于所述像素电极16底下，并与所述扫描线10平行，且同样与所述资料线12绝缘交错。
所述第二电极18是对应所述共电极线17的位置而设于所述第一绝缘层11上，并连接所述像素电极16。所述第二电极18与所述共电极线17构成一可储存像素电压的储存电容。
所述第二绝缘层19是覆盖所述漏极段13、所述半导体层14、所述源极段15及所述第二电极18。再者，所述第二绝缘层19具有一对应所述源极段15的第一穿孔200，使所述像素电极16可通过所述第一穿孔200连接所述源极段15。所述第二绝缘层19还具有一对应所述第二电极18的第二穿孔201，使所述像素电极16可通过所述第二穿孔201连接所述第二电极18。
本发明的TFT像素单元中，所述漏极段13、半导体层14与源极段15所堆叠而成的结构隔着所述第一绝缘层11而相对所述扫描线10形成一纵向对叠的TFT开关架构，其中所述扫描线10即为栅极端。当扫描线10接收适当电压时，所述半导体层14即在所述漏极段13与源极段15之间形成电子通道。而此半导体层14可通过沉积工艺达到需求的膜厚，进而产生小通道高电流充电的功能。
由上述说明可知，相较于现有TFT像素单元的源极配置于半导体层的顶面，本发明的TFT像素单元的漏极段13、半导体层14与源极段15构成纵向对叠的TFT开关架构，相对减少了开口率的损失，进而有助于提升液晶显示器的画质。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。
 本发明的实施方式
工业实用性
序列表自由内容

Claims (7)

  1. 一种TFT像素单元，其特征在于：所述TFT像素单元包含：
    一扫描线，具有一内侧面；
    一第一绝缘层，设于所述扫描线上并包覆所述内侧面；
    一资料线，与所述扫描线彼此绝缘交错而共同定义一像素区；
    一漏极段，自所述资料线一侧延伸出而配置于第一绝缘层上；
    一半导体层，设置于所述源极段的顶面；
    一源极段，设置于所述半导体层的顶面，所述漏极段、半导体层与所述源极段邻近所述扫描线的内侧面，且所述源极段的宽度与所述半导体层的宽度相等；
    一像素电极，设置所述像素区内并连接所述源极段；
    一共电极线，隔着所述第一绝缘层绝缘地配置于所述像素电极底下，并与所述扫描线平行，且与所述资料线绝缘交错；以及
    一第二电极，对应所述共电极线的位置而设于所述第一绝缘层上，并连接所述像素电极。
  2. 一种TFT像素单元，其特征在于：所述TFT像素单元包含：
    一扫描线，具有一内侧面；
    一第一绝缘层，设于所述扫描线上并包覆所述内侧面；
    一资料线，与所述扫描线彼此绝缘交错而共同定义一像素区；
    一漏极段，自所述资料线一侧延伸出而配置于第一绝缘层上；
    一半导体层，设置于所述源极段的顶面；
    一源极段，设置于所述半导体层的顶面，所述漏极段、半导体层与所述源极段邻近所述扫描线的内侧面；以及
    一像素电极，设置所述像素区内并连接所述源极段。
  3. 如权利要求2所述的TFT像素单元，其特征在于：所述源极段的宽度与所述半导体层的宽度相等。
  4. 如权利要求2所述的TFT像素单元，其特征在于：所述TFT像素单元还包含一共电极线与一第二电极，其中所述共电极线是隔着所述第一绝缘层绝缘地配置于所述像素电极底下，并与所述扫描线平行，且与所述资料线绝缘交错；所述第二电极是对应所述共电极线的位置而设于所述第一绝缘层上，并连接所述像素电极。
  5. 如权利要求4所述的TFT像素单元，其特征在于：所述TFT像素单元还包含一第二绝缘层，其中所述第二绝缘层是覆盖所述漏极段、所述半导体层、所述源极段及所述第二电极，并具有一对应所述源极段的第一穿孔，所述像素电极是通过所述第一穿孔连接所述源极段。
  6. 如权利要求5所述的TFT像素单元，其特征在于：所述第二绝缘层还具有一对应所述第二电极的第二穿孔，所述像素电极是通过所述第二穿孔连接所述第二电极。
  7. 如权利要求2所述的TFT像素单元，其特征在于：所述半导体层包含非晶硅层及n型非晶硅层。
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