WO2017166428A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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WO2017166428A1
WO2017166428A1 PCT/CN2016/084702 CN2016084702W WO2017166428A1 WO 2017166428 A1 WO2017166428 A1 WO 2017166428A1 CN 2016084702 W CN2016084702 W CN 2016084702W WO 2017166428 A1 WO2017166428 A1 WO 2017166428A1
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Prior art keywords
gate
thin film
film transistor
line
source
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PCT/CN2016/084702
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English (en)
French (fr)
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程鸿飞
先建波
李盼
郝学光
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京东方科技集团股份有限公司
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Priority to US15/525,622 priority Critical patent/US10147744B2/en
Publication of WO2017166428A1 publication Critical patent/WO2017166428A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004—Devices characterised by their operation
    • H01L33/0041—Devices characterised by their operation characterised by field-effect operation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to an array substrate, a method for manufacturing the same, and a display device.
  • the existing liquid crystal display panel comprises an array substrate, the array substrate comprises a data line, a gate line and a plurality of pixel regions arranged vertically, and a thin film transistor and a pixel electrode are arranged in each pixel region, and a gate and a gate line of the thin film transistor are disposed. Electrically connected, the drain of the thin film transistor is electrically connected to the pixel electrode, and the source of the thin film transistor is electrically connected to the data line, so that the thin film transistor can be driven by the data line and the gate line, and the data signal is written to the pixel electrode.
  • two pixel electrodes are generally disposed in each pixel region, and two pixel electrodes are respectively driven by two thin film transistors.
  • the present invention is directed to the above-mentioned technical problems, and provides an array substrate, a method of manufacturing the same, and a display device.
  • the array substrate can reduce the coupling capacitance between the data lines and the gate lines and reduce mutual interference between the two thin film transistors in each pixel region.
  • an array substrate comprising a substrate substrate, a gate line, a data line and a plurality of pixel regions, wherein the pixel region is provided with a first pixel electrode and a second pixel electrode, The first pixel electrode and the second The pixel electrodes are oppositely disposed on opposite sides of the gate line corresponding to the pixel region, and are electrically insulated from each other; the pixel region is further provided with a first thin film transistor and a second thin film transistor, and the data line passes through the first The thin film transistor is electrically connected to the first pixel electrode, and the data line is electrically connected to the second pixel electrode through the second thin film transistor, a gate of the first thin film transistor and a gate of the second thin film transistor The poles are respectively disposed on opposite sides of the corresponding gate line of the pixel region and disposed opposite to each other, wherein the gate line is provided with a gate slit in a region crossing the data line.
  • the gate slit is opened along an extending direction of the gate line, and the gate slit extends at least in a length direction of the gate slit beyond a region where the gate line intersects the data line.
  • the width of the gate cut is smaller than the width of the gate line.
  • the gate cut is opened along a direction in which the gate line extends, and the gate cut extends beyond a gate of the first thin film transistor and the second thin film transistor in a length direction of the gate cut The area between the gates.
  • the pixel region further includes a first storage electrode line and a second storage electrode line, the first storage electrode line and the orthographic projection of the first pixel electrode on the substrate substrate at least partially overlapping, The second storage electrode line and the orthographic projection of the second pixel electrode on the substrate substrate at least partially overlap.
  • a gate of the first thin film transistor is disposed in the same layer as a gate of the second thin film transistor, and is electrically connected to the gate line corresponding to the pixel region.
  • a source of the first thin film transistor is disposed in the same layer as a source of the second thin film transistor, and a source between the source of the first thin film transistor and a source of the second thin film transistor is disposed a source connection line electrically connected to a source of the first thin film transistor and a source of the second thin film transistor, and the source connection line intersects the gate line.
  • the source connection line has an active slit, and the source slit is located inside the source connection line.
  • the source connection line has an active slit, and the source slit is located on one side of the source connection line.
  • the gate slit extends beyond the length of the gate cut over the length a region between a gate of the first thin film transistor and a gate of the second thin film transistor, the source slit being located in a region where the source connection line intersects the gate line.
  • the gate slit extends in a length direction of the gate slit beyond a region between a gate of the first thin film transistor and a gate of the second thin film transistor, the source slit is on the substrate An orthographic projection on the substrate is located within the orthographic projection of the gate cut on the substrate.
  • a drain of the first thin film transistor is disposed in the same layer as a drain of the second thin film transistor, and a drain of the first thin film transistor is electrically connected to the first pixel electrode, the second A drain of the thin film transistor is electrically connected to the second pixel electrode.
  • the present invention provides another technical solution: a display device including the above array substrate.
  • the present invention provides a method of fabricating the foregoing display substrate, comprising the steps of sequentially forming a gate line, a data line, and a plurality of pixel regions on a substrate substrate, wherein the pixel region is provided with a first pixel electrode and a second a pixel electrode, the first pixel electrode and the second pixel electrode are oppositely disposed on opposite sides of the gate line corresponding to the pixel region, and are electrically insulated from each other; the pixel region is further provided with a first thin film transistor and a second thin film transistor, the data line is electrically connected to the first pixel electrode through the first thin film transistor, and the data line is electrically connected to the second pixel electrode through the second thin film transistor, the first a gate of the thin film transistor and a gate of the second thin film transistor are respectively located on opposite sides of the gate line corresponding to the pixel region, and are oppositely disposed, wherein
  • the manufacturing method of the display substrate further includes the steps of:
  • a gate cut is formed in a region of the gate line that intersects the data line.
  • the step of forming the gate slit further includes: forming the gate cut along an extending direction of the gate line, and the gate cut is formed to extend at least over the length direction of the gate cut An area where the gate line intersects the data line.
  • the step of forming the gate slit further comprises forming the gate slit to have a width smaller than a width of the gate line.
  • the step of forming the gate slit further includes: forming the gate cut along an extending direction of the gate line, and the gate cut is formed to extend beyond the length in a length direction of the gate cut A region between the gate of a thin film transistor and the gate of the second thin film transistor.
  • the source of the first thin film transistor is disposed in the same layer as the source of the second thin film transistor, wherein the manufacturing method further comprises the steps of:
  • a source connection line between a source of the first thin film transistor and a source of the second thin film transistor, wherein the source connection line is respectively connected to a source of the first thin film transistor and the source A source of the second thin film transistor is electrically connected, and the source connection line crosses the gate line.
  • the manufacturing method further includes: forming a source slit in the source connection line, wherein the source slit is located inside the source connection line, or the source cutout is located at the source connection On one side of the line.
  • the gate slit extends in a length direction of the gate slit beyond a region between a gate of the first thin film transistor and a gate of the second thin film transistor, the source slit being located at the source An area where the connecting line intersects the gate line.
  • the gate cut is formed to extend beyond a region between a gate of the first thin film transistor and a gate of the second thin film transistor in a length direction of the gate cut, the source slit is in the An orthographic projection on the substrate substrate is located within an orthographic projection of the gate cutout on the substrate substrate.
  • the method of manufacturing the same, and the display device provided by the present invention first, by providing a gate slit in a region intersecting the data line on the gate line, the coupling capacitance between the data line and the gate line can be reduced, thereby reducing data.
  • Crosstalk occurs between the line and the gate line to ensure uniform display of the picture;
  • the gate cut extends over the length of the gate cut beyond the area between the first thin film transistor and the second thin film transistor, thereby reducing mutual interference between the first thin film transistor and the second thin film transistor;
  • the source connection line is electrically connected to the source of the first thin film transistor and the source of the second thin film transistor, so that the voltage of the source of the first thin film transistor is consistent with the voltage of the source of the second thin film transistor.
  • the body tube is consistent with the driving of the second thin film transistor; and by opening the source slit on the source connection line, the coupling capacitance between the source connection line and the gate line can be reduced, thereby reducing the source connection line and the gate line. Crosstalk.
  • FIG. 1A is a schematic structural view of a pixel region in an array substrate according to Embodiment 1 of the present invention.
  • FIG. 1B is another schematic structural diagram of a pixel region in an array substrate according to Embodiment 1 of the present invention.
  • Figure 2 is a cross-sectional view taken along line A1-A2 of Figure 1A;
  • FIG. 3 is a schematic structural view of a pixel region in an array substrate according to Embodiment 2 of the present invention.
  • Figure 4 is a cross-sectional view taken along line B1-B2 of Figure 3;
  • FIG. 5 is a schematic structural view of a pixel region in an array substrate according to Embodiment 3 of the present invention.
  • Figure 6 is a cross-sectional view taken along line C1-C2 of Figure 5;
  • FIG. 7 is a schematic structural view of a pixel region in an array substrate according to Embodiment 4 of the present invention.
  • Figure 8 is a cross-sectional view taken along line D1-D2 of Figure 7;
  • FIG. 9 is a schematic structural diagram of a pixel region in an array substrate according to Embodiment 5 of the present invention.
  • Figure 10 is a cross-sectional view taken along line E1-E2 of Figure 9;
  • Fig. 11 is a flow chart showing a method of manufacturing the array substrate of the sixth embodiment of the present invention.
  • the embodiment provides an array substrate in which a gate line is provided with a gate slit in a region crossing the data line and extending along the gate line, thereby reducing a coupling capacitance between the data line and the gate line. Reduce crosstalk between data lines and gate lines.
  • FIG. 1A is a schematic structural view of a pixel region in the array substrate of the present embodiment
  • FIG. 2 is a cross-sectional view taken along line A1-A2 of FIG. 1A
  • the array substrate includes a substrate substrate 14, a gate line 2, a data line 1 and a plurality of pixel regions.
  • the first pixel electrode 5a and the second pixel electrode 5b are disposed in the pixel region, and the first pixel electrode 5a and the second pixel electrode 5b are oppositely disposed on the gate line 2 corresponding to the pixel region.
  • each of the pixel regions is provided with a first thin film transistor and a second thin film transistor, and the data line 1 is electrically connected to the first pixel electrode 5a through the first thin film transistor, and the data line 1 passes through the second
  • the thin film transistor is electrically connected to the second pixel electrode 5b, and the gate electrode 6a of the first thin film transistor and the gate electrode 6b of the second thin film transistor are respectively located on opposite sides of the corresponding gate line 2 of the pixel region, and are oppositely disposed, and the gate line 2 is in the data
  • a region where the line 1 intersects is provided with a gate slit 3 extending in the extending direction of the gate line 2, and the gate slit 3 extends in a length direction of the gate slit 3 beyond a region where the gate line 2 intersects the data line 1, and the length direction of the gate slit 3 is The direction in which the gate lines 2 extend is uniform.
  • FIG. 1B is another schematic structural diagram of a pixel region in the array substrate of the embodiment.
  • the structure of the pixel region of FIG. 1B is different from the structure of the pixel region of FIG. 1A in that the gate slit 3 in FIG. 1B is in the gate cutout 3.
  • the lengthwise direction extends beyond the area where the gate line 2 intersects the data line 1, and extends to a region between the gate 7a of the first thin film transistor and the gate 7b of the second thin film transistor.
  • Such a grid cut 3 is not only advantageous for reducing the coupling capacitance between the gate line 2 and the data line 1, but also for reducing the first film. Interference between the transistor and the second thin film transistor.
  • the data line 1 and the gate line 2 may be formed of a conductive material including Cu, Al, Mo, Ti, Cr or W, and of course, an alloy of the above materials may also be used.
  • the gate line 2 may be a single layer structure or a multilayer structure, such as a multilayer structure of Mo/Al/Mo, a multilayer structure of Ti/Cu/Ti, and a multilayer structure of Mo/Ti/Cu.
  • the width of the gate slit 3 is smaller than the width of the gate line 2, thereby ensuring that the gate line 2 is not broken by the opening of the gate slit 3.
  • the shape of the gate slit 3 is preferably rectangular, and other shapes may of course be employed. Opening the gate slit 3 on the gate line 2 reduces the overlapping area of the gate line 2 and the data line 1, and can reduce the coupling capacitance between the data line 1 and the gate line 2, thereby reducing crosstalk between the data line 1 and the gate line 2.
  • the width direction of the gate slit 3 coincides with the extending direction of the data line 1.
  • the width direction of the gate line 2 coincides with the extending direction of the data line 1.
  • the pixel area of the array substrate further includes two storage electrode lines, which are a first storage electrode line 4a and a second storage electrode line 4b, respectively, and the first storage electrode line 4a and the second storage electrode line 4b are respectively connected to the first pixel electrode 5a.
  • the orthographic projection of the second pixel electrode 5b on the base substrate 14 at least partially overlaps.
  • the first storage electrode line 4a and the second storage electrode line 4b are respectively disposed in parallel with the gate line 2; and, the first storage electrode line 4a and the second storage electrode line 4b are disposed in the same layer as the gate line 2, and the first storage
  • the orthographic projection of the electrode line 4a and the first pixel electrode 5a on the substrate substrate 14 at least partially overlaps; the orthographic projection of the second storage electrode line 4b and the second pixel electrode 5b on the substrate substrate 14 at least partially overlaps.
  • the first pixel electrode 5a and the second pixel electrode 5b When the display device is formed by using the above array substrate, when the voltages of the first storage electrode line 4a and the second storage electrode line 4b in the same pixel region are respectively controlled, between the first storage electrode line 4a and the first pixel electrode 5a Storage capacitance and storage capacitance between the second storage electrode line 4b and the second pixel electrode 5b, the first pixel electrode 5a and the second pixel electrode 5b will generate different voltages, that is, the first pixel electrode 5a and the first The two-pixel electrode 5b drives the respective liquid crystals with different voltages, which can compensate the viewing angle of the entire array substrate and improve the color shift defects.
  • the gate 6a of the first thin film transistor is on the same layer as the gate 6b of the second thin film transistor
  • the gate lines 2 respectively disposed and corresponding to the pixel regions are electrically connected.
  • the source 7a of the first thin film transistor is disposed in the same layer as the source 7b of the second thin film transistor, and is electrically connected to the same data line 1.
  • the drain 8a of the first thin film transistor is disposed in the same layer as the drain 8b of the second thin film transistor, and the drain 8a of the first thin film transistor and the first pixel electrode 5a are electrically connected through the first via 15a on the passivation layer 11.
  • the drain 8b of the second thin film transistor and the second pixel electrode 5b are electrically connected through the second via 15b on the passivation layer 11.
  • the active layer 9a of the first thin film transistor is disposed in the same layer as the active layer 9b of the second thin film transistor.
  • the gate electrode 6a of the first thin film transistor and the active layer 9 (including the active layer 9a of the first thin film transistor and the active layer 9b of the second thin film transistor) and the gate electrode 6b and the active layer of the second thin film transistor
  • a gate insulating layer 10 is disposed between the layers 9 and the gate insulating layer 10 is made of silicon oxide or silicon nitride.
  • the gate insulating layer 10 may be a single layer structure or a multilayer structure such as a silicon oxide/silicon nitride multilayer.
  • the material of the gate insulating layer 10 will be filled in the gate slit 3 during the preparation process.
  • the active layer 9 may be prepared using any one of amorphous silicon, polycrystalline silicon, microcrystalline silicon, and an oxide semiconductor.
  • a passivation layer 11 is disposed between the first thin film transistor and the first pixel electrode 5a in the pixel region and between the second thin film transistor and the second pixel electrode 5b in the pixel region, and the passivation layer 11 can be prepared from an inorganic material.
  • silicon nitride can also be prepared using an organic material such as an organic resin. That is, the passivation layer 11 is provided between the source 7a of the first thin film transistor, the drain 8a and the first pixel electrode 5a, and the source 7b, the drain 8b, and the second pixel electrode 5b of the second thin film transistor.
  • the first pixel electrode 5a and the second pixel electrode 5b in the pixel region are formed of a transparent metal oxide conductive material, and the transparent metal oxide conductive material includes indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the area of the overlapping area of the data line and the gate line can be reduced, and the coupling capacitance between the data line and the gate line can be reduced, thereby reducing Crosstalk occurs between the data line and the gate line to ensure uniform display of the picture.
  • the embodiment provides an array substrate having a structure similar to that of the array substrate of Embodiment 1, which is different from Embodiment 1 in that: in the array substrate of this embodiment, a gate slit is formed on the gate line, and the gate is cut in the gate. The length direction extends beyond the area between the gate of the first thin film transistor and the gate of the second thin film transistor.
  • FIG. 3 is a schematic structural view of a pixel region in the array substrate of the present embodiment.
  • the gate line 2 is opened in a region crossing the data line 1 and along a direction in which the gate line 2 extends.
  • the slit 3, the gate slit 3 extends in the length direction beyond the region between the gate of the first thin film transistor and the gate of the second thin film transistor, and separates the first thin film transistor and the second thin film transistor from the first embodiment. better result.
  • FIG. 4 is a cross-sectional view taken along line B1-B2 of FIG. 3.
  • the gate electrode 6a of the first thin film transistor is disposed in the same layer as the gate electrode 6b of the second thin film transistor, and is electrically connected to the same gate line 2.
  • the gate 6a of the first thin film transistor and the gate 6b of the second thin film transistor are located on different sides of the gate line 2, and a gate cutout 3 is formed in a middle portion of the gate line 2, and the gate insulating layer 10 is filled in the gate cutout 3 s material.
  • the array substrate provided in this embodiment extends the gate slit beyond the area between the first thin film transistor and the second thin film transistor based on the array substrate of the first embodiment, thereby reducing the first thin film transistor and the second thin film transistor. Mutual interference between each other.
  • the present embodiment provides an array substrate having a structure similar to that of the array substrate of the second embodiment, which is different from the second embodiment in that the array substrate of the first embodiment is in the source and the second of the first thin film transistor.
  • a source connection line is disposed between the source of the thin film transistor, and the source connection line is electrically connected to the source of the first thin film transistor and the source of the second thin film transistor, respectively, and the source connection line intersects the gate line.
  • the length of the source connection line is not limited.
  • the length of the source connection line may be greater than the width of the gate line.
  • the length of the source connection line may also be smaller than the width of the gate line, or the length of the source connection line may also be Equal to the width of the gate line.
  • Source cable length direction and data The lines extend in the same direction.
  • FIG. 5 is a schematic structural diagram of a pixel region in the array substrate of the embodiment. As shown in FIG. 5, in the array substrate, an active source is disposed between the source 7a of the first thin film transistor and the source 7b of the second thin film transistor.
  • the pole connection line 12, the source connection line 12 intersects the gate line 2, preferably in a vertical cross arrangement.
  • the source connection line 12 is in the same layer as the source 7a of the first thin film transistor and the source 7b of the second thin film transistor. It is provided that, correspondingly, the active layer 9a of the first thin film transistor is disposed in the same layer as the active layer 9b of the second thin film transistor and connected to each other.
  • the source of the first thin film transistor and the source of the second thin film transistor are electrically connected by providing a source connection line on the basis of the array substrate of the second embodiment, so that the first thin film transistor can be made.
  • the voltage of the source is consistent with the voltage of the source of the second thin film transistor, thereby ensuring the consistency of the driving of the first thin film transistor and the second thin film transistor.
  • the embodiment provides an array substrate having a structure similar to that of the array substrate of the embodiment 3, which is different from the embodiment 3 in that, in the array substrate of the embodiment, the source connection line is provided with an active slit, and the source is cut. Located inside the source cable. Preferably, the source slit is located in a region where the source connection line intersects the gate line. In this embodiment, the region where the source connection line intersects the gate line includes a region where the source connection line and the source slit intersect with the gate line and the gate line, respectively.
  • FIG. 7 is a schematic structural view of a pixel region in the array substrate of the embodiment
  • FIG. 8 is a cross-sectional view taken along line D1-D2 of FIG. 7.
  • the gate slit 3 extends beyond A region between the gate 6a of the first thin film transistor and the gate 6b of the second thin film transistor.
  • An active slit 13 is formed in a region where the source connection line 12 intersects the gate slit 3, and an orthographic projection of the source slit 13 on the base substrate 14 is located in the orthographic projection of the gate slit 3 on the base substrate 14.
  • the area of the region where the source connection line 12 overlaps the gate line 2 can be reduced, and the coupling capacitance between the source connection line and the gate line can be reduced.
  • the width of the source slit 13 is smaller than the width of the source connection line 12 to ensure that the source connection line 12 does not break due to the opening of the active slit 13.
  • the shape of the source slit 13 is preferably square, although other shapes may be employed.
  • the width direction of the source connection line 12 and the source slit 13 coincides with the extending direction of the gate line 2.
  • the coupling capacitance between the source connection line and the gate line can be reduced.
  • crosstalk between the source connection line and the gate line is reduced.
  • the embodiment provides an array substrate having a structure similar to that of the array substrate of the embodiment 4, which is different from the embodiment 4 in that the source substrate has an active slit and a source slit in the array substrate of the embodiment.
  • the source slit is located in a region where the source connection line intersects the gate line.
  • the region where the source connection line intersects the gate line includes a region where the source connection line and the source slit intersect with the gate line and the gate line, respectively.
  • FIG. 9 is a schematic structural view of a pixel region in the array substrate of the present embodiment
  • FIG. 10 is a cross-sectional view taken along line E1-E2 of FIG. 9.
  • the gate slit 3 extends beyond A region between the gate 6a of the first thin film transistor and the gate 6b of the second thin film transistor.
  • An active slit 13 is formed in a region of one side of the source connection line 12 that intersects the gate slit 3, and an orthographic projection of the source slit 13 on the base substrate 14 is located in the orthographic projection of the gate slit 3 on the base substrate 14.
  • the array substrate provided in this embodiment can achieve the same effect as the array substrate of the fourth embodiment.
  • the manufacturing method includes the steps of sequentially forming gate lines, data lines, and a plurality of pixel regions on a substrate. a first pixel electrode and a second pixel electrode disposed in the pixel region, the first pixel electrode and the second pixel electrode Opposite to the two sides of the corresponding gate line of the pixel region, and electrically insulated from each other; the pixel region is further provided with a first thin film transistor and a second thin film transistor, and the data line passes through the first thin film transistor Electrically connecting the first pixel electrode, and the data line is electrically connected to the second pixel electrode through the second thin film transistor, a gate of the first thin film transistor and a gate of the second thin film transistor respectively Located on opposite sides of the corresponding gate line of the pixel area, and oppositely disposed, wherein
  • the manufacturing method of the display substrate further includes the steps of:
  • a gate cut is formed in a region of the gate line that intersects the data line.
  • the step of forming the gate slit further includes: forming the gate cut along an extending direction of the gate line, and the gate cut is formed to extend at least over the length direction of the gate cut An area where the gate line intersects the data line.
  • the step of forming the gate slit further comprises forming the gate slit to have a width smaller than a width of the gate line.
  • the step of forming the gate slit further includes: forming the gate cut along an extending direction of the gate line, and the gate cut is formed to extend beyond the length in a length direction of the gate cut A region between the gate of a thin film transistor and the gate of the second thin film transistor.
  • the source of the first thin film transistor is disposed in the same layer as the source of the second thin film transistor, wherein the manufacturing method further comprises the steps of:
  • a source connection line between a source of the first thin film transistor and a source of the second thin film transistor, wherein the source connection line is respectively connected to a source of the first thin film transistor and the source A source of the second thin film transistor is electrically connected, and the source connection line crosses the gate line.
  • the manufacturing method further includes: forming a source slit in the source connection line, wherein the source slit is located inside the source connection line, or the source slit is located in the source connection line On one side of the side.
  • the gate slit extends in a length direction of the gate slit beyond a region between a gate of the first thin film transistor and a gate of the second thin film transistor, the source slit being located at the source An area where the connecting line intersects the gate line.
  • the gate cut is formed to extend beyond a region between a gate of the first thin film transistor and a gate of the second thin film transistor in a length direction of the gate cut, the source slit is in the An orthographic projection on the substrate substrate is located within an orthographic projection of the gate cutout on the substrate substrate.
  • the area of the overlapping area of the data line and the gate line can be reduced, and the data line and the gate line can be reduced.
  • the coupling capacitance between the two reduces the crosstalk between the data line and the gate line to ensure uniform display of the picture.
  • the voltage of the source of the first thin film transistor and the voltage of the source of the second thin film transistor can be kept consistent. Thereby ensuring the consistency of the driving of the first thin film transistor and the second thin film transistor.
  • the coupling capacitance between the source connection line and the gate line can be reduced, thereby reducing crosstalk between the source connection line and the gate line.
  • the embodiment provides a display device, which includes any of the array substrates of Embodiments 1-5.
  • the display device can be any product or component having a display function, such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the area of the overlapping area of the data line and the gate line can be reduced, the coupling capacitance between the data line and the gate line can be reduced, and crosstalk between the data line and the gate line can be reduced, thereby ensuring uniform display of the picture.

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Abstract

一种阵列基板及其制造方法、显示装置，属于显示技术领域，其可解决现有的阵列基板中数据线（1）与栅线（2）交叉重叠的区域耦合电容过大以及薄膜晶体管之间互相干扰的问题。在阵列基板中，在栅线（2）与数据线（1）交叉的区域开设有栅切口（3）。该阵列基板能够减少数据线（1）与栅线（2）之间的耦合电容；当栅切口（3）延伸超过第一薄膜晶体管与第二薄膜晶体管之间的区域，还能够减少每个像素区的两个薄膜晶体管之间的相互干扰。

Description

阵列基板及其制造方法、显示装置 技术领域
本发明属于显示技术领域，具体涉及阵列基板及其制造方法、显示装置。
背景技术
如今，液晶显示技术已广泛应用于电视、手机、电脑以及公共信息显示屏等设备中。现有的液晶显示面板包括阵列基板，阵列基板包括垂直交叉设置的数据线、栅线和多个像素区，在每个像素区内设置有薄膜晶体管和像素电极，薄膜晶体管的栅极与栅线电连接，薄膜晶体管的漏极与像素电极电连接，薄膜晶体管的源极与数据线电连接，从而可通过数据线和栅线对薄膜晶体管进行驱动，而将数据信号写入像素电极。
现有技术中，为了能够实现宽视角液晶显示，通常在每个像素区内设置两个像素电极，由两个薄膜晶体管分别对两个像素电极进行驱动。
发明人发现现有技术中至少存在如下问题：
1.在数据线与栅线重叠的区域，数据线与栅线之间将产生耦合电容，进而数据线与栅线发生串扰，导致画面显示不均匀；
2.每个像素区的两个薄膜晶体管相互干扰，导致画面质量下降。
发明内容
本发明针对现有的上述技术问题，提供了阵列基板及其制造方法、和显示装置。该阵列基板能够减少数据线与栅线之间的耦合电容，并减少每个像素区的两个薄膜晶体管之间的相互干扰。
解决本发明技术问题所采用的技术方案是：一种阵列基板，包括衬底基板、栅线、数据线和多个像素区，所述像素区内设置有第一像素电极和第二像素电极，所述第一像素电极与所述第二 像素电极相对设置于所述像素区对应的所述栅线的两侧、且互相电绝缘；所述像素区还设置有第一薄膜晶体管和第二薄膜晶体管，所述数据线通过所述第一薄膜晶体管电连接所述第一像素电极，且所述数据线通过所述第二薄膜晶体管电连接所述第二像素电极，所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极分别位于所述像素区对应的所述栅线的两侧、且相对设置，其中，所述栅线在与所述数据线交叉的区域设有栅切口。
优选地是，所述栅切口沿所述栅线的延伸方向开设，所述栅切口在所述栅切口的长度方向上至少延伸超过所述栅线与所述数据线交叉的区域。
优选的是，所述栅切口的宽度小于所述栅线的宽度。
优选的是，所述栅切口沿所述栅线的延伸方向开设，所述栅切口在所述栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域。
优选的是，所述像素区还包括第一存储电极线和第二存储电极线，所述第一存储电极线与所述第一像素电极在所述衬底基板上的正投影至少部分重叠,所述第二存储电极线与所述第二像素电极在所述衬底基板上的正投影至少部分重叠。
优选的是，所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极同层设置、且分别与所述像素区对应的所述栅线电连接。
优选的是，所述第一薄膜晶体管的源极与所述第二薄膜晶体管的源极同层设置，所述第一薄膜晶体管的源极与所述第二薄膜晶体管的源极之间设置有源极连接线，所述源极连接线分别与所述第一薄膜晶体管的源极和所述第二薄膜晶体管的源极电连接，所述源极连接线与所述栅线交叉。
优选的是，所述源极连接线开设有源切口，所述源切口位于所述源极连接线的内部。
优选的是，所述源极连接线开设有源切口，所述源切口位于所述源极连接线的一个侧边上。
优选的是，所述栅切口在栅切口的长度方向上延伸超过所述 第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域，所述源切口位于所述源极连接线与所述栅线交叉的区域。
优选的是，所述栅切口在栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域，所述源切口在所述衬底基板上的正投影位于所述栅切口在所述衬底基板上的正投影内。
优选的是，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的漏极同层设置，所述第一薄膜晶体管的漏极与所述第一像素电极电连接，所述第二薄膜晶体管的漏极与所述第二像素电极电连接。
本发明提供另一技术方案：一种显示装置，包括上述阵列基板。
本发明提供了一种前述显示基板的制造方法，包括在衬底基板上顺序形成栅线、数据线和多个像素区的步骤，其中，所述像素区内设置有第一像素电极和第二像素电极，所述第一像素电极与所述第二像素电极相对设置于所述像素区对应的所述栅线的两侧、且互相电绝缘；所述像素区还设置有第一薄膜晶体管和第二薄膜晶体管，所述数据线通过所述第一薄膜晶体管电连接所述第一像素电极，且所述数据线通过所述第二薄膜晶体管电连接所述第二像素电极，所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极分别位于所述像素区对应的所述栅线的两侧、且相对设置，其中
所述显示基板的制造方法还包括步骤：
在所述栅线上与所述数据线交叉的区域中形成栅切口。
优选地是，形成所述栅切口的步骤进一步包括：沿所述栅线的延伸方向形成所述栅切口，且所述栅切口被形成为在所述栅切口的长度方向上至少延伸超过所述栅线与所述数据线交叉的区域。
优选的是，形成所述栅切口的步骤进一步包括：将所述栅切口形成为其宽度小于所述栅线的宽度。
优选的是，形成所述栅切口的步骤进一步包括：沿所述栅线的延伸方向形成所述栅切口，且所述栅切口被形成为在所述栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域。
优选的是，所述第一薄膜晶体管的源极与所述第二薄膜晶体管的源极同层设置，其中所述制造方法进一步包括步骤：
在所述第一薄膜晶体管的源极与所述第二薄膜晶体管的源极之间形成源极连接线，其中，所述源极连接线分别与所述第一薄膜晶体管的源极和所述第二薄膜晶体管的源极电连接，所述源极连接线与所述栅线交叉。
优选的是，所述制造方法进一步包括：在所述源极连接线中形成源切口，其中，所述源切口位于所述源极连接线的内部，或所述源切口位于所述源极连接线的一个侧边上。
优选的是，所述栅切口在栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域，所述源切口位于所述源极连接线与所述栅线交叉的区域。
优选的是，所述栅切口被形成为在栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域，所述源切口在所述衬底基板上的正投影位于所述栅切口在所述衬底基板上的正投影内。
在本发明提供的阵列基板及其制造方法、显示装置中，首先，通过在栅线上与数据线交叉的区域开设有栅切口，能够减少数据线与栅线之间的耦合电容，进而减少数据线与栅线发生串扰，保证画面均匀显示；
其次，将栅切口在栅切口的长度方向上延伸超过第一薄膜晶体管与第二薄膜晶体管之间的区域，从而能够减少第一薄膜晶体管与第二薄膜晶体管之间的相互干扰；
最后，设置源极连接线将第一薄膜晶体管的源极与第二薄膜晶体管的源极电连接，能够使第一薄膜晶体管的源极的电压与第二薄膜晶体管的源极的电压时刻保持一致，从而保证第一薄膜晶 体管与第二薄膜晶体管驱动的一致性；并且，通过在源极连接线上开设源切口，能够减少源极连接线与栅线之间的耦合电容，进而减少源极连接线与栅线发生串扰。
附图说明
图1A为本发明的实施例1的阵列基板中一个像素区的一种结构示意图；
图1B为本发明的实施例1的阵列基板中一个像素区的另一种结构示意图；
图2为图1A中沿A1-A2线的剖视图；
图3为本发明的实施例2的阵列基板中一个像素区的结构示意图；
图4为图3中沿B1-B2线的剖视图；
图5为本发明的实施例3的阵列基板中一个像素区的结构示意图；
图6为图5中沿C1-C2线的剖视图；
图7为本发明的实施例4的阵列基板中一个像素区的结构示意图；
图8为图7中沿D1-D2线的剖视图；
图9为本发明的实施例5的阵列基板中一个像素区的结构示意图；
图10为图9中沿E1-E2线的剖视图；以及
图11是本发明的实施例6的阵列基板的制造方法的流程图。
其中，附图标记为：
1、数据线；2、栅线；3、栅切口；4a、第一存储电极线；4b、第二存储电极线；5a、第一像素电极；5b、第二像素电极；6a、第一薄膜晶体管的栅极；6b、第二薄膜晶体管的栅极；7a、第一薄膜晶体管的源极；7b、第二薄膜晶体管的源极；8a、第一薄膜晶体管的漏极；8b、第二薄膜晶体管的漏极；9a、第一薄膜晶体管的有源层；9b、第二薄膜晶体管的有源层；9、有源层；10、栅 绝缘层；11、钝化层；12、源极连接线；13、源切口；14、衬底基板；15a、第一过孔；15b、第二过孔。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
本实施例提供一种阵列基板，在该阵列基板中，栅线在与数据线交叉的区域、沿栅线的延伸方向开设有栅切口，能够减少数据线与栅线之间的耦合电容，进而减少数据线与栅线发生串扰。
图1A为本实施例的阵列基板中一个像素区的一种结构示意图，图2为图1A中沿A1-A2线的剖视图，如图1A、图2所示，阵列基板包括衬底基板14、栅线2、数据线1和多个像素区，像素区内设置第一像素电极5a和第二像素电极5b，第一像素电极5a与第二像素电极5b相对设置于像素区对应的栅线2的两侧、且互相电绝缘；每一像素区内均设置有第一薄膜晶体管和第二薄膜晶体管，数据线1通过第一薄膜晶体管电连接第一像素电极5a，且数据线1通过第二薄膜晶体管电连接第二像素电极5b，第一薄膜晶体管的栅极6a与第二薄膜晶体管的栅极6b分别位于像素区对应的栅线2的两侧、且相对设置，栅线2在与数据线1交叉的区域、沿栅线2的延伸方向开设有栅切口3，栅切口3在栅切口3的长度方向上延伸超过栅线2与数据线1交叉的区域，栅切口3的长度方向与栅线2的延伸方向一致。
图1B为本实施例的阵列基板中一个像素区的另一种结构示意图，图1B的像素区的结构与图1A的像素区的结构的区别在于，图1B中的栅切口3在栅切口3的长度方向上延伸超过栅线2与数据线1交叉的区域，且延伸至了第一薄膜晶体管的栅极7a与第二薄膜晶体管的栅极7b之间的区域。这样设置栅切口3不仅有利于减小栅线2与数据线1之间的耦合电容，还有利于减小第一薄膜 晶体管与第二薄膜晶体管之间的干扰。
具体的，数据线1和栅线2可以采用导电材料形成，导电材料包括Cu、Al、Mo、Ti、Cr或W，当然也可采用上述材料的合金形成。其中，栅线2可以是单层结构，也可以是多层结构，例如Mo/Al/Mo的多层结构、Ti/Cu/Ti的多层结构、Mo/Ti/Cu的多层结构。
栅切口3的宽度小于栅线2的宽度，从而保证栅线2不会因为开设了栅切口3而断裂，栅切口3的形状优选为长方形，当然也可以采用其他形状。栅线2上开设栅切口3使栅线2与数据线1的重叠面积减小，能够减少数据线1与栅线2之间的耦合电容，进而减少数据线1与栅线2发生串扰。栅切口3的宽度方向与数据线1的延伸方向一致。栅线2的宽度方向与数据线1的延伸方向一致。
该阵列基板的像素区还包括两条存储电极线，分别为第一存储电极线4a和第二存储电极线4b，第一存储电极线4a和第二存储电极线4b分别与第一像素电极5a和第二像素电极5b在衬底基板14上的正投影至少部分重叠。
具体的，第一存储电极线4a和第二存储电极线4b分别与栅线2平行设置；并且，第一存储电极线4a和第二存储电极线4b与栅线2同层设置，第一存储电极线4a与第一像素电极5a在衬底基板14上的正投影至少部分重叠；第二存储电极线4b与第二像素电极5b在衬底基板14上的正投影至少部分重叠。
采用上述阵列基板形成显示装置时，当对同一像素区内的第一存储电极线4a和第二存储电极线4b电压分别进行控制时，通过第一存储电极线4a与第一像素电极5a之间的存储电容和第二存储电极线4b与第二像素电极5b之间的存储电容，第一像素电极5a与第二像素电极5b将产生不同的电压，也就是说，第一像素电极5a与第二像素电极5b采用不同的电压驱动各自对应的液晶，这样可补偿整个阵列基板显示的视角、改善色偏缺陷。
第一薄膜晶体管的栅极6a与第二薄膜晶体管的栅极6b同层 设置、且分别与像素区对应的栅线2电连接。第一薄膜晶体管的源极7a与第二薄膜晶体管的源极7b同层设置、且与同一数据线1电连接。第一薄膜晶体管的漏极8a与第二薄膜晶体管的漏极8b同层设置，第一薄膜晶体管的漏极8a与第一像素电极5a通过钝化层11上的第一过孔15a电连接，第二薄膜晶体管的漏极8b与第二像素电极5b通过钝化层11上的第二过孔15b电连接。
第一薄膜晶体管的有源层9a与第二薄膜晶体管的有源层9b同层设置。
第一薄膜晶体管的栅极6a与有源层9(包括第一薄膜晶体管的有源层9a和第二薄膜晶体管的有源层9b)之间以及第二薄膜晶体管的栅极6b与有源层9之间设置有栅绝缘层10，栅绝缘层10采用氧化硅或氮化硅制备，栅绝缘层10可以是单层结构，也可以是多层结构，例如氧化硅/氮化硅的多层结构，同时，由于栅绝缘层10形成在栅线2上方，在制备过程中，栅切口3内将填入栅绝缘层10的材料。此外，有源层9可采用非晶硅、多晶硅、微晶硅、氧化物半导体中的任一种材料制备。
第一薄膜晶体管与像素区内的第一像素电极5a之间以及第二薄膜晶体管与像素区内的第二像素电极5b之间设置有钝化层11，钝化层11可以采用无机物材料制备，例如氮化硅，也可以采用有机物材料制备，例如有机树脂。也就是说，钝化层11设置在第一薄膜晶体管的源极7a、漏极8a与第一像素电极5a以及第二薄膜晶体管的源极7b、漏极8b与第二像素电极5b之间。其中，像素区内的第一像素电极5a和第二像素电极5b采用透明金属氧化物导电材料形成，透明金属氧化物导电材料包括氧化铟锡(ITO)或氧化铟锌(IZO)。
本实施例提供的阵列基板，通过在栅线上与数据线交叉的区域开设有栅切口，能够减少数据线与栅线的重叠区域面积，减少数据线与栅线之间的耦合电容，进而减少数据线与栅线发生串扰，保证画面均匀显示。
实施例2：
本实施例提供一种阵列基板，其具有与实施例1的阵列基板类似的结构，其与实施例1的区别在于：本实施例的阵列基板中，栅线上开设的栅切口，在栅切口的长度方向上延伸超过了第一薄膜晶体管的栅极与第二薄膜晶体管的栅极之间的区域。
图3为本实施例的阵列基板中一个像素区的结构示意图，如图3所示，在阵列基板中，栅线2在与数据线1交叉的区域、沿栅线2的延伸方向开设有栅切口3，栅切口3在长度方向上延伸超过了第一薄膜晶体管的栅极与第二薄膜晶体管的栅极之间的区域，相比实施例1，分隔第一薄膜晶体管和第二薄膜晶体管的效果更好。
图4为图3中沿B1-B2线的剖视图，如图4所示，第一薄膜晶体管的栅极6a与第二薄膜晶体管的栅极6b同层设置、且与同一栅线2电连接。其中，第一薄膜晶体管的栅极6a与第二薄膜晶体管的栅极6b位于栅线2的不同侧，且栅线2的中部开设有栅切口3，栅切口3内填入有栅绝缘层10的材料。
本实施例提供的阵列基板，在实施例1的阵列基板的基础上，将栅切口延伸超过第一薄膜晶体管与第二薄膜晶体管之间的区域，从而能够减少第一薄膜晶体管与第二薄膜晶体管之间的相互干扰。
实施例3：
本实施例提供一种阵列基板，其具有与实施例2的阵列基板类似的结构，其与实施例2的区别在于：本实施例的阵列基板中，在第一薄膜晶体管的源极与第二薄膜晶体管的源极之间设置有源极连接线，源极连接线分别与第一薄膜晶体管的源极和第二薄膜晶体管的源极电连接，源极连接线与栅线交叉。本实施例并不对源极连接线的长度进行限制，源极连接线的长度可以大于栅线的宽度，源极连接线的长度也可以小于栅线的宽度，或者源极连接线的长度也可以等于栅线的宽度。源极连接线的长度方向与数据 线的延伸方向一致。
图5为本实施例的阵列基板中一个像素区的结构示意图，如图5所示，在阵列基板中，第一薄膜晶体管的源极7a与第二薄膜晶体管的源极7b之间设置有源极连接线12，源极连接线12与栅线2交叉，优选为垂直交叉设置。
图6为图5中沿C1-C2线的剖视图，如图6所示，在阵列基板中，源极连接线12与第一薄膜晶体管的源极7a和第二薄膜晶体管的源极7b同层设置，相应的，第一薄膜晶体管的有源层9a与第二薄膜晶体管的有源层9b同层设置、且相互连接。
本实施例提供的阵列基板，在实施例2的阵列基板的基础上，通过设置源极连接线将第一薄膜晶体管的源极与第二薄膜晶体管的源极电连接，能够使第一薄膜晶体管的源极的电压与第二薄膜晶体管的源极的电压时刻保持一致，从而保证第一薄膜晶体管与第二薄膜晶体管驱动的一致性。
实施例4：
本实施例提供一种阵列基板，其具有与实施例3的阵列基板类似的结构，其与实施例3的区别在于：本实施例的阵列基板中，源极连接线开设有源切口，源切口位于源极连接线的内部。优选地，源切口位于源极连接线与栅线交叉的区域。本实施例中，源极连接线与栅线交叉的区域包括源极连接线和源切口分别与栅线和栅切口交叉的区域。
图7为本实施例的阵列基板中一个像素区的结构示意图，图8为图7中沿D1-D2线的剖视图，如图7、图8所示，在阵列基板中，栅切口3延伸超过第一薄膜晶体管的栅极6a与第二薄膜晶体管的栅极6b之间的区域。源极连接线12与栅切口3交叉的区域开设有源切口13，源切口13在衬底基板14上的正投影位于栅切口3在衬底基板14上的正投影内。这样，能够减小源极连接线12与栅线2重叠区域的面积，进而减少源极连接线与栅线之间的耦合电容。
同时，源切口13的宽度小于源极连接线12的宽度，以保证源极连接线12不会因为开设有源切口13而造成断裂。源切口13的形状优选为方形，当然也可以采用其他形状。源极连接线12和源切口13的宽度方向与栅线2的延伸方向一致。
本实施例提供的阵列基板，在实施例3的阵列基板的基础上，通过在源极连接线与栅线交叉的区域开设源切口，能够减少源极连接线与栅线之间的耦合电容，进而减少源极连接线与栅线发生串扰。
实施例5：
本实施例提供一种阵列基板，其具有与实施例4的阵列基板类似的结构，其与实施例4的区别在于：本实施例的阵列基板中，源极连接线开设有源切口，源切口位于源极连接线的一个侧边上。优选地，源切口位于源极连接线与栅线交叉的区域。本实施例中，源极连接线与栅线交叉的区域包括源极连接线和源切口分别与栅线和栅切口交叉的区域。
图9为本实施例的阵列基板中一个像素区的结构示意图，图10为图9中沿E1-E2线的剖视图，如图9、图10所示，在阵列基板中，栅切口3延伸超过第一薄膜晶体管的栅极6a与第二薄膜晶体管的栅极6b之间的区域。源极连接线12的一个侧边上与栅切口3交叉的区域开设有源切口13，源切口13在衬底基板14上的正投影位于栅切口3在衬底基板14上的正投影内。
本实施例提供的阵列基板能够起到与实施例4的阵列基板相同的效果。
实施例6：
本实施例提供一种前述任一实施例中的阵列基板的制造方法，如图11所示，该制造方法包括在衬底基板上顺序形成栅线、数据线和多个像素区的步骤，其中，所述像素区内设置有第一像素电极和第二像素电极，所述第一像素电极与所述第二像素电极 相对设置于所述像素区对应的所述栅线的两侧、且互相电绝缘；所述像素区还设置有第一薄膜晶体管和第二薄膜晶体管，所述数据线通过所述第一薄膜晶体管电连接所述第一像素电极，且所述数据线通过所述第二薄膜晶体管电连接所述第二像素电极，所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极分别位于所述像素区对应的所述栅线的两侧、且相对设置，其中
所述显示基板的制造方法还包括步骤：
在所述栅线上与所述数据线交叉的区域中形成栅切口。
优选地是，形成所述栅切口的步骤进一步包括：沿所述栅线的延伸方向形成所述栅切口，且所述栅切口被形成为在所述栅切口的长度方向上至少延伸超过所述栅线与所述数据线交叉的区域。
优选的是，形成所述栅切口的步骤进一步包括：将所述栅切口形成为其宽度小于所述栅线的宽度。
优选的是，形成所述栅切口的步骤进一步包括：沿所述栅线的延伸方向形成所述栅切口，且所述栅切口被形成为在所述栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域。
优选的是，所述第一薄膜晶体管的源极与所述第二薄膜晶体管的源极同层设置，其中所述制造方法进一步包括步骤：
在所述第一薄膜晶体管的源极与所述第二薄膜晶体管的源极之间形成源极连接线，其中，所述源极连接线分别与所述第一薄膜晶体管的源极和所述第二薄膜晶体管的源极电连接，所述源极连接线与所述栅线交叉。
优选的是，所述制造方法进一步包括：在所述源极连接线形成源切口，其中，所述源切口位于所述源极连接线的内部，或所述源切口位于所述源极连接线的一个侧边上。
优选的是，所述栅切口在栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域，所述源切口位于所述源极连接线与所述栅线交叉的区域。
优选的是，所述栅切口被形成为在栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域，所述源切口在所述衬底基板上的正投影位于所述栅切口在所述衬底基板上的正投影内。
本实施例提供的阵列基板的制造方法中，通过在栅线和数据线交叉的区域中在栅线上开设栅切口，能够减少数据线与栅线的重叠区域面积，减少数据线与栅线之间的耦合电容，进而减少数据线与栅线发生串扰，保证画面均匀显示。通过将栅切口延伸超过第一薄膜晶体管与第二薄膜晶体管之间的区域，从而能够减少第一薄膜晶体管与第二薄膜晶体管之间的相互干扰。通过设置源极连接线将第一薄膜晶体管的源极与第二薄膜晶体管的源极电连接，能够使第一薄膜晶体管的源极的电压与第二薄膜晶体管的源极的电压时刻保持一致，从而保证第一薄膜晶体管与第二薄膜晶体管驱动的一致性。通过在源极连接线与栅线交叉的区域开设源切口，能够减少源极连接线与栅线之间的耦合电容，进而减少源极连接线与栅线发生串扰。
实施例7：
本实施例提供一种显示装置，该显示装置包括实施例1-5中任一种阵列基板。
该显示装置可以为：液晶显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实施例的显示装置，能够减少数据线与栅线的重叠区域面积，减少数据线与栅线之间的耦合电容，进而减少数据线与栅线发生串扰，保证画面均匀显示。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况 下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (22)

  1. 一种阵列基板，包括衬底基板、栅线、数据线和多个像素区，其特征在于，所述像素区内设置有第一像素电极和第二像素电极，所述第一像素电极与所述第二像素电极相对设置于所述像素区对应的所述栅线的两侧、且互相电绝缘；所述像素区还设置有第一薄膜晶体管和第二薄膜晶体管，所述数据线通过所述第一薄膜晶体管电连接所述第一像素电极，且所述数据线通过所述第二薄膜晶体管电连接所述第二像素电极，所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极分别位于所述像素区对应的所述栅线的两侧、且相对设置，所述栅线在与所述数据线交叉的区域设有栅切口。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述栅切口沿所述栅线的延伸方向开设，所述栅切口在所述栅切口的长度方向上至少延伸超过所述栅线与所述数据线交叉的区域。
  3. 根据权利要求1或2所述的阵列基板，其特征在于，所述栅切口的宽度小于所述栅线的宽度。
  4. 根据权利要求1所述的阵列基板，其特征在于，所述栅切口沿所述栅线的延伸方向开设，所述栅切口在所述栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域。
  5. 根据权利要求1所述的阵列基板，其特征在于，所述像素区还包括第一存储电极线和第二存储电极线，所述第一存储电极线与所述第一像素电极在所述衬底基板上的正投影至少部分重叠,所述第二存储电极线与所述第二像素电极在所述衬底基板上的正投影至少部分重叠。
  6. 根据权利要求1所述的阵列基板，其特征在于，所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极同层设置、且分别与所述像素区对应的所述栅线电连接。
  7. 根据权利要求1所述的阵列基板，其特征在于，所述第一薄膜晶体管的源极与所述第二薄膜晶体管的源极同层设置，所述第一薄膜晶体管的源极与所述第二薄膜晶体管的源极之间设置有源极连接线，所述源极连接线分别与所述第一薄膜晶体管的源极和所述第二薄膜晶体管的源极电连接，所述源极连接线与所述栅线交叉。
  8. 根据权利要求7所述的阵列基板，其特征在于，所述源极连接线开设有源切口，所述源切口位于所述源极连接线的内部。
  9. 根据权利要求7所述的阵列基板，其特征在于，所述源极连接线开设有源切口，所述源切口位于所述源极连接线的一个侧边上。
  10. 根据权利要求8或9所述的阵列基板，其特征在于，所述栅切口在栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域，所述源切口位于所述源极连接线与所述栅线交叉的区域。
  11. 根据权利要求8或9所述的阵列基板，其特征在于，所述栅切口在栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域，所述源切口在所述衬底基板上的正投影位于所述栅切口在所述衬底基板上的正投影内。
  12. 根据权利要求1-9任一所述的阵列基板，其特征在于，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的漏极同层设置，所述第一薄膜晶体管的漏极与所述第一像素电极电连接，所述第二薄膜晶体管的漏极与所述第二像素电极电连接。
  13. 一种显示装置，其特征在于，包括权利要求1-12任一所述的阵列基板。
  14. 一种显示基板的制造方法，其特征在于，包括在衬底基板上顺序形成栅线、数据线和多个像素区的步骤，其中，所述像素区内设置有第一像素电极和第二像素电极，所述第一像素电极与所述第二像素电极相对设置于所述像素区对应的所述栅线的两侧、且互相电绝缘；所述像素区还设置有第一薄膜晶体管和第二薄膜晶体管，所述数据线通过所述第一薄膜晶体管电连接所述第一像素电极，且所述数据线通过所述第二薄膜晶体管电连接所述第二像素电极，所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极分别位于所述像素区对应的所述栅线的两侧、且相对设置，其中
    所述显示基板的制造方法还包括步骤：
    在所述栅线上与所述数据线交叉的区域中形成栅切口。
  15. 根据权利要求14所述的制造方法，其特征在于，形成所述栅切口的步骤进一步包括：
    沿所述栅线的延伸方向形成所述栅切口，且所述栅切口被形成为在所述栅切口的长度方向上至少延伸超过所述栅线与所述数据线交叉的区域。
  16. 根据权利要求14或15所述的制造方法，其特征在于，形成所述栅切口的步骤进一步包括：将所述栅切口形成为其宽度小于所述栅线的宽度。
  17. 根据权利要求14所述的制造方法，其特征在于，形成所述栅切口的步骤进一步包括：
    沿所述栅线的延伸方向形成所述栅切口，且所述栅切口被形成为在所述栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域。
  18. 根据权利要求14所述的制造方法，其特征在于，所述第一薄膜晶体管的源极与所述第二薄膜晶体管的源极同层设置，其中，所述制造方法进一步包括步骤：
    在所述第一薄膜晶体管的源极与所述第二薄膜晶体管的源极之间形成源极连接线，所述源极连接线分别与所述第一薄膜晶体管的源极和所述第二薄膜晶体管的源极电连接，所述源极连接线与所述栅线交叉。
  19. 根据权利要求18所述的制造方法，其特征在于，所述制造方法进一步包括：
    在所述源极连接线形成源切口，其中，所述源切口位于所述源极连接线的内部。
  20. 根据权利要求18所述的制造方法，其特征在于，所述制造方法进一步包括：
    所述源切口位于所述源极连接线的一个侧边上。
  21. 根据权利要求19所述的制造方法，其特征在于，所述栅切口被形成为在栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域，且所述源切口位于所述源极连接线与所述栅线交叉的区域。
  22. 根据权利要求19所述的制造方法，其特征在于，所述栅 切口被形成为在栅切口的长度方向上延伸超过所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极之间的区域，且所述源切口在所述衬底基板上的正投影位于所述栅切口在所述衬底基板上的正投影内。
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