CN114068589A - 阵列基板、阵列基板的制作方法及显示面板 - Google Patents

阵列基板、阵列基板的制作方法及显示面板 Download PDF

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CN114068589A
CN114068589A CN202110906207.5A CN202110906207A CN114068589A CN 114068589 A CN114068589 A CN 114068589A CN 202110906207 A CN202110906207 A CN 202110906207A CN 114068589 A CN114068589 A CN 114068589A
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gate
layer
grid electrode
line
insulating layer
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江志雄
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TCL Huaxing Photoelectric Technology Co Ltd
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TCL Huaxing Photoelectric Technology Co Ltd
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Priority to CN202110906207.5A priority Critical patent/CN114068589A/zh
Priority to PCT/CN2021/115291 priority patent/WO2023015620A1/zh
Priority to US17/600,254 priority patent/US20230215872A1/en
Publication of CN114068589A publication Critical patent/CN114068589A/zh
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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Abstract

本申请提供一种阵列基板、阵列基板的制作方法及显示面板。阵列基板包括基板和设置在基板上的薄膜晶体管层，薄膜晶体管层包括多个薄膜晶体管，薄膜晶体管包括有源层、与有源层电连接的源漏极、与有源层对应的第一栅极和第二栅极；第一栅极和第二栅极之间设有第一绝缘层，第一绝缘层上开设有通孔，第一栅极和第二栅极通过通孔电连接。通过在阵列基板中设置层叠的第一栅极和第二栅极，并使第一栅极和第二栅极电连接，在减小了薄膜晶体管栅极电阻的同时，也避免了制作一层较厚的栅极时导致的蚀刻困难和蚀刻时间过长的问题。

Description

阵列基板、阵列基板的制作方法及显示面板
技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板、阵列基板的制作方法及显示面板。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)液晶显示面板具有体积小、对比度高等优点，普遍应用于手机、电视、电脑等电子产品中。TFT中通常包括栅极，源漏极和有源层。随着对分辨率需求的提升，TFT中栅极占比越来越大，从而导致电阻电容延迟成倍增大，进而导致错充电压过高而出现显示异常。
发明内容
本申请提供一种阵列基板、阵列基板的制作方法及显示面板，旨在解决现有的阵列基板中电阻电容延迟过大导致错充电压过高而出现显示异常的问题。
第一方面，本申请提供一种阵列基板，所述阵列基板包括：
基板；
薄膜晶体管层，设置在所述基板上，所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管包括有源层、与所述有源层电连接的源漏极、与所述有源层对应的第一栅极和第二栅极，所述第一栅极和所述第二栅极之间设有第一绝缘层，所述第一绝缘层上开设有通孔，所述第一栅极和所述第二栅极通过所述通孔电连接。
可选的，所述薄膜晶体管层包括第一栅极线和数据线，所述第一栅极线与所述第一栅极电连接且同层设置，所述数据线与所述源漏极电连接且同层设置；所述第一栅极线和所述数据线错开设置。
可选的，所述薄膜晶体管层包括第二栅极线，所述第二栅极线与所述第二栅极电连接且同层设置，所述第二栅极线与所述数据线交叉；
所述第一栅极线和所述第二栅极线至少部分重叠，所述第一栅极线在所述第二栅极线与所述数据线交叉处断开。
可选的，所述第一栅极和所述有源层之间设有第二绝缘层；
所述第二栅极线、所述第一绝缘层、所述第一栅极线、所述第二绝缘层、所述有源层以及所述数据线层叠地设置在所述基板上，所述第一栅极与所述有源层的位置对应。
可选的，所述第二栅极和所述有源层之间设有第二绝缘层；
所述有源层、所述第二绝缘层、所述第二栅极线、所述第一绝缘层、所述第一栅极线以及所述数据线依次层叠地设置在所述基板上，所述第二栅极与所述有源层的位置对应。
可选的，所述第一绝缘层的厚度大于或者等于所述第二绝缘层的厚度。
可选的，所述第一栅极线的厚度大于或者等于所述第二栅极线的厚度。
可选的，所述通孔与所述第一栅极的位置对应。
第二方面，本申请提供一种阵列基板的制作方法，包括如下步骤：
提供一基板；
在所述基板上制作第二栅极和第二栅极线，所述第二栅极和第二栅极线电连接且同层设置；
在所述第二栅极和第二栅极线上制作第一绝缘层，并在所述第一绝缘层上开设通孔；
在所述第一绝缘层上制作第一栅极和第一栅极线，并使所述第一栅极穿过所述通孔与所述第二栅极电连接，所述第一栅极线与所述第一栅极电连接且同层设置；
在所述第一栅极和第一栅极线上制作第二绝缘层；
在所述第二绝缘层上制作有源层；
在所述有源层上制作源漏极和数据线，所述数据线与所述源漏极中的源极电连接且同层设置。
可选的，所述第一栅极线设置有隔断区域，所述在所述有源层上制作源漏极和数据线的步骤中，包括：
在所述有源层上沉积金属层；
图案化所述金属层形成源漏极和数据线，所述数据线与所述隔断区域至少部分重叠。
第三方面，本申请提供一种显示面板，所述显示面板包括本申请实施方案中的阵列基板。
本申请提供一种阵列基板、阵列基板的制作方法及显示面板。阵列基板包括基板和设置在基板上的薄膜晶体管层，薄膜晶体管层包括多个薄膜晶体管，薄膜晶体管包括有源层、与有源层电连接的源漏极、与有源层对应的第一栅极和第二栅极；第一栅极和第二栅极之间设有第一绝缘层，第一绝缘层上开设有通孔，第一栅极和第二栅极通过通孔电连接。通过在阵列基板中设置层叠的第一栅极和第二栅极，并使第一栅极和第二栅极电连接，增加了薄膜晶体管栅极的厚度，减小栅极电阻，从而避免电阻电容延迟过大导致错充电压过高而出现显示异常的问题。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请第一实施例提供的阵列基板的结构示意图；
图2为本申请第二实施例提供的阵列基板的结构示意图；
图3为本申请实施例中阵列基板的平面结构示意图；
图4为本申请实施例中阵列基板的制作方法流程图；
图5为图4中步骤S4的流程示意图。
Figure BDA0003201719110000031
Figure BDA0003201719110000041
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
首先，本申请提供一种阵列基板10。结合图1和图2，阵列基板10包括基板11和设置在基板11上的薄膜晶体管层12，薄膜晶体管层12包括多个薄膜晶体管120。薄膜晶体管120是阵列基板10的主要构成器件，用于控制像素的开启和关闭。可以理解的是，薄膜晶体管120的数量可以根据实际情况进行确定，此处不作限定。
薄膜晶体管120包括有源层1204、与有源层1204电连接的源漏极1203、与有源层1204对应的第一栅极1201和第二栅极1202。其中，源漏极1203包括源极1203a和漏极1203b。第一栅极1201和第二栅极1202层叠间隔设置，第一栅极1201和第二栅极1202之间设有第一绝缘层1211，第一绝缘层1211上开设有通孔1210，第一栅极1201和第二栅极1202通过通孔1210电连接。
为了减少栅极驱动信号的电阻电容延迟(RC delay)，需要减小薄膜晶体管120中栅极的电阻。现有技术中通常采用增加栅极厚度、并使用铜作为栅极材料以减小其电阻的方式。在制作栅极时，通常是先沉积一层金属层，然后对其进行图案化刻蚀。然而，铜的刻蚀较为困难，尤其时当栅极厚度增加时，更增加了刻蚀的时间和难度，使得阵列基板10的制造成本增加。
通过在阵列基板10的薄膜晶体管120中层叠设置第一栅极1201和第二栅极1202，在制程中可以相继沉积两层金属层，并分别对两层金属层刻蚀以形成第一栅极1201和第二栅极1202。和刻蚀一层较厚的金属层以形成栅极的方式相比，减少了制作时间，刻蚀也相对容易。另外，第一栅极1201和第二栅极1202之间设有第一绝缘层1211，第一栅极1201和第二栅极1202通过第一绝缘层1211上的通孔1210实现电连接，相当于增加薄膜晶体管120中栅极的厚度，减小了其电阻，由此实现了减小栅极驱动信号的电阻电容延迟。
第一绝缘层1211的材料可以是氧化硅或者氮化硅等具有良好绝缘性能的材料。通孔1210可通过光刻方式在第一绝缘层1211上形成。需要说明的是，通孔1210的位置可以根据实际情况进行确定，此处不作限定。
由于第一栅极1201是穿过通孔1210与第二栅极1202连接，通孔1210的位置决定了第一栅极1201的走线方式以及第一栅极1201与第二栅极1202之间的连接性。优选的，结合图1和图2，在本申请实施例中通孔1210与第一栅极1201的位置对应，即通孔1210在沿阵列基板10厚度上的正投影全部落在第一栅极1201上。通孔1210贯穿第一绝缘层1211并延伸至第二栅极1202，以使第一栅极1201能够穿过通孔1210与第二栅极1202连接。由此，简化了第一栅极1201的走线，同时可以保证第一栅极1201和第二栅极1202之间良好的连接。
结合图1、图2和图3，在本申请所提供的实施例中，薄膜晶体管层12包括第一栅极线121和数据线123，第一栅极线121与第一栅极1201电连接且同层设置，数据线123与源漏极1203电连接且同层设置，第一栅极线121和数据线123错开设置。薄膜晶体管层12还包括第二栅极线122，第二栅极线122与第二栅极1202电连接且同层设置。
通过使第一栅极线121和数据线123错开设置，可以避免当第一栅极线121与数据线123重叠时两者之间产生寄生电容，有利于减小阵列基板10的电阻电容延迟。
在阵列基板10的制作过程中，可以在基板11上通过物理气相沉积工艺或化学气相沉积工艺形成一层金属层，采用一道光罩制程对该金属层进行图案化处理以得到第一栅极1201和第一栅极线121。同样，在制作第二栅极1202和第二栅极线122，以及制作源漏极1203和数据线123时也可以采用先沉积金属层，然后对金属层进行图案化处理的方式，沉积的金属层可以采用铜或者铝等具有良好导电性能的材料。
需要说明的是，为了使第一栅极线121和数据线123错开，需要对第一栅极线121进行刻蚀，以使第一栅极1201上具有与数据线123错开的镂空区域。结合图1、图2和图3，第二栅极线122与数据线123交叉，第一栅极线121和第二栅极线122至少部分重叠，第一栅极线121在第二栅极线122与数据线123交叉处断开，以使第一栅极线121与数据线123错开。通过使第一栅极线121在第二栅极线122与数据线123交叉处断开，即第一栅极线121上在第二栅极线122与数据线123交叉处镂空，在对第一栅极线121作刻蚀处理时只需要镂空其在第二栅极线122与数据线123交叉处的部分，简化了工艺。
结合图1和图2，薄膜晶体管层12中包括第一绝缘层1211和第二绝缘层1212。第二绝缘层1212作为薄膜晶体管120中的栅极绝缘层，实现了第一栅极1201或者第二栅极1202与有源层1204之间的绝缘。第二栅极线122、第一绝缘层1211、第一栅极线121、第二绝缘层1212、有源层1204以及数据线123层叠地设置在基板11上，第一栅极1201与有源层1204的位置对应。
由于第一栅极线121与数据线123错开，第二栅极线122与数据线123交错重叠，因此薄膜晶体管120中的寄生电容产生于第二栅极线122和数据线123之间。通过设置第一绝缘层1211和第二绝缘层1212，第二栅极线122和数据线123之间相隔了两层绝缘层，即实现了第二栅极线122和数据线123之间绝缘层厚度的增加。因此，可以减小第二栅极线122和数据线123在交叠区域所产生的电容，有利于减少阵列基板10的电阻电容延迟。
需要说明的是，第一栅极1201、第二栅极1202、有源层1204、以及源漏极1203之间的位置可以根据实际情况进行确定。如图3所示，第二栅极1202和有源层1204之间设有第二绝缘层1212。有源层1204、第二绝缘层1212、第二栅极线122、第一绝缘层1211、第一栅极线121以及数据线123依次层叠地设置在基板11上，第二栅极1202与有源层1204的位置对应。
优选的，如图2所示，第一栅极1201和有源层1204之间设有第二绝缘层1212。第二栅极线122、第一绝缘层1211、第一栅极线121、第二绝缘层1212、有源层1204以及数据线123层叠地设置在基板11上，第一栅极1201与有源层1204的位置对应。由此可以使第一栅极1201和第二栅极1202遮挡有源层1204，避免背光照射到有源层1204上而对薄膜晶体管120的性能造成影响。
可以理解的是，第一绝缘层1211和第二绝缘层1212的厚度可以根据实际情况进行确定。优选的，第一绝缘层1211的厚度大于或者等于第二绝缘层1212的厚度，第一绝缘层1211和第二绝缘层1212的厚度之和至少是第二绝缘层1212厚度的两倍。即在阵列基板10的制作中，可通过增加第一绝缘层1211的厚度以减小第二栅极线122和数据线123之间电容，避免了增加第二绝缘层1212的厚度对薄膜晶体管120的性能造成影响。
另一方面，本申请提供一种阵列基板10的制作方法，如图4所示，包括如下步骤：
S1、提供一基板11；
S2、在基板11上制作第二栅极1202和第二栅极线122，第二栅极1202和第二栅极线122电连接且同层设置；
S3、在第二栅极1202和第二栅极线122上制作第一绝缘层1211，并在第一绝缘层1211上开设通孔1210；
S4、在第一绝缘层1211上制作第一栅极1201和第一栅极线121，并使第一栅极1201穿过通孔1210与第二栅极1202电连接，第一栅极线121与第一栅极1201电连接且同层设置；
S5、在第一栅极1201和第一栅极线121上制作第二绝缘层1212；
S6、在第二绝缘层1212上制作有源层1204；
S7、在有源层1204上制作源漏极1203和数据线123，数据线123与源漏极1203中的源极1203a电连接且同层设置，数据线123与第二栅极线122交叉。
首先，提供一基板11，基板11的材料可以为玻璃或者树脂，具体此处不作限定。然后在基板11上制作第二栅极1202和第二栅极线122。本申请实施例中，在基板11上通过物理气相沉积工艺或化学气相沉积工艺形成一金属层，然后采用一道光罩制程对该金属层进行图案化处理以得到第二栅极1202和第二栅极线122。金属层可以采用铜或者铝等具有良好导电性能的材料，具体可以根据实际情况进行确定。
在制作第二栅极1202和第二栅极线122后，通过物理气相沉积方法、化学气相沉积方法、或涂覆方法在第二栅极1202和第二栅极线122上制作第一绝缘层1211，并在第一绝缘层1211上开设通孔1210。第一绝缘层1211的材料可以是二氧化硅或者氮化硅，开设通孔1210的工艺包括黄光刻蚀或者激光刻蚀，具体可根据实际情况进行确定。
接着，在第一绝缘层1211上制作第一栅极1201和第一栅极线121，并使第一栅极1201穿过通孔1210与第二栅极1202电连接。可以在第一绝缘层1211上通过物理气相沉积工艺或化学气相沉积工艺形成一层金属层，然后采用一道光罩制程对该金属层进行图案化处理以得到第一栅极1201和第一栅极线121。
需要说明的是，在制作第一栅极1201和第一栅极线121时，结合图3，使第一栅极线121上设置有隔断区域1213，以便在后续制作数据线123时能使数据线123能和第一栅极线121错开。
在制作第一栅极1201和第一栅极线121后，通过物理气相沉积方法、化学气相沉积方法、或涂覆方法在第一栅极1201和第一栅极线121上制作第二绝缘层1212。之后，在第二绝缘层1212之上制作有源层1204，有源层1204可以采用非晶硅、微晶硅、多晶硅、金属氧化物等半导体材料。
优选的，在步骤S7中，如图5所示，还包括：
S71、在有源层1204上沉积金属层；
S72、图案化金属层形成源漏极1203和数据线123，数据线123与隔断区域1213至少部分重叠。
在有源层1204之上沉积一层金属层，然后对该金属层进行图案化刻蚀的方式形成源漏极1203和数据线123，并使数据线123走线位于第一栅极线121上的隔断区域1213。即使数据线123与第一栅极线121错开，保证栅极线和数据线123之间的寄生电容是由第二栅极线122和数据线123之间交叠产生。因此，可以通过设置两层绝缘层的方式，减小第二栅极线122和数据线123之间的寄生电容，同时又不会影响薄膜晶体管120的性能。
以上对本申请提供一种阵列基板、阵列基板的制作方法及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (11)

1.一种阵列基板，其特征在于，所述阵列基板包括：
基板；
薄膜晶体管层，设置在所述基板上，所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管包括有源层、与所述有源层电连接的源漏极、与所述有源层对应的第一栅极和第二栅极，所述第一栅极和所述第二栅极之间设有第一绝缘层，所述第一绝缘层上开设有通孔，所述第一栅极和所述第二栅极通过所述通孔电连接。
2.根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管层包括第一栅极线和数据线，所述第一栅极线与所述第一栅极电连接且同层设置，所述数据线与所述源漏极电连接且同层设置；所述第一栅极线和所述数据线错开设置。
3.根据权利要求2所述的阵列基板，其特征在于，所述薄膜晶体管层包括第二栅极线，所述第二栅极线与所述第二栅极电连接且同层设置，所述第二栅极线与所述数据线交叉；
所述第一栅极线和所述第二栅极线至少部分重叠；所述第一栅极线在所述第二栅极线与所述数据线交叉处断开。
4.根据权利要求2所述的阵列基板，其特征在于，所述第一栅极和所述有源层之间设有第二绝缘层；
所述第二栅极线、所述第一绝缘层、所述第一栅极线、所述第二绝缘层、所述有源层以及所述数据线层叠地设置在所述基板上，所述第一栅极与所述有源层的位置对应。
5.根据权利要求2所述的阵列基板，其特征在于，所述第二栅极和所述有源层之间设有第二绝缘层；
所述有源层、所述第二绝缘层、所述第二栅极线、所述第一绝缘层、所述第一栅极线以及所述数据线依次层叠地设置在所述基板上，所述第二栅极与所述有源层的位置对应。
6.根据权利要求4或5所述的阵列基板，其特征在于，所述第一绝缘层的厚度大于或者等于所述第二绝缘层的厚度。
7.根据权利要求3所述的阵列基板，其特征在于，所述第一栅极线的厚度大于或者等于所述第二栅极线的厚度。
8.根据权利要求6所述的阵列基板，其特征在于，所述通孔与所述第一栅极的位置对应。
9.一种阵列基板的制作方法，其特征在于，包括如下步骤：
提供一基板；
在所述基板上制作第二栅极和第二栅极线，所述第二栅极和第二栅极线电连接且同层设置；
在所述第二栅极和第二栅极线上制作第一绝缘层，并在所述第一绝缘层上开设通孔；
在所述第一绝缘层上制作第一栅极和第一栅极线，并使所述第一栅极穿过所述通孔与所述第二栅极电连接，所述第一栅极线与所述第一栅极电连接且同层设置；
在所述第一栅极和第一栅极线上制作第二绝缘层；
在所述第二绝缘层上制作有源层；
在所述有源层上制作源漏极和数据线，所述数据线与所述源漏极中的源极电连接且同层设置。
10.根据权利要求9所述的阵列基板的制作方法，其特征在于，所述第一栅极线设置有隔断区域，所述在所述有源层上制作源漏极和数据线的步骤中，包括：
在所述有源层上沉积金属层；
图案化所述金属层形成源漏极和数据线，所述数据线与所述隔断区域至少部分重叠。
11.一种显示面板，其特征在于，所述显示面板包括权利要求1至8中任意一项所述的阵列基板。
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