WO2010078743A1 - 像素薄膜晶体管结构 - Google Patents

像素薄膜晶体管结构 Download PDF

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Publication number
WO2010078743A1
WO2010078743A1 PCT/CN2009/072493 CN2009072493W WO2010078743A1 WO 2010078743 A1 WO2010078743 A1 WO 2010078743A1 CN 2009072493 W CN2009072493 W CN 2009072493W WO 2010078743 A1 WO2010078743 A1 WO 2010078743A1
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WIPO (PCT)
Prior art keywords
electrode
gate electrode
amorphous silicon
thin film
silicon layer
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PCT/CN2009/072493
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English (en)
French (fr)
Inventor
柳智忠
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深超光电（深圳）有限公司
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Priority to TW098145641A priority Critical patent/TWI479245B/zh
Publication of WO2010078743A1 publication Critical patent/WO2010078743A1/zh
Priority to US12/869,754 priority patent/US8188518B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate

Definitions

  • the present invention relates to a transistor structure, and more particularly to a pixel thin film transistor structure which can be applied to a lower guide plate design of a liquid crystal display panel.
  • FIG. 1 is a schematic structural view of a thin film transistor of the prior art.
  • the first metal layer 10 serves as a gate electrode 12, and an amorphous silicon layer 14 and a first metal are formed on the first metal layer 10.
  • the layers 10 are partially overlapped; the second metal layer 16 is over the first metal layer 10 to form the drain electrode 18, the source electrode 20 and the data line 22, and the drain electrode 18 is T-shaped and will extend to
  • the amorphous silicon layer 14 overlaps with a portion thereof; the source electrode 20 is located on the amorphous silicon layer 14 and has a ⁇ -shaped correspondence with the drain electrode 18 and a data extending vertically across the first metal layer 10.
  • the line electrodes are connected.
  • the pixel electrode layer 24 is located above the drain electrode 18 and is electrically connected to the drain electrode 18 through the contact hole 26.
  • the exposure process When the exposure process is performed in the array process, the exposure will be shifted due to the slight vibration generated by the exposure machine during exposure.
  • the position of the drain electrode 18 is compared with that of FIG.
  • the longitudinal downward shift occurs such that the area of the portion where the drain electrode 18 and the amorphous silicon layer 14 are formed by the second metal layer 16 is changed, thus causing a parasitic capacitance between the drain electrode 18 and the gate electrode 12 ( Cgd) )
  • the change which causes the pixel electrode potential to drop due to the parasitic capacitance (C gd )
  • the present invention provides a pixel thin film transistor structure for resisting a deviation phenomenon occurring when an exposure machine is exposed.
  • the technical problem to be solved by the present invention is to provide a pixel thin film transistor structure having a displacement caused by vibration of a machine against an exposure process, so that a parasitic capacitance (c gd ) between a drain and a gate of a thin film transistor is fixed. So that the voltage applied to the pixel electrode is positive and negative, so that the voltage drop error of the DC level is reduced to a minimum.
  • Another technical problem to be solved by the present invention is to provide a pixel thin film transistor structure, which will reduce color unevenness (Mura) and flicker (Flicker) phenomenon in a local region of a liquid crystal display panel, so that the quality of the liquid crystal display panel can be greatly improved. .
  • the present invention provides a pixel thin film transistor structure in which a gate electrode is formed on a first metal layer, the gate electrode has an electrode portion extending outward; an insulating layer is formed on the first metal layer, and an amorphous silicon layer is formed on The insulating layer is respectively disposed above the gate electrode and the electrode portion; a second metal layer is further formed on the amorphous silicon layer, the second metal layer has a drain electrode and a source electrode, and the source electrode is located at the gate On the amorphous silicon layer above the pole electrode; the drain electrode overlaps the portion of the amorphous silicon layer above the gate electrode and above the electrode portion, and transmits the amorphous silicon layer, the insulating layer, the gate electrode and the electrode portion A first parasitic capacitance and a second parasitic capacitance are formed, and a sum of capacitances of the first parasitic capacitance and the second parasitic capacitance formed is a constant value.
  • FIG. 1 is a schematic structural view of a prior art thin film transistor.
  • FIG. 2 is a schematic structural view showing exposure shift of a thin film transistor of the prior art.
  • Figure 3 (a) is a cross-sectional view showing the structure of the present invention.
  • Fig. 3 (b) is a cross-sectional view showing the structure of the section AA of the present invention.
  • FIG. 4 is a schematic view showing the layout of a first embodiment of the present invention.
  • Fig. 5 is a schematic view showing exposure shift occurring in the first embodiment of the present invention.
  • Fig. 6 is a schematic view showing the layout of a second embodiment of the present invention.
  • Fig. 7 is a schematic view showing exposure shift occurring in the second embodiment of the present invention.
  • Figure 8 is a schematic view showing the layout of a third embodiment of the present invention.
  • Fig. 9 is a schematic view showing exposure shift occurring in the third embodiment of the present invention.
  • the invention provides a pixel thin film transistor structure, wherein a gate electrode of a first metal layer has an outwardly extending electrode portion, and a drain electrode of the second metal layer transmits an amorphous silicon layer and a gate electrode and an electrode portion, respectively
  • the parasitic current between the drain electrode and the gate electrode is as shown in FIG. 4, and please refer to the structural cross-sectional view shown in FIG. 3(a) and FIG. 3(b).
  • AA is a cross-sectional view of a section of the structure, the first metal layer 30 serves as a gate electrode 32, and the gate electrode 32 has an electrode portion 34 extending outwardly, and the electrode portion 34 has an L shape.
  • the insulating layer 36 is located on this first metal layer 30.
  • An amorphous silicon layer 38 is formed on the insulating layer 36, and is disposed on the gate electrode 32 and the electrode portion 34, respectively.
  • the second metal layer 40 is formed on the amorphous silicon layer 38 and has a drain electrode 42 and a source electrode 44.
  • the source electrode 44 is located on the amorphous silicon layer 38 on the gate electrode 32, and is open upward.
  • one end of the drain electrode 42 extends longitudinally to the amorphous silicon layer 38 on the gate electrode 32 corresponding to the center position of the source electrode 44, and transmits the amorphous silicon layer 38 and the gate electrode 32 portions overlap to form a first parasitic capacitance (not shown); and the other end of the drain electrode 42 extends laterally to the amorphous silicon layer 38 on the electrode portion 34 and transmits through the amorphous silicon
  • the layer 38 overlaps with the electrode portion 34 to form a second parasitic capacitance (not shown); the length of the drain electrode 42 overlapping the portion of the gate electrode 32 is equivalent to the drain electrode 42 and the electrode portion 34. Partially overlapping lengths.
  • an insulating layer 36 is formed on the second metal layer 40, and a hole 48 is formed in the insulating layer 36 opposite to the drain electrode 42 of the second metal layer 40, and then a pixel electrode is formed on the insulating layer 36.
  • the layer 46, the pixel electrode layer 46 will be electrically connected to the drain electrode 42 of the second metal layer 40 through the hole 48.
  • a scan line (not shown) and a data line 50 are connected to the gate electrode 32 of the first metal layer 30 and the source electrode 42 of the second metal layer 40, respectively.
  • the position of the drain electrode 42 is shifted upward in the longitudinal direction as compared with FIG. 4, so that the drain electrode 42 is transmitted through the amorphous silicon layer 38.
  • the area overlapping the portion of the gate electrode 32 is reduced, while the area of the drain electrode 42 that overlaps the portion of the electrode portion 34 through the amorphous silicon layer 38 is increased, which causes the capacitance value of the first capacitor to decrease, and vice versa.
  • the capacitance value of the capacitor increases, and the compensation relationship of the capacitor will increase the sum of the capacitances of the first parasitic capacitor and the second parasitic capacitor, and will not change due to the offset, thereby causing the drain electrode 42 and the gate.
  • the parasitic capacitance (C gd ) between the electrode electrodes 32 is maintained constant.
  • the drain electrode 42 extends longitudinally and laterally to the gate electrode 32 and the electrode portion 34, respectively, and is a first embodiment in which longitudinal offset occurs.
  • the shapes and arrangement positions of the gate electrode 32, the electrode portion 34, the drain electrode 42, and the source electrode 44, respectively, are changeable.
  • the second embodiment shows that the gate electrode 32 of the first metal layer 30 is a leftward extending electrode portion 34, and the two ends of the drain electrode 42 extend laterally to the gate electrode 32 and the electrode, respectively.
  • the amorphous silicon layer 38 on the portion 34 corresponds to the source electrode 44 which presents the ⁇ -shaped opening to the right.
  • FIG. 7 is a schematic diagram showing the offset of the second embodiment of the present invention.
  • the drain electrode 42 is laterally shifted to the left, and the drain electrode 42 and the electrode portion 34 are partially overlapped by the amorphous silicon layer 38.
  • the area overlapping with the portion of the gate electrode 32 passing through the amorphous silicon layer 38 decreases, and the total value of the parasitic capacitance (C gd ) is relatively fixed.
  • the drain electrode 42-end extends to the amorphous silicon layer 38 on the gate electrode 32, and has a terminal end having a ⁇ -shape and the other end transmitting the amorphous silicon layer 38 and the electrode portion 34.
  • the partial electrodes overlap each other, and the source electrode 44 has a straight strip shape corresponding to a ⁇ -shaped center point of the end of the drain electrode 42.
  • Figure 9 is a schematic view showing the lateral shift of the third embodiment of the present invention, as shown, the drain electrode 42 is laterally offset, The portion of the portion of the drain electrode 42 that is not ⁇ -shaped overlaps with the gate electrode 32 by the amorphous silicon layer 38 is reduced, and the portion where the overlap area is reduced is complemented by a portion where the area overlapping with the electrode layer 34 is increased.
  • the present invention is to compensate the gate electrode 32 of the first metal layer 30 outwardly from the electrode portion 34 as the gate electrode 32 to resist the offset of the exposure process, so that the second metal layer
  • the parasitic capacitance (C gd ) formed between the drain electrode 42 and the gate electrode 32 of 40 will remain constant when the exposure process is shifted.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Description

像素薄膜晶体管结构
【技术领域】
本发明有关于一种晶体管结构，特别有关于一种可应用于液晶显示面板中 下导板设计的像素薄膜晶体管结构。
【背景技术】
在薄膜晶体管液晶显示面板（TFT LCD ) 的制造中， 区分为阵列 （Array ) 工艺与彩色滤光片 （Color Filter )工艺， 其中于阵列工艺中制作出用于传递信 号的电压控制元件薄膜晶体管（Thin Film Transistors, TFT ), 以形成所需的电 极基板。 如图 1所示为现有技术的薄膜晶体管的结构示意图， 如图所示， 第一 金属层 10作为栅极电极 12, 此第一金属层 10上将形成非晶硅层 14与第一金 属层 10部分相重叠； 第二金属层 16位于第一金属层 10之上， 以形成漏极电 极 18、 源极电极 20与数据线 22, 此漏极电极 18为 T字状， 且将延伸至非晶 硅层 14上与其部分相重叠； 源极电极 20位于此非晶硅层 14上， 呈现 π字状 与漏极电极 18对应， 并且与纵向横跨于第一金属层 10之上的数据线相连接， 此外， 像素电极层 24位于漏极电极 18之上， 并且透过接触孔 26与漏极电极 18相导通。
当于阵列工艺中进行曝光工艺时，将会因曝光机台于曝光时所产生的微小 震动， 使曝光发生偏移现象， 如图 2所示， 漏极电极 18的位置相较于图 1将 发生纵向往下偏移使得第二金属层 16形成的漏极电极 18与非晶硅层 14重叠 部分的面积改变，如此将造成漏极电极 18与栅极电极 12之间的寄生电容（Cgd ) 有所变化， 进而导致像素电极电位因寄生电容（Cgd )存在所下降的电位（Feed Through Voltage )将随之而改变， 这将使得液晶显示面板的局部区域因此而发 生色彩不均 （Mura )与闪烁 （Flicker )等现象。 有鉴于此， 针对上述问题， 本发明提出一种像素薄膜晶体管结构， 用来抵 抗曝光机台曝光时所发生的偏差现象。
【发明内容】
本发明要解决的技术问题是提供一种像素薄膜晶体管结构，其具有抵抗曝 光工艺时机台振动所造成的偏移，使得薄膜晶体管的漏极与栅极之间的寄生电 容（cgd )得以固定， 以使得加在像素电极上的电压为正负相对称， 使直流位 准的电压降误差降低到最小值。
本发明要解决的又一技术问题是提供一种像素薄膜晶体管结构，其将减少 液晶显示面板局部区域的色彩不均（Mura )与闪烁（Flicker )现象发生， 使得 液晶显示面板的品质得以大幅提升。
为达到上述目的，本发明提出像素薄膜晶体管结构于第一金属层形成栅极 电极， 此栅极电极具有向外延伸的电极部； 绝缘层形成于第一金属层上， 非晶 硅层形成于绝缘层上并分别设置在栅极电极与电极部的上方；在此非晶硅层上 将再形成第二金属层， 此第二金属层具有漏极电极与源极电极， 源极电极位于 栅极电极上方的非晶硅层上； 漏极电极分别与栅极电极上方及电极部上方的非 晶硅层部分相重叠， 并透过非晶硅层、 绝缘层与栅极电极及电极部之间形成第 一寄生电容与第二寄生电容，且形成的第一寄生电容与第二寄生电容的电容量 总和为定值。
【附图说明】
下面结合附图和实施例对本发明进一步说明。
图 1为现有技术的薄膜晶体管的结构示意图。
图 2为现有技术的薄膜晶体管发生曝光偏移的结构示意图。
图 3 ( a ) 为本发明的结构剖视图。 图 3 ( b ) 为本发明的 A-A，区间的结构截面剖视图。
图 4为本发明的第一实施例的布局结构示意图。
图 5为本发明第一实施例发生曝光偏移的示意图。
图 6为本发明的第二实施例的布局结构示意图。
图 7为本发明第二实施例发生曝光偏移的示意图。
图 8为本发明的第三实施例的布局结构示意图。
图 9为本发明第三实施例发生曝光偏移的示意图。
【具体实施方式】
本发明提出一种像素薄膜晶体管结构，其第一金属层的栅极电极具有向外 延伸的电极部，第二金属层的漏极电极透过非晶硅层分别与栅极电极及电极部 部分相重叠， 以使曝光工艺造成偏移时， 让漏极电极与栅极电极之间的寄生电 如图 4所示， 并请同时参阅图 3 ( a )所示的结构剖视图与图 3 ( b )所示 的 A-A，区间的结构截面剖视图， 第一金属层 30作为栅极电极 32, 此栅极电极 32具有向外拓展延伸的电极部 34, 此电极部 34为 L字状。 绝缘层 36位于此 第一金属层 30上。于此绝缘层 36上形成非晶硅层 38,且分别设置于栅极电极 32与电极部 34上。 第二金属层 40形成于非晶硅层 38上， 且具有漏极电极 42 与源极电极 44, 此源极电极 44位于栅极电极 32上的非晶硅层 38上， 且为开 口向上的 π字状；此漏极电极 42的一端为纵向延伸至栅极电极 32上的非晶硅 层 38上与源极电极 44的中心位置相对应， 并透过非晶硅层 38与栅极电极 32 部分相重叠， 以形成第一寄生电容（图中未示出）； 而此漏极电极 42的另一端 为横向延伸至电极部 34上的非晶硅层 38上， 并透过非晶硅层 38与电极部 34 部分相重叠， 以形成第二寄生电容（图中未示出）； 此漏极电极 42与栅极电极 32部分相重叠的长度等同于此漏极电极 42与电极部 34部分相重叠的长度。此 外，在此第二金属层 40之上将再形成绝缘层 36,且于绝缘层 36相对第二金属 层 40的漏极电极 42所在位置开设孔洞 48, 其后于绝缘层 36上形成像素电极 层 46 ,像素电极层 46将透过此孔洞 48与第二金属层 40的漏极电极 42相导通。 另外， 还有扫描线（图中未示出）及数据线 50分别与第一金属层 30的栅极电 极 32及第二金属层 40的源极电极 42相连接。
当曝光工艺因机台震动发生曝光偏移现象时， 如图 5所示， 漏极电极 42 的位置相较于图 4将纵向往上偏移，使漏极电极 42透过非晶硅层 38与栅极电 极 32部分相重叠的面积缩减， 而同时漏极电极 42透过非晶硅层 38与电极部 34部分相重叠的面积将增加，将使得第一电容的电容值减少，反之第二电容的 电容值增加， 如此的此消彼涨的补偿关系， 将使第一寄生电容与第二寄生电容 的电容量总和为定值， 不会因偏移改变， 进而使漏极电极 42与栅极电极 32之 间的寄生电容（Cgd )得以维持固定。
承上所述是漏极电极 42分别纵向与横向延伸至栅极电极 32及电极部 34 之上， 且为发生纵向偏移的第一实施例。 另外， 栅极电极 32、 电极部 34、 漏 极电极 42与源极 44分别所呈现的形状与设置位置是可改变。如图 6所示为第 二实施例， 如图所示， 第一金属层 30的栅极电极 32是向左延伸电极部 34, 漏 极电极 42两端分别横向延伸至栅极电极 32及电极部 34上的非晶硅层 38上， 且与呈现 π字形开口向右的源极电极 44相对应。 图 7所示为本发明第二实施 例发生偏移的示意图， 如图所示， 漏极电极 42横向往左偏移， 使漏极电极 42 与电极部 34通过非晶硅层 38部分相重叠面积增加， 与栅极电极 32通过非晶 硅层 38部分相重叠面积减少， 而寄生电容（Cgd )总值则相对固定。
第三实施例如图 8所示，漏极电极 42—端延伸至栅极电极 32上的非晶硅 层 38上， 且末端为 π字状， 另一端透过非晶硅层 38与电极部 34部分相重叠， 源极电极 44为直条状与漏极电极 42末端的 π字状的中心点对应。 图 9为本发 明第三实施例发生横向偏移的示意图， 如图所示， 漏极电极 42横向偏移， 此 漏极电极 42非 π字状的部分通过非晶硅层 38与栅极电极 32相重叠的面积将 缩减， 重叠面积缩减的部分由与电极层 34重叠面积增加的部分补足。
经由上述各实施例说明可知本发明为将第一金属层 30的栅极电极 32向外 拓展电极部 34来作为栅极电极 32的补偿， 以抵抗曝光工艺所发生偏移， 使得 第二金属层 40的漏极电极 42与栅极电极 32之间形成的寄生电容（Cgd )将能 在曝光工艺发生偏移时仍保持定值。 一般技术人员能够了解本发明的内容并据以实施，不可理解为对本发明的保护 范围的限定，对于该领域内的技术工程人员根据本实施例所做的不超出本发明 技术方案的调整和改动， 应该认为落在本发明的保护范围内。

Claims

权 利 要 求
1. 一种像素薄膜晶体管结构， 其特征在于： 包括，
第一金属层， 以形成栅极电极， 和该栅极电极向外延伸的电极部； 绝缘层， 位于该第一金属层上；
非晶硅层， 位于该绝缘层上， 且分别设置于该栅极电极上方与该电极部上 方； 以及
第二金属层， 设置于该非晶硅层上， 以形成漏极电极与源极电极， 该源极 电极位于该栅极电极上方的该非晶硅层上，该漏极电极分别延伸至该栅极电极 上方及该电极部上方的该非晶硅层上，并且透过该非晶硅层分别与该栅极电极 及该电极部部分相重叠。
2. 根据权利要求 1所述的像素薄膜晶体管结构， 其特征在于： 该漏极电 极与该栅极电极部分相重叠的长度相等于该漏极电极与该电极部部分相重叠 的长度。
3. 根据权利要求 2所述的像素薄膜晶体管结构， 其特征在于： 该漏极电 极与该栅极电极通过该非晶硅层部分相重叠之间将形成第一寄生电容，该漏极 电极与该电极部通过该非晶硅层部分相重叠之间将形成第二寄生电容。
4. 根据权利要求 3所述的像素薄膜晶体管结构， 其特征在于： 该第一寄 生电容与该第二寄生电容的电容量总和为定值。
5. 根据权利要求 1所述的像素薄膜晶体管结构， 其特征在于： 还包括扫 描线与该栅极电极相连接。
6. 根据权利要求 1所述的像素薄膜晶体管结构， 其特征在于： 还包括数 据线与源极电极相连接。
7. 根据权利要求 1所述的像素薄膜晶体管结构， 其特征在于： 该漏极电 极延伸对应于该源极电极的中心位置。
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