CN101707211B - 像素薄膜晶体管结构 - Google Patents

像素薄膜晶体管结构 Download PDF

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CN101707211B
CN101707211B CN2009100365635A CN200910036563A CN101707211B CN 101707211 B CN101707211 B CN 101707211B CN 2009100365635 A CN2009100365635 A CN 2009100365635A CN 200910036563 A CN200910036563 A CN 200910036563A CN 101707211 B CN101707211 B CN 101707211B
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柳智忠
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Century Technology Shenzhen Corp Ltd
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate

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Abstract

本发明提供一种像素薄膜晶体管结构，其以第一金属层做为闸极电极，且闸极电极具有向外延展的一电极部，一第二金属层具有一汲极电极分别与闸极电极及电极部透过非晶硅层部份相重迭，并将形成第一寄生电容与第二寄生电容，且第一寄生电容与第二寄生电容的总电容值为定值，如此将能抵抗因黄光制程机台振动所造成的偏移，进而减少液晶显示面板局发生部区域色彩不均与闪烁等现象。

Description

像素薄膜晶体管结构
【技术领域】
本发明是有关一种晶体管结构，特别是关于一种可应用于液晶显示面板中下导板设计的像素薄膜晶体管结构。
【背景技术】
在薄膜晶体管液晶显示面板(TFT LCD)的制造中，区分为数组(Array)制程与彩色光阻(Color Filter)制程，其中于数组制程中制作出用以传递讯号的电压控制组件薄膜晶体管(Thin Film Transistors，TFT)，以形成所须的电极基板。如图1所示为现有技术的薄膜晶体管的结构示意图，如图所示，一第一金属层10系做为栅极电极12，此第一金属层10上将形成一非晶硅层14与第一金属层10部分相重迭；一第二金属层16系位于第一金属层10之上，以形成一漏极电极18、一源极电极20与一资料线22，此漏极电极18为T字型状，且将延伸至非晶硅层14上与其部分相重迭；源极电极20位于此非晶硅层14上，呈现ㄇ字状与漏极电极18对应，并且与纵向横跨于第一金属层10之上的数据线相连接，此外，一像素电极层24位于漏极电极18之上，并且透过一开洞26与漏极电极18相导通。
当于进行数组制程中的黄光制程时，将会因黄光机台于曝光时所产生些微震动，使曝光发生偏移现象，如图2所示，漏极电极18的位置相较于图1将发生纵向往下偏移使得第二金属层16形成的漏极电极18与非晶硅层14重迭部分的面积改变，如此将造成漏极电极18与栅极电极12之间的寄生电容(Cgd)有所变化，进而导致像素电极电位因寄生电容(Cgd)存在所下降的电位(Feed Through Voltage)将随之而改变，这将使得液晶显示面板的局部区域因此而发生色彩不均(Mura)与闪烁(Flicker)等现象。
有鉴于此，本发明是针对上述问题，以提出一种像素薄膜晶体管结构，以抵抗黄光机台曝光时所发生的偏差现象。
【发明内容】
本发明的主要目的是在提供一种像素薄膜晶体管结构，其具有抵抗黄光制程时机台振动所造成的偏移，使得薄膜晶体管的漏极与栅极之间的寄生电容(Cgd)得以固定，以使得加在像素电极上的电压为正负相对称，使直流位准的电压降误差降低到最小值。
本发明的又一目的是在提供一种像素薄膜晶体管结构，其将减少液晶显示面板局部区域的色彩不均(Mura)与闪烁(Flicker)现象发生，使得液晶显示面板的质量得以大幅提升。
为达到上述目的，本发明提出像素薄膜晶体管结构于第一金属层形成栅极电极，此栅极电极具有向外延伸的电极部；一绝缘层形成于第一金属层上，一非晶硅层形成于绝缘层上并分别设置在栅极电极与电极部的上方；在此非晶硅层上将再形成一第二金属层，此第二金属层具有一漏极电极与一源极电极，源极电极位于栅极电极上方的非晶硅层上；漏极电极分别与栅极电极上方及电极部上方的非晶硅层部分相重迭，并透过非晶硅层、绝缘层与栅极电极及电极部之间形成一第一寄生电容与一第二寄生电容，且形成之第一寄生电容与第二寄生电容的电容量总和为定值。
【附图说明】
下面结合附图和实施例对本发明进一步说明。
图1为现有技术的薄膜晶体管的结构示意图；
图2为现有技术的薄膜晶体管发生曝光偏移的结构示意图；
图3(a)为本发明的结构剖视图；
图3(b)为本发明的eA-A’区间的结构截面剖视图；
图4为本发明的第一实施例的布局结构示意图；
图5为本发明第一实施例发生曝光偏移的示意图；
图6为本发明的第二实施例的布局结构示意图；
图7为本发明第二实施例发生曝光偏移的示意图；
图8为本发明的第三实施例的布局结构示意图；
图9为本发明第三实施例发生曝光偏移的示意图。
【具体实施方式】
本发明提出一种像素薄膜晶体管结构其第一金属层的栅极电极系具有向外延伸的电极部，第二金属层的漏极电极系透过非晶硅层分别与栅极电极及电极部部分相重迭，以使黄光制程造成偏移时，让漏极电极与栅极电极之间的寄生电容(Cgd)的数值得以固定，底下则将以较佳实施例来详述本发明的技术特征。
如图4所示，并请同时参阅图3(a)所示的结构剖视图与图3(b)所示之A-A’区间的结构截面剖视图，一第一金属层30作为一栅极电极32，此栅极电极32具有向外拓展延伸的一电极部34，此电极部34为L字型状。一绝缘层36位于此一第一金属层30上。于此绝缘层36上形成一非晶硅层38，且分别设置于栅极电极32与电极部34上。一第二金属层40形成于非晶硅层38上，且具有一漏极电极42与一源极电极44，此源极电极44位于栅极电极32上的非晶硅层38上，且为开口向上的ㄇ字型状；此漏极电极42的一端为纵向延伸至栅极电极32上的非晶硅层38上与源极电极44的中心位置相对应，并透过非晶硅层38与栅极电极32部分相重迭，以形成一第一寄生电容(图中未示)；而此漏极电极42的另一端为横向延伸至电极部34上的非晶硅层38上，并透过非晶硅层38与电极部34部分相重迭，以形成一第二寄生电容(图中未示)；此漏极电极42与栅极电极32部分相重迭的长度等同于此漏极电极42与电极部34部分相重迭的长度。此外，在此第二金属层40之上将再形成绝缘层36，且于绝缘层36相对第二金属层40的漏极电极42所在位置开设一孔洞48，其后于绝缘层36上形成一像素电极层46，像素电极层46将透过此孔洞48与第二金属层40的漏极电极42相导通。另外，亦有一扫描线(图中未示)及一资料线50分别与第一金属层30之栅极电极32及第二金属层40之源极电极42相连接。
当黄光制程因机台震动发生曝光偏移现象时，如图5所示，漏极电极42的位置相较于图4将纵向往上偏移，使漏极电极42透过非晶硅层38与栅极电极32部分相重迭的面积缩减，而同时漏极电极42透过非晶硅层38与电极部34部分相重迭的面积将增加，将使得第一电容的电容值减少，反之第二电容的电容值增加，如此的此消彼涨的补偿关系，将使第一寄生电容与第二寄生电容的电容量总和为定值，不将因偏移改变，进而使漏极电极42与栅极电极32之间的寄生电容(Cgd)得以维持固定。
承上所述为漏极电极42分别纵向与横向延伸至栅极电极32及电极部34之上，且为发生纵向偏移的第一实施例。另外，栅极电极32、电极部34、漏极电极42与源极44分别所呈现的形状与设置位置是可改变。如图6所示为第二实施例，如图所示，第一金属层30的栅极电极32是向左延伸电极部34，漏极电极42两端分别横向延伸至栅极电极32及电极部34上之非晶硅层38上，且与呈现ㄇ字形开口向右之源极电极44相对应。图7所示为本发明第二实施例发生偏移的示意图，如图所示，漏极电极42横向往左偏移，使漏极电极42与电极部34通过非晶硅层38部分相重迭面积增加，与栅极电极32通过非晶硅层38部分相重迭面积减少，而寄生电容(Cgd)总值则相对固定。
第三实施例如图8所示，漏极电极42一端延伸至栅极电极32上的非晶硅层38上，且末端为ㄇ字型状，另一端透过非晶硅层38与电极部34部分相重迭，源极电极44为直条状与漏极电极42末端之ㄇ字型状的中心点对应。图9为本发明第三实施例发生横向偏移的示意图，如图所示，漏极电极42横向偏移，此漏极电极42非ㄇ字型状的部分藉由非晶硅层38与栅极电极32相重迭的面积将缩减，重迭面积缩减的部分由与电极层34重迭面积增加的部分补足。
经由上述各实施例说明可知本发明为将第一金属层30之栅极电极32向外拓展一电极部34来做为栅极电极32的补偿，以抵抗黄光制程所发生偏移，使得第二金属层40之漏极电极42与栅极电极32之间形成的寄生电容(Cgd)将能于黄光制程发生偏移时仍保持定值。
以上所述的实施例仅为说明本发明的技术思想及特点，其目的在使本领域一般技术人员能够了解本发明的内容并据以实施，不可理解为对本发明的保护范围的限定，对于该领域内的技术工程人员根据本实施例所做的不超出本发明技术方案的调整和改动，应该认为落在本发明的保护范围内。

Claims (7)

1.一种像素薄膜晶体管结构，其特征在于：包括，
一第一金属层，以形成一栅极电极，并该栅极电极向外延伸一电极部；
一绝缘层，位于该第一金属层上；
一非晶硅层，位于该绝缘层上，且分别设置于该栅极电极上方与该电极部上方；以及
一第二金属层，设置于该非晶硅层上，以形成一漏极电极与一源极电极，该源极电极位于该栅极电极上方的该非晶硅层上，该漏极电极分别延伸至该栅极电极上方及该电极部上方的该非晶硅层上，并且透过该非晶硅层分别与该栅极电极及该电极部部分相重迭。
2.根据权利要求1所述的薄膜晶体管结构，其特征在于：该漏极电极与该栅极电极部分相重迭的长度相等于该漏极电极与该电极部部分相重迭的长度。
3.根据权利要求2所述的薄膜晶体管结构，其特征在于：该漏极电极与该栅极电极通过该非晶硅层部分相重迭之间将形成一第一寄生电容，该漏极电极与该电极部通过该非晶硅层部分相重迭之间将形成一第二寄生电容。
4.根据权利要求3所述的薄膜晶体管结构，其特征在于：该第一寄生电容与该第二寄生电容的电容量总和为定值。
5.根据权利要求1所述的薄膜晶体管结构，其特征在于：还包括一扫描线与该栅极电极相连接。
6.根据权利要求1所述的薄膜晶体管结构，其特征在于：还包括一数据线与源极电极相连接。
7.根据权利要求1所述的薄膜晶体管结构，其特征在于：该漏极电极延伸对应于该源极电极的中心位置。
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CN2009100365635A CN101707211B (zh) 2009-01-09 2009-01-09 像素薄膜晶体管结构
PCT/CN2009/072493 WO2010078743A1 (zh) 2009-01-09 2009-06-26 像素薄膜晶体管结构
TW098145641A TWI479245B (zh) 2009-01-09 2009-12-29 畫素結構
US12/869,754 US8188518B2 (en) 2009-01-09 2010-08-27 Thin film transistor structure of pixel with drain extensions overlapping gate electrode and gate electrode extention

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