WO2013117004A1 - Tft阵列基板的制作方法 - Google Patents

Tft阵列基板的制作方法 Download PDF

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Publication number
WO2013117004A1
WO2013117004A1 PCT/CN2012/071005 CN2012071005W WO2013117004A1 WO 2013117004 A1 WO2013117004 A1 WO 2013117004A1 CN 2012071005 W CN2012071005 W CN 2012071005W WO 2013117004 A1 WO2013117004 A1 WO 2013117004A1
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layer
metal layer
array substrate
tft array
fabricating
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PCT/CN2012/071005
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English (en)
French (fr)
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覃事建
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深圳市华星光电技术有限公司
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Priority to DE112012005832.1T priority Critical patent/DE112012005832B4/de
Priority to US13/503,650 priority patent/US8895428B2/en
Publication of WO2013117004A1 publication Critical patent/WO2013117004A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of semiconductor fabrication, and in particular to a method for fabricating a TFT array substrate capable of reducing the number of lithography.
  • LCD liquid crystal Display: liquid crystal display
  • TFT thin film Transistor: Thin film field effect transistor
  • the LCD panel includes a TFT array substrate and a color filter substrate, and the liquid crystal is located therebetween.
  • the fabrication of the TFT array substrate is mainly performed by performing a photolithography process on a glass substrate to form a desired pattern structure to form TFT elements and corresponding wirings. Since the wiring on the TFT element and the glass substrate has multiple layers, it is necessary to perform a plurality of photolithography processes to complete the fabrication of the TFT array substrate. After the development and improvement of technology, four times of photolithography have been formed to form IPS (In-Plane) Switching, planar conversion) LCD TFT array substrate process technology.
  • IPS In-Plane
  • Fig. 1 is a plan view showing the planar structure of a TFT array substrate of a prior art IPS type LCD
  • Fig. 2 is a cross-sectional view taken along line III-III' and line IV-IV' of Fig. 1.
  • a conductive metal is deposited on the lower substrate 80, and is patterned by photolithography to form a scanning line 81 and a gate 81a.
  • the common line 81b is formed simultaneously with the scanning line 81, and the plurality of transparent electrodes 81c are connected to the common line 81b.
  • an insulating layer 82 is formed on the entire surface of the lower substrate 80 including the scanning lines 81, a semiconductor layer is deposited on the insulating layer 82, and is photolithographically patterned to form an active layer 83 over the gate.
  • a conductive metal is deposited on the entire surface of the lower substrate 80 on which the active layer 83 is formed, and is photolithographically patterned to form data lines 84_1, 84_2, 84_3, and 84_4, and a source 84a and a drain are simultaneously formed.
  • 84b A protective layer 85 is formed on the entire surface of the lower substrate 80, and a contact hole 86 is formed to expose the drain electrode 84b.
  • a transparent conductive metal is deposited on the protective layer 85, and the transparent conductive metal is photolithographically patterned to form a pixel electrode 87 that is in contact with the drain electrode 84b through the contact hole 86.
  • the pixel electrode 87 is formed while being above the common line 81b.
  • the storage electrode 88 is formed on the protective layer 85.
  • the process of forming a TFT array substrate of an IPS type LCD by four times of lithography is still complicated, the fabrication difficulty and the manufacturing cost are high, and the production difficulty of the liquid crystal display is increased. Therefore, it is necessary to provide a TFT array substrate.
  • the production method is to solve the problems existing in the prior art.
  • the present invention provides a TFT array substrate which can complete the fabrication of the entire TFT array substrate by using three photolithography processes, simplify the fabrication process of the TFT array substrate, save the fabrication cost of the TFT array substrate, and save the fabrication time of the TFT array substrate. .
  • the fabrication process of the entire TFT array substrate is completed by four photolithography processes, which causes a problem of increasing the manufacturing cost of the TFT array substrate and prolonging the fabrication time.
  • the invention constructs a TFT array substrate manufacturing method, comprising the steps of: A, sequentially depositing a first transparent conductive layer and a first metal layer, performing pattern processing to form a common electrode, a gate electrode and a transparent electrode array; Depositing an insulating layer, an active layer, an ohmic contact layer, and a second metal layer, performing patterning treatment such that the second metal layer forms a source and a drain on both sides of the active layer; C, depositing a second transparent a conductive layer, patterned to form a source contact layer, a drain contact layer, and a pixel electrode array connected to the drain contact layer; D, forming a protective layer on a channel surface of the active layer;
  • the first transparent conductive layer and the first metal layer are sequentially deposited by using a sputtering method in A; in the step A, a semi-transparent lithography plate is used for patterning to form the common electrode, the gate electrode, and the a transparent electrode array; the insulating layer, the active layer,
  • the channel surface of the active layer is passivated using a plasma in the step D to form a protective layer.
  • the first metal layer includes an aluminum metal layer and a first molybdenum metal layer
  • the second metal layer includes a first molybdenum metal layer, an aluminum metal layer, and a second molybdenum metal layer.
  • the first metal layer is wet-etched using a mixed solution of nitric acid, phosphoric acid, and acetic acid, and the first transparent conductive layer is performed using oxalic acid. Wet etching.
  • the second metal layer is wet-etched using a mixed solution of nitric acid, phosphoric acid, and acetic acid to the insulating layer and the active layer. And the ohmic contact layer is dry etched.
  • the invention constructs a method for fabricating a TFT array substrate, comprising the steps of: A, sequentially depositing a first transparent conductive layer and a first metal layer, performing pattern processing to form a common electrode, a gate electrode and a transparent electrode array; B, sequentially depositing insulation a layer, an active layer, an ohmic contact layer, and a second metal layer, patterned to form the second metal layer to form a source and a drain on both sides of the active layer; C, depositing a second transparent conductive layer Performing a patterning process to form a source contact layer, a drain contact layer, and a pixel electrode array connected to the drain contact layer; D, forming a protective layer on a channel surface of the active layer.
  • the first transparent conductive layer and the first metal layer are sequentially deposited in the step A using a sputtering method.
  • a semi-transparent lithography plate is used for patterning to form the common electrode, the gate electrode, and the transparent electrode array.
  • the insulating layer, the active layer, the ohmic contact layer, and the second metal layer are sequentially deposited in the step B using a chemical weather deposition method.
  • the source electrode and the drain are formed on both sides of the active layer by performing a patterning process using the semi-transparent lithography plate in the step B.
  • the second transparent conductive layer is deposited in the step C using a sputtering method.
  • the channel surface of the active layer is passivated using a plasma in the step D to form a protective layer.
  • the first metal layer includes an aluminum metal layer and a first molybdenum metal layer
  • the second metal layer includes a first molybdenum metal layer, an aluminum metal layer, and a second molybdenum metal layer.
  • the first metal layer is wet-etched using a mixed solution of nitric acid, phosphoric acid, and acetic acid, and the first transparent conductive layer is performed using oxalic acid. Wet etching.
  • the second metal layer is wet-etched using a mixed solution of nitric acid, phosphoric acid, and acetic acid to the insulating layer and the active layer. And the ohmic contact layer is dry etched.
  • the fabrication of the entire TFT array substrate can be completed by three photolithography processes, the fabrication process of the TFT array substrate is simplified, the fabrication cost of the TFT array substrate is saved, and the fabrication time of the TFT array substrate is saved, and the fabrication of the TFT array substrate of the prior art is solved.
  • the method uses four photolithography processes to complete the fabrication of the entire TFT array substrate, and the manufacturing cost of the TFT array substrate is increased and the production time is prolonged.
  • FIG. 1 is a schematic plan view showing a planar structure of a TFT array substrate of a prior art IPS type LCD
  • Figure 2 is a cross-sectional view taken along line III-III' and line IV-IV' of Figure 1;
  • FIG. 3 is a flow chart of a preferred embodiment of a method of fabricating a TFT array substrate of the present invention
  • FIG. 4 is a schematic plan view showing a planar structure of a TFT array substrate according to a preferred embodiment of the method for fabricating a TFT array substrate of the present invention
  • 5A-5D are schematic diagrams showing the fabrication of a preferred embodiment of a method of fabricating a TFT array substrate of the present invention.
  • FIG. 3 is a flow chart of a preferred embodiment of a method for fabricating a TFT array substrate of the present invention.
  • the manufacturing method of the TFT array substrate includes the following steps:
  • Step 101 sequentially depositing a first transparent conductive layer and a first metal layer, performing patterning processing to form a common electrode 301, a gate 302, and a transparent electrode array 201;
  • Step 102 after sequentially depositing the insulating layer 4, the active layer 5, the ohmic contact layer 6, and the second metal layer, performing patterning processing so that the second metal layer forms the source 701 and the drain 702 on both sides of the active layer 5. ;
  • Step 103 depositing a second transparent conductive layer, performing a patterning process to form a source contact layer 801, a drain contact layer 802, and a pixel electrode array 803 connected to the drain contact layer 802;
  • Step 104 forming a protective layer 502 on the channel surface of the active layer 5.
  • Step 101 includes:
  • Step 1011 sequentially depositing a first transparent conductive layer and a first metal layer on the lower substrate 1 by using a sputtering method.
  • the first transparent conductive layer is formed using a transparent conductive metal, for example, indium tin oxide (ITO), tin oxide (TO) And indium zinc oxide (IZO) and indium tin zinc oxide (ITZO), the first metal layer preferably comprising an aluminum metal layer and a first molybdenum metal layer.
  • ITO indium tin oxide
  • TO tin oxide
  • IZO indium zinc oxide
  • ITZO indium tin zinc oxide
  • Step 1012 performing a patterning process using a semi-transparent lithography plate to form a common electrode 301, a gate 302, and a transparent electrode array 201 (while forming a scan line 303 connected to the gate 302), wherein the common electrode 301 is connected to the transparent electrode array 201.
  • the common electrode 301 and the gate electrode 302 are formed on the first metal layer, and the transparent electrode array 201 is formed on the first transparent conductive layer.
  • the gate 302 and the common electrode 301 portion, the transparent electrode array 201 portion, and other portions of the lower substrate 1 are exposed to different degrees using a semi-transparent lithography plate, and then the first metal layer is performed using a mixed solution of nitric acid, phosphoric acid, and acetic acid.
  • the wet etching is performed to form the gate electrode 302 and the common electrode 301, and the first transparent conductive layer is wet-etched using oxalic acid to form the transparent electrode array 201.
  • the pattern of the patterned TFT array substrate is as shown in FIG. 5A.
  • Step 102 includes:
  • Step 1021 sequentially depositing an insulating layer 4, an active layer 5, an ohmic contact layer 6, and a second metal layer by using a chemical vapor deposition method, wherein the second metal layer preferably includes a first molybdenum metal layer, an aluminum metal layer, and a second molybdenum metal Floor.
  • Step 1022 performing patterning processing using semi-transparent lithography, so that the second metal layer forms a source 701 and a drain 702 on both sides of the active layer (while forming a signal line 703 connected to the source 701), wherein the source The pole 701 and the drain 702 are located on the ohmic contact layer 6, and the source 701 and the drain 702 portion, the channel 501 portion of the active layer 5, and other portions are exposed to different degrees using a semi-transparent lithography plate, and then nitric acid is used.
  • the second metal layer is wet etched with a mixture of phosphoric acid and acetic acid, and then RIE (Reactive) Ion
  • An etching method such as Etching: reactive ion etching) dry-etches the insulating layer 4, the active layer 5, and the ohmic contact layer 6 to form a source 701 and a drain 702, and exposes the source 701 and the drain 702.
  • Etching: reactive ion etching dry-etches the insulating layer 4, the active layer 5, and the ohmic contact layer 6 to form a source 701 and a drain 702, and exposes the source 701 and the drain 702.
  • the portion of the channel 501 of the active layer 5, the pattern of the patterned TFT array substrate is as shown in FIG. 5B.
  • Step 103 includes:
  • Step 1031 depositing a second transparent conductive layer by using a sputtering method, wherein the second transparent conductive layer is formed using a transparent conductive metal, for example, indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and Indium tin zinc oxide (ITZO).
  • ITO indium tin oxide
  • TO tin oxide
  • IZO indium zinc oxide
  • ITZO Indium tin zinc oxide
  • Step 1032 performing a patterning process to form a source contact layer 801, a drain contact layer 802, and a pixel electrode array 803 connected to the drain contact layer 802.
  • the pixel electrode array 803 portion and the non-pixel electrode array may be used by using a photoresist plate. Partially performing different degrees of exposure, and then etching the second transparent conductive layer with oxalic acid to form a source contact layer 801, a drain contact layer 802, and a pixel electrode array 803, and the pattern of the imaged TFT array substrate is as follows. 4 and 5C, in which the transparent electrode array 201 and the pixel electrode array 803 are separated by the insulating layer 4, and the right side of the pixel electrode array 803 and the common electrode 301 constitute the storage capacitance of the TFT array substrate.
  • Step 104 is specifically to passivate the surface of the channel 501 of the active layer 5 using a plasma to form a protective layer 502 on the surface of the channel 501 of the active layer 5.
  • the pattern of the passivated TFT array substrate is as shown in FIG. 5D. Shown.
  • the active layer 5, the source 701 and the drain 702 are formed by one photolithography, which can be conveniently used in the fabrication of an IPS type wide viewing angle liquid crystal display, so that three-time lithography is used.
  • the entire TFT array substrate can be completed in the process, the manufacturing process is simplified, the manufacturing cost is saved, the fabrication time is saved, and the fabrication method of the prior art TFT array substrate is well solved.
  • the entire TFT is completed by four photolithography processes. The manufacturing cost of the TFT array substrate due to the fabrication of the array substrate and the technical problem of prolonged production time.

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Abstract

一种TFT阵列基板的制作方法，包括沉积第一透明导电层以及第一金属层，进行图形化形成公共电极（301）、栅极（302）以及透明电极阵列（201）；沉积绝缘层（4）、有源层（5）、欧姆接触层（6）以及第二金属层，进行图形化形成源极（701）和漏极（702）；沉积第二透明导电层，进行图形化形成源极接触层（801）、漏极接触层（802）以及像素电极阵列（803）。本发明简化了制作工艺、节约了制作成本并且节省了制作时间。

Description

TFT阵列基板的制作方法 技术领域
本发明涉及半导体制作领域，特别是涉及一种可以减少光刻次数的TFT阵列基板的制作方法。
 背景技术
LCD（liquid crystal display:液晶显示器）面板是液晶显示器的重要组件之一，现有的TFT（thin film transistor：薄膜场效应晶体管）LCD面板由于其功率低、体积小、无辐射等优点，被广泛的用于液晶显示器中。
TFT LCD面板包括TFT阵列基板和彩膜基板，液晶位于两者之间。目前，TFT阵列基板的制作主要是通过在玻璃基板上进行光刻工艺，制作成所需要的图形结构，以形成TFT元件以及相应的布线。由于TFT元件及玻璃基板上的布线具有多层次，因而需要实施多次光刻工艺才能完成TFT阵列基板的制作。经过技术的发展和改进，现在已经形成了四次光刻形成IPS（In-Plane Switching，平面转换）型LCD的TFT阵列基板的工艺技术。
图1为现有技术的IPS型LCD的TFT阵列基板的平面结构示意图，图2为沿图1的Ⅲ-Ⅲ’线和Ⅳ-Ⅳ’线的剖面图。
现在参照图1和图2说明现有技术的四次光刻形成IPS型LCD的TFT阵列基板的工艺。首先，在下基板80上沉积一导电金属，并对其进行光刻构图形成扫描线81以及栅极81a，公共线81b与扫描线81同时形成，多个透明电极81c与公共线81b相连。接着，在包括扫描线81的下基板80的整个表面上形成绝缘层82，在绝缘层82上沉积一半导体层，并对其进行光刻构图，以在栅极上方形成有源层83。然后，在形成有源层83的下基板80的整个表面上沉积一导电金属，并对其进行光刻构图，以形成数据线84_1、84_2、84_3以及84_4，并同时形成源极84a和漏极84b。在下基板80的整个表面上形成保护层85，并形成一接触孔86以暴露漏极84b。最后，在保护层85上沉积透明导电金属，对该透明导电金属进行光刻构图，形成通过接触孔86与漏极84b接触的像素电极87，在形成像素电极87的同时，在公共线81b上方的保护层85上形成存储电极88。
综上所述，四次光刻形成IPS型LCD的TFT阵列基板的工艺制程仍然较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度，故，有必要提供一种TFT阵列基板的制作方法，以解决现有技术所存在的问题。
 技术问题
本发明提供一种采用三次光刻工序即可完成整个TFT阵列基板的制作，简化TFT阵列基板的制作工艺、节约TFT阵列基板的制作成本以及节省TFT阵列基板的制作时间的TFT阵列基板的制作方法。以解决现有技术的TFT阵列基板的制作方法采用四次光刻工序完成整个TFT阵列基板的制作造成TFT阵列基板的制作成本增加以及制作时间延长的技术问题。
 技术解决方案
本发明构造了一种TFT阵列基板的制作方法，其中包括步骤：A、依次沉积第一透明导电层以及第一金属层，进行图形化处理形成公共电极、栅极以及透明电极阵列；B、依次沉积绝缘层、有源层、欧姆接触层以及第二金属层，进行图形化处理使所述第二金属层在所述有源层的两侧形成源极和漏极；C、沉积第二透明导电层，进行图形化处理形成源极接触层、漏极接触层以及与所述漏极接触层连接的像素电极阵列；D、在所述有源层的沟道表面形成保护层；所述步骤A中使用溅射法依次沉积所述第一透明导电层以及所述第一金属层；所述步骤A中使用半透性光刻板进行图形化处理形成所述公共电极、所述栅极以及所述透明电极阵列；所述步骤B中使用化学气象沉积法依次沉积所述绝缘层、所述有源层、所述欧姆接触层以及所述第二金属层；所述步骤C中使用溅射法沉积所述第二透明导电层。
在本发明的TFT阵列基板的制作方法中，所述步骤D中使用等离子体对所述有源层的沟道表面进行钝化处理以形成保护层。
在本发明的TFT阵列基板的制作方法中，所述第一金属层包括铝金属层和第一钼金属层，所述第二金属层包括第一钼金属层、铝金属层以及第二钼金属层。
在本发明的TFT阵列基板的制作方法中，所述步骤A中使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述第一透明导电层进行湿法刻蚀。
在本发明的TFT阵列基板的制作方法中，所述步骤B中使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，对所述绝缘层、所述有源层以及所述欧姆接触层进行干法刻蚀。
本发明构造了TFT阵列基板的制作方法，其中包括步骤：A、依次沉积第一透明导电层以及第一金属层，进行图形化处理形成公共电极、栅极以及透明电极阵列；B、依次沉积绝缘层、有源层、欧姆接触层以及第二金属层，进行图形化处理使所述第二金属层在所述有源层的两侧形成源极和漏极；C、沉积第二透明导电层，进行图形化处理形成源极接触层、漏极接触层以及与所述漏极接触层连接的像素电极阵列；D、在所述有源层的沟道表面形成保护层。
在本发明的TFT阵列基板的制作方法中，所述步骤A中使用溅射法依次沉积所述第一透明导电层以及所述第一金属层。
在本发明的TFT阵列基板的制作方法中，所述步骤A中使用半透性光刻板进行图形化处理形成所述公共电极、所述栅极以及所述透明电极阵列。
在本发明的TFT阵列基板的制作方法中，所述步骤B中使用化学气象沉积法依次沉积所述绝缘层、所述有源层、所述欧姆接触层以及所述第二金属层。
在本发明的TFT阵列基板的制作方法中，所述步骤B中使用半透性光刻板进行图形化处理在所述有源层的两侧形成所述源极和所述漏极。
在本发明的TFT阵列基板的制作方法中，所述步骤C中使用溅射法沉积所述第二透明导电层。
在本发明的TFT阵列基板的制作方法中，所述步骤D中使用等离子体对所述有源层的沟道表面进行钝化处理以形成保护层。
在本发明的TFT阵列基板的制作方法中，所述第一金属层包括铝金属层和第一钼金属层，所述第二金属层包括第一钼金属层、铝金属层以及第二钼金属层。
在本发明的TFT阵列基板的制作方法中，所述步骤A中使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述第一透明导电层进行湿法刻蚀。
在本发明的TFT阵列基板的制作方法中，所述步骤B中使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，对所述绝缘层、所述有源层以及所述欧姆接触层进行干法刻蚀。
 有益效果
采用三次光刻工序即可完成整个TFT阵列基板的制作，简化TFT阵列基板的制作工艺、节约TFT阵列基板的制作成本以及节省TFT阵列基板的制作时间，解决了现有技术的TFT阵列基板的制作方法采用四次光刻工序完成整个TFT阵列基板的制作造成的TFT阵列基板的制作成本增加以及制作时间延长的技术问题。
 附图说明
图1为现有技术的IPS型LCD的TFT阵列基板的平面结构示意图；
图2为沿图1的Ⅲ-Ⅲ’线和Ⅳ-Ⅳ’线的剖面图；
图3为本发明的TFT阵列基板的制作方法的优选实施例的流程图；
图4为本发明的TFT阵列基板的制作方法的优选实施例的TFT阵列基板的平面结构示意图；
图5A-图5D为本发明的TFT阵列基板的制作方法的优选实施例的制作结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
本发明涉及一种TFT阵列基板的制作方法，如图3所示，图3为本发明的TFT阵列基板的制作方法的优选实施例的流程图。所述TFT阵列基板的制作方法包括以下步骤：
步骤101、依次沉积第一透明导电层以及第一金属层，进行图形化处理形成公共电极301、栅极302以及透明电极阵列201；
步骤102、依次沉积绝缘层4、有源层5、欧姆接触层6以及第二金属层后，进行图形化处理使第二金属层在有源层5的两侧形成源极701和漏极702；
步骤103、沉积第二透明导电层，进行图形化处理形成源极接触层801、漏极接触层802以及与漏极接触层802连接的像素电极阵列803；
步骤104、在有源层5的沟道表面形成保护层502。
下面参照图4、图5A、图5B、图5C以及图5D来详细说明本发明的TFT阵列基板的制作方法的流程。
步骤101包括：
步骤1011、使用溅射法依次在下基板1上沉积第一透明导电层以及第一金属层，第一透明导电层使用透明导电金属形成，例如，铟锡氧化物（ITO）、锡氧化物（TO）、铟锌氧化物（IZO）以及铟锡锌氧化物（ITZO），第一金属层优选包括铝金属层和第一钼金属层。
步骤1012、使用半透性光刻板进行图形化处理形成公共电极301、栅极302以及透明电极阵列201（同时形成与栅极302相连的扫描线303），其中公共电极301与透明电极阵列201连接，公共电极301和栅极302形成于第一金属层上，透明电极阵列201形成于第一透明导电层上。使用半透性光刻板对栅极302和公共电极301部分、透明电极阵列201部分以及下基板1的其它部分进行不同程度的曝光，然后使用硝酸、磷酸以及醋酸的混合液对第一金属层进行湿法刻蚀以形成栅极302以及公共电极301，使用草酸对第一透明导电层进行湿法刻蚀以形成透明电极阵列201，图形化处理后的TFT阵列基板的图案如图5A所示。
步骤102包括：
步骤1021、使用化学气相沉积法依次沉积绝缘层4、有源层5、欧姆接触层6以及第二金属层，其中第二金属层优选包括第一钼金属层、铝金属层以及第二钼金属层。
步骤1022、使用半透性光刻进行图形化处理，使第二金属层在有源层的两侧形成源极701以及漏极702（同时形成与源极701相连的信号线703），其中源极701和漏极702位于欧姆接触层6上，使用半透性光刻板对源极701和漏极702部分、有源层5的沟道501部分以及其他部分进行不同程度的曝光，然后使用硝酸、磷酸以及醋酸的混合液对第二金属层进行湿法刻蚀，然后采用RIE（Reactive Ion Etching：反应离子刻蚀）等刻蚀方法对绝缘层4、有源层5以及欧姆接触层6进行干法刻蚀以形成源极701和漏极702，并露出源极701和漏极702之间的有源层5的沟道501部分，图形化处理后的TFT阵列基板的图案如图5B所示。
步骤103包括：
步骤1031、使用溅射法沉积第二透明导电层，第二透明导电层使用透明导电金属形成，例如，铟锡氧化物（ITO）、锡氧化物（TO）、铟锌氧化物（IZO）以及铟锡锌氧化物（ITZO）。
步骤1032、进行图形化处理形成源极接触层801、漏极接触层802以及与所述漏极接触层802连接的像素电极阵列803，可使用光刻板对像素电极阵列803部分和非像素电极阵列部分进行不同程度的曝光，然后使用草酸对第二透明导电层进行施法刻蚀以形成源极接触层801、漏极接触层802以及像素电极阵列803，图像化处理后的TFT阵列基板的图案如图4和图5C所示，其中透明电极阵列201和像素电极阵列803通过绝缘层4隔开，并且图中像素电极阵列803的右侧和公共电极301构成了TFT阵列基板的存储电容。
步骤104具体为使用等离子体对有源层5的沟道501表面进行钝化处理从而在有源层5的沟道501表面形成保护层502，钝化处理后的TFT阵列基板的图案如图5D所示。
本发明的TFT阵列基板的制作方法中有源层5、源极701和漏极702通过一次光刻形成，可以方便的运用于IPS型广视角显液晶示器的制作中，使得采用三次光刻工序即可完成整个TFT阵列基板的制作，简化了制作工艺，节约了制作成本，节省了制作时间，很好的解决了现有技术的TFT阵列基板的制作方法采用四次光刻工序完成整个TFT阵列基板的制作造成的TFT阵列基板的制作成本增加以及制作时间延长的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
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Claims (15)

  1. 一种TFT阵列基板的制作方法，其中包括步骤：
    A、依次沉积第一透明导电层以及第一金属层，进行图形化处理形成公共电极、栅极以及透明电极阵列；
    B、依次沉积绝缘层、有源层、欧姆接触层以及第二金属层，进行图形化处理使所述第二金属层在所述有源层的两侧形成源极和漏极；
    C、沉积第二透明导电层，进行图形化处理形成源极接触层、漏极接触层以及与所述漏极接触层连接的像素电极阵列；
    D、在所述有源层的沟道表面形成保护层；
    所述步骤A中使用溅射法依次沉积所述第一透明导电层以及所述第一金属层；
    所述步骤A中使用半透性光刻板进行图形化处理形成所述公共电极、所述栅极以及所述透明电极阵列；
    所述步骤B中使用化学气象沉积法依次沉积所述绝缘层、所述有源层、所述欧姆接触层以及所述第二金属层；
    所述步骤C中使用溅射法沉积所述第二透明导电层。
  2. 根据权利要求1所述的TFT阵列基板的制作方法，其中所述步骤D中使用等离子体对所述有源层的沟道表面进行钝化处理以形成保护层。
  3. 根据权利要求1所述的TFT阵列基板的制作方法，其中所述第一金属层包括铝金属层和第一钼金属层，所述第二金属层包括第一钼金属层、铝金属层以及第二钼金属层。
  4. 根据权利要求1所述的TFT阵列基板的制作方法，其中所述步骤A中使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述第一透明导电层进行湿法刻蚀。
  5. 根据权利要求1所述的TFT阵列基板的制作方法，其中所述步骤B中使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，对所述绝缘层、所述有源层以及所述欧姆接触层进行干法刻蚀。
  6. 一种TFT阵列基板的制作方法，其中包括步骤：
    A、依次沉积第一透明导电层以及第一金属层，进行图形化处理形成公共电极、栅极以及透明电极阵列；
    B、依次沉积绝缘层、有源层、欧姆接触层以及第二金属层，进行图形化处理使所述第二金属层在所述有源层的两侧形成源极和漏极；
    C、沉积第二透明导电层，进行图形化处理形成源极接触层、漏极接触层以及与所述漏极接触层连接的像素电极阵列；
    D、在所述有源层的沟道表面形成保护层。
  7. 根据权利要求6所述的TFT阵列基板的制作方法，其中所述步骤A中使用溅射法依次沉积所述第一透明导电层以及所述第一金属层。
  8. 根据权利要求6所述的TFT阵列基板的制作方法，其中所述步骤A中使用半透性光刻板进行图形化处理形成所述公共电极、所述栅极以及所述透明电极阵列。
  9. 根据权利要求6所述的TFT阵列基板的制作方法，其中所述步骤B中使用化学气象沉积法依次沉积所述绝缘层、所述有源层、所述欧姆接触层以及所述第二金属层。
  10. 根据权利要求6所述的TFT阵列基板的制作方法，其中所述步骤B中使用半透性光刻板进行图形化处理在所述有源层的两侧形成所述源极和所述漏极。
  11. 根据权利要求6所述的TFT阵列基板的制作方法，其中所述步骤C中使用溅射法沉积所述第二透明导电层。
  12. 根据权利要求6所述的TFT阵列基板的制作方法，其中所述步骤D中使用等离子体对所述有源层的沟道表面进行钝化处理以形成保护层。
  13. 根据权利要求6所述的TFT阵列基板的制作方法，其中所述第一金属层包括铝金属层和第一钼金属层，所述第二金属层包括第一钼金属层、铝金属层以及第二钼金属层。
  14. 根据权利要求8所述的TFT阵列基板的制作方法，其中所述步骤A中使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述第一透明导电层进行湿法刻蚀。
  15. 根据权利要求10所述的TFT阵列基板的制作方法，其中所述步骤B中使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，对所述绝缘层、所述有源层以及所述欧姆接触层进行干法刻蚀。
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