WO2013143064A1 - 液晶显示面板以及其制造方法 - Google Patents

液晶显示面板以及其制造方法 Download PDF

Info

Publication number
WO2013143064A1
WO2013143064A1 PCT/CN2012/073091 CN2012073091W WO2013143064A1 WO 2013143064 A1 WO2013143064 A1 WO 2013143064A1 CN 2012073091 W CN2012073091 W CN 2012073091W WO 2013143064 A1 WO2013143064 A1 WO 2013143064A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
pixel electrode
transistor
control voltage
voltage line
Prior art date
Application number
PCT/CN2012/073091
Other languages
English (en)
French (fr)
Inventor
姜佳丽
杜鹏
林师勤
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/502,744 priority Critical patent/US20150009446A1/en
Priority to DE112012006096.2T priority patent/DE112012006096B4/de
Publication of WO2013143064A1 publication Critical patent/WO2013143064A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present invention relates to a liquid crystal display panel and a method of fabricating the same, and, in particular, to a liquid crystal display panel which can increase a pixel aperture ratio without lowering a storage capacitor value, and a method of fabricating the same.
  • LCD monitors have become widely used in a variety of electronic devices such as televisions, mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook screens.
  • PDAs personal digital assistants
  • a display with a high resolution color screen is a display with a high resolution color screen.
  • Transistor liquid crystal displays have become the mainstream of the market due to their high image quality, good space utilization efficiency, low power consumption, and no radiation. At present, the market's performance requirements for liquid crystal displays are toward high contrast (High Contrast Ratio), fast response and large viewing angle.
  • FIG. 1 is a design diagram of a pixel capable of reducing color shift.
  • the pixel 10 employs a design of two sub-pixel electrodes 11, 12.
  • the storage capacitor 17 of the conventional pixel 10 is disposed between the sub-pixel electrode 12 and the control voltage line 16, thus causing the aperture ratio of the sub-pixel electrode 12 to be affected.
  • An object of the present invention is to provide a liquid crystal display panel and a method of fabricating the same that a storage capacitor is disposed between a scan line and a control voltage line to increase an aperture ratio to solve the problems of the prior art.
  • the present invention discloses a liquid crystal display panel comprising a scan line, which is composed of a first metal layer and is disposed on the glass substrate for transmitting a scan signal, and a control voltage line formed by the first metal layer. And on the glass substrate for transmitting a control signal; an insulating layer above the scan line and the control voltage line; and a data line formed by a second metal layer and located on the insulating layer Above, for transmitting a data signal; a first transistor electrically connected to the first sub-pixel electrode; a second transistor electrically connected to the control voltage line and the first transistor; a sub-pixel electrode and a second sub-pixel electrode are both formed by a transparent conductive layer, the second sub-pixel electrode comprises a first conductive region; a common electrode, composed of the first metal layer and located at the a common conductive signal is transmitted on the glass substrate; a second conductive region is formed by the transparent conductive layer, electrically connected to the common electrode; and a lower electrode sheet is formed by the second metal layer and located at the Above
  • the liquid crystal display panel further includes: a protective layer over the second metal layer; a first opening formed in the protective layer and located on the scan line and Between the control voltage lines, the first sub-pixel electrode is electrically connected to the first transistor through the first opening; and a second opening through the protective layer and the insulating layer And being located between the control voltage line and the second sub-pixel electrode such that the common electrode is electrically connected to the second conductive region through the second opening.
  • the first storage capacitor and the second storage capacitor are projected on the glass substrate at a position where the scan line and the control voltage line are projected on the glass substrate. between.
  • the material of the transparent conductive layer is indium tin oxide.
  • the first transistor, the second transistor, the scan line, and the control voltage line are located between the first sub-pixel electrode and the second sub-pixel electrode.
  • the invention further discloses a method for manufacturing a liquid crystal display panel, the manufacturing method comprising: providing a glass substrate; forming a first metal layer on the glass substrate; etching the first metal layer to form a first a gate of the transistor, a gate of a second transistor, a control voltage line, a common voltage line, and a scan line; a gate of the first transistor, a gate of the second transistor, the control voltage Forming an insulating layer on the line, the common voltage line, and the scan line; forming a second metal layer, and etching the second metal layer to form a source and a drain of the first transistor, a source and a drain of the second transistor, a lower electrode tab, and a data line, the lower electrode tab being electrically connected to the drain of the second transistor and located between the control voltage line and the scan line Forming a protective layer over the second metal layer; etching the protective layer to form a first opening and a second opening; forming a transparent conductive layer, and etching the transparent conductive
  • the first storage capacitor and the second storage capacitor are projected on the glass substrate at a position where the scan line and the control voltage line are projected on the glass substrate. between.
  • the material of the transparent conductive layer is indium tin oxide.
  • the first transistor, the second transistor, the scan line, and the control voltage line are located between the first sub-pixel electrode and the second sub-pixel electrode.
  • the liquid crystal display panel of the present invention and the method of fabricating the same are disposed between a scan line and a control voltage line as a lower electrode sheet of an electrode of a storage capacitor, and are the first electrode as another electrode of the storage capacitor.
  • the conductive region and the second conductive region are formed of a transparent conductive layer. Therefore, the position at which the storage capacitor is formed is located between the scan line and the control signal line, so that the second sub-pixel electrode has a larger layout space, and thus the aperture ratio of the second sub-pixel electrode can be increased.
  • FIG. 1 is a design diagram of a pixel which can reduce color shift.
  • FIG. 2 is a simplified schematic view of a liquid crystal display panel of the present invention.
  • Fig. 3 is a partial enlarged view of Fig. 2;
  • 4 to 7 are schematic views showing a method of forming a flat display panel of the present invention.
  • FIG. 2 is a simplified schematic view of a liquid crystal display panel 300 of the present invention
  • FIG. 3 is a partial enlarged view of a region B of FIG.
  • the liquid crystal display panel 300 includes a plurality of data lines, a plurality of scanning lines, a plurality of control voltage lines, a plurality of transistors, and a plurality of pixel units.
  • Each of the pixel units includes transistors 303, 323, a first sub-pixel electrode 331, and a second sub-pixel electrode 332.
  • To simplify the drawing in the following embodiments, only one data line 302, one scan line 301, one common voltage line 305, and one control voltage line 307 are shown.
  • the gate of the first transistor 303 is coupled to the scan line 301, and the source of the first transistor 303 is coupled to the data line 302.
  • the gate of the second transistor 323 is coupled to the control voltage line 307, the source of the second transistor 323 is coupled to the drain of the first transistor 303, and the drain of the second transistor 323 is coupled to the lower electrode plate 308.
  • the drain of the first transistor 303 is coupled to the first sub-pixel electrode 331 and the second sub-pixel electrode 332.
  • Control voltage line 307 is used to provide a control signal.
  • the driving manner of the liquid crystal display panel 300 is as follows: a scan signal output from a gate driver (not shown) is input through the scan line 301, so that the first transistor 303 connected to the scan line 301 is sequentially turned on, and the source driver (not shown) The corresponding data signal is outputted to the first transistor 303 through the data line 302, and the first transistor 303 transmits the data signal to the first sub-pixel electrode 331 and the second sub-pixel electrode 332 to charge the device.
  • the liquid crystal above the first sub-pixel electrode 331 and the second sub-pixel electrode 332 is twisted according to the voltage difference between the data signal and the common voltage of the common voltage line 305, thereby displaying different gray levels.
  • the gate driver outputs the scan signals row by row through a plurality of scan lines to turn on the first transistor 303 of each row, and then the source driver drives the first sub-pixel electrode 331 and the second sub-pixel electrode 332 of each row. Discharge. In this way, the complete display of the liquid crystal display panel 300 can be completed.
  • FIG. 4 to FIG. 7 are schematic diagrams showing a method of forming the flat display panel 300 of the present invention. 4 to 7 are also sectional views of the flat display panel 300 shown in Fig. 3 along the line segment A-A' and the line segment C-C'.
  • a glass substrate 350 is provided as a lower substrate, and then a metal thin film deposition process is performed to form a first metal layer (not shown) on the surface of the glass substrate 350, and a first mask is used.
  • the film is subjected to a first lithography etching to etch the gate 371 of the first transistor 303, the common voltage line 305, the control voltage line 307, and the scan line 301.
  • FIG. 4 does not depict scan line 301, those skilled in the art will appreciate that gate 371 is substantially a portion of scan line 301.
  • an insulating layer 351 made of silicon nitride (SiNx) is deposited to cover the gate electrode 371, the common voltage line 305, the control voltage line 307, and the scan line 301. Continuous deposition of amorphous silicon on the insulating layer 351 (a-Si, Amorphous) Si) layer and a high electron doping concentration of N+ amorphous silicon layer. And then an amorphous silicon layer and a high electron doping concentration of N+ The amorphous silicon layer is covered with a second metal layer (not shown).
  • the amorphous silicon layer is formed to constitute the semiconductor layer 372 while the second metal layer is etched to form the source 373, the drain 374, the lower electrode plate 308, and the data line 302 of the thin film transistor 303.
  • the semiconductor layer 372 includes an amorphous silicon layer 372a as a channel of the transistor 303 and an ohmic contact layer for reducing the impedance (Ohmic) Contact layer) 372b.
  • FIG. 5 does not identify data line 302, those skilled in the art will appreciate that source 373 is substantially part of data line 302.
  • the structure of FIG. 5 is to simultaneously etch the amorphous silicon layer with a second mask, N+ An amorphous silicon layer and a second metal layer.
  • an amorphous silicon layer and an N+ amorphous silicon layer may be formed on the insulating layer 351, and the amorphous silicon layer is first etched by the second mask, N+.
  • An amorphous silicon layer is formed to form the semiconductor layer 372; thereafter, a second metal layer is formed over the semiconductor layer 372 and the insulating layer 351, and the second metal layer is etched by another mask to form a source 373 and a drain of the thin film transistor 303.
  • FIGS. 4 to 6 Please refer to Figure 3 and Figure 6, and then deposit a protective layer of silicon nitride (passivation). Layer 375, and then using a third mask for third lithography etching to remove a portion of the protective layer 375 over the drain 374 up to the surface of the drain 374 to form a first opening (Via) 531, a second The opening 532 and the third opening 533.
  • the position at which the first opening 531 is projected on the glass substrate 350 is between the position where the scanning line 301 / the control voltage line 307 is projected on the glass substrate 350.
  • the second opening 532 extends through the protective layer 375 and the insulating layer 351 and is located between the control voltage line 307 and the second sub-pixel electrode 332.
  • the transistor 323 is not illustrated in FIGS. 4 to 6 , the field The skilled person can understand that the order of formation of the transistor 303 and the transistor 323 is the same, and will not be further described herein.
  • Figure 7 is also a cross-sectional view of the flat display panel 300 of Figure 3 taken along line A-A' and line C-C'.
  • Indium tin oxide is formed on the protective layer 375 (Indium Tin Oxide, ITO) is a transparent conductive layer of material, and then the transparent conductive layer is etched by a fourth mask to form a first sub-pixel electrode 331, a second sub-pixel electrode 332, and a second conductive region 334.
  • the first sub-pixel electrode 331 is electrically connected to the drain 374 of the transistor 303 through the first opening 531.
  • the second sub-pixel electrode 332 is electrically connected to the drain 374 of the transistor 303 through the third opening 533.
  • the common electrode 305 is electrically connected to the second conductive region 334 through the second opening 532.
  • the second sub-pixel electrode 332 includes a first conductive region 332a that spans the control signal line 306.
  • the first conductive region 332a and the second conductive region 334 are both located above the lower electrode tab 308 to form a first storage capacitor Cs1 and a second storage capacitor Cs2.
  • the first storage capacitor Cs1 and the second storage capacitor Cs2 formed by the first conductive region 332a of the lower electrode tab 308 and the second subpixel electrode 332 and the second conductive region 334 are located on the scan line 301 and The voltage line 306 is controlled, so the layout area of the second sub-pixel electrode 332 can be increased.
  • the aperture ratio of the second sub-pixel electrode 332 of the present invention can be increased from 67.17% to 69.9%.

Abstract

一种液晶显示面板和其制造方法，将作为存储电容的电极的下电极片（308）设置到扫描线（301）和控制电压线（307）之间，而作为存储电容的另一电极的第一导电区（332a）以及第二导电区（334）则采用透明导电层。因此形成存储电容的位置是位于扫描线（301）和控制电压线（307）之间，使得第二子像素电极（332）有更大的布局空间，因此可以增加第二子像素电极（332）的开口率。

Description

液晶显示面板以及其制造方法 技术领域
本发明涉及一种液晶显示面板以及其制造方法，特别是涉及一种可以增加像素开口率但不降低存储电容值的液晶显示面板以及其制造方法。
 背景技术
功能先进的显示器渐成为现今消费电子产品的重要特色，其中液晶显示器已经逐渐成为各种电子设备如电视、行动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记型计算机屏幕所广泛应用具有高分辨率彩色屏幕的显示器。
晶体管液晶显示器由于具有高画质、空间利用效率佳、低消耗功率、无辐射等优越特性，因而已逐渐成为市场之主流。目前，市场对于液晶显示器的性能要求是朝向高对比度(High Contrast Ratio)、快速反应与大视角等特性。
但是当使用者在大视角下观看液晶面板时，画面显示的色彩会偏离其原本应该呈现出来的色彩，而使观看到的画面失真。为了解决降低色偏的影响，目前有许多种类的像素结构被开发出来。请参阅图1，图1是一种可以降低色偏的像素的设计图。像素10采用了两子像素电极11、12的设计。传统的像素10的存储电容17是设置在子像素电极12和控制电压线16之间，因此使得子像素电极12的开口率受到影响。
 技术问题
本发明的目的是提供一种液晶显示面板和其制造方法，将存储电容设置在扫描线和控制电压线之间，所提高开口率，以解决现有技术的问题。
 技术解决方案
本发明揭露一种液晶显示面板，其包含一扫描线，由一第一金属层构成且位于所述玻璃基板上，用于传输一扫描信号；一控制电压线，由所述第一金属层构成且位于所述玻璃基板上，用来传输一控制信号；一绝缘层，位于所述扫描线和所述控制电压线之上；一数据线，由一第二金属层构成且位于所述绝缘层之上，用于传输一数据信号；一第一晶体管，电性连接于所述第一子像素电极；一第二晶体管，电性连接于所述控制电压线和所述第一晶体管；一第一子像素电极以及一第二子像素电极，皆由一透明导电层形成，所述第二子像素电极包含一第一导电区；一共通电极，由所述第一金属层构成且位于所述玻璃基板上，用来传输一共通信号；一第二导电区，由所述透明导电层形成，电性连接所述共通电极；一下电极片，由所述第二金属层构成且位于所述绝缘层之上且位于所述扫描线以及所述控制电压线之间，所述下电极片电性连接第二晶体管；及一第一存储电容以及一第二存储电容，所述第一存储电容是由所述下电极片以及所述第二子像素电极的所述第一导电区组成，所述第二存储电容是由所述下电极片以及所述第二导电区组成。
根据本发明的实施例，所述液晶显示面板另包含：一保护层，位于所述第二金属层之上；一第一开孔，开设于所述保护层中且位在所述扫描线和所述控制电压线之间，使得所述第一子像素电极通过所述第一开孔与所述第一晶体管电性连接；以及一第二开孔，贯穿所述保护层和所述绝缘层，且位在所述控制电压线和所述第二子像素电极之间，使得所述共通电极通过所述第二开孔与所述第二导电区电性连接。
根据本发明的实施例，所述第一存储电容和所述第二存储电容投射于所述玻璃基板的位置，是位于所述扫描线和所述控制电压线投射于所述玻璃基板的位置之间。
根据本发明的实施例，所述透明导电层的材料是氧化铟锡。
根据本发明的实施例，所述第一晶体管、所述第二晶体管、所述扫描线和所述控制电压线位于所述第一子像素电极以及所述第二子像素电极之间。
本发明又揭示一种液晶显示面板的制造方法，所述制造方法包含：提供一玻璃基板；形成一第一金属层于所述玻璃基板上；蚀刻所述第一金属层，以形成一第一晶体管的栅极、一第二晶体管的栅极、一控制电压线、一共通电压线以及一扫描线；在所述第一晶体管的栅极、所述第二晶体管的栅极、所述控制电压线、所述共通电压线以及所述扫描线上形成一绝缘层；形成一第二金属层，并蚀刻所述第二金属层，以形成所述第一晶体管的源极和漏极、所述第二晶体管的源极和漏极、一下电极片以及一数据线，所述下电极片与所述第二晶体管的漏极电性连接，且位于所述控制电压线和所述扫描线之间；形成一保护层于所述第二金属层之上；蚀刻所述保护层以形成一第一开孔和一第二开孔；形成一透明导电层，并蚀刻所述透明导电层以形成一第一子像素电极、一第二子像素电极以及一第二导电区，所述第二子像素电极包含一第一导电区，其中所述第一子像素电极通过所述第一开孔与所述晶体管电性连接，所述共通电极通过所述第二开孔与所述第二导电区电性连接，所述下电极片以及所述第二子像素电极的所述第一导电区形成一第一存储电容，所述下电极片以及所述第二导电区形成一第二存储电容。
根据本发明的实施例，所述第一存储电容和所述第二存储电容投射于所述玻璃基板的位置，是位于所述扫描线和所述控制电压线投射于所述玻璃基板的位置之间。
根据本发明的实施例，所述透明导电层的材料是氧化铟锡。
根据本发明的实施例，所述第一晶体管、所述第二晶体管、所述扫描线和所述控制电压线位于所述第一子像素电极以及所述第二子像素电极之间。
 有益效果
相较于现有技术，本发明的液晶显示面板以及其制造方法将作为存储电容的电极的下电极片设置到扫描线和控制电压线之间，而作为作为存储电容的另一电极的第一导电区以及第二导电区则采用透明导电层。因此形成存储电容的位置是位于扫描线和控制信号线之间，使得第二子像素电极有更大的布局空间，因此可以增加第二子像素电极的开口率。
 附图说明
图1是一种可以降低色偏的像素的设计图。
图2是本发明液晶显示面板的简易示意图。
图3是图2的局部放大图。
图4至图7为形成本发明平面显示面板的方法示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施之特定实施例。本发明所提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”、“顶”、“底”、“水平”、“垂直”等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参阅图2和图3，图2是本发明液晶显示面板300的简易示意图，图3是图2区域B的局部放大图。液晶显示面板300包含数条数据线、数条扫描线、数条控制电压线、数个晶体管和数个像素单元。每一像素单元包含晶体管303、323、第一子像素电极331以及第二子像素电极332。为简化图式，在以下实施例中，仅绘示一数据线302、一扫描线301、一共通电压线305及一控制电压线307。第一晶体管303的栅极耦接到扫描线301，第一晶体管303的源极则耦接至数据线302。第二晶体管323的栅极耦接到控制电压线307，第二晶体管323的源极则耦接至第一晶体管303的漏极，第二晶体管323的漏极耦接到下电极板308。此外，第一晶体管303的漏极耦接至第一子像素电极331以及第二子像素电极332。控制电压线307用来提供一控制信号。
液晶显示面板300的驱动方式如下所述：栅极驱动器(图未示)输出的扫描信号通过扫描线301输入，使得连接扫描线301的第一晶体管303依序开启，同时源极驱动器(未图示)则输出对应的数据信号，通过数据线302输入至第一晶体管303，而第一晶体管303则将数据信号传递至第一子像素电极331以及第二子像素电极332，使其充电到所需的电压。而第一子像素电极331以及第二子像素电极332上方的液晶就是依据该数据信号和共通电压线305的共通电压的电压差扭转(twist)，进而显示出不同的灰阶。栅极驱动器会通过数条扫描线一行接一行地输出扫描信号以将每一行的第一晶体管303打开，再由源极驱动器对每一行的第一子像素电极331以及第二子像素电极332进行充放电。如此依序下去，便可完成液晶显示面板300的完整显示。
在以下的揭露之中，将解说本发明平面显示面板300的制程方式。在此请参阅图4至图7，图4至图7为形成本发明平面显示面板300的方法示意图。图4至图7也是图3所示的平面显示面板300沿线段A-A’和线段C-C’的剖面图。
在此请先参阅图4，首先提供一个玻璃基板350当作下基板，接着进行一金属薄膜沉积制程，以于玻璃基板350表面形成一第一金属层（未显示），并利用一第一掩膜来进行第一微影蚀刻，以蚀刻得到第一晶体管303的栅极371、共通电压线305、控制电压线307以及扫描线301。虽然图4并未标示出扫描线301，但本领域的技术人员可以了解栅极371实质上是扫描线301的一部分。
接着请参阅图3和图5，接着沉积以氮化硅(SiNx)为材质的绝缘层351而覆盖栅极371、共通电压线305、控制电压线307以及扫描线301。于绝缘层351上连续沉积非晶硅(a－Si，Amorphous Si)层以及一高电子掺杂浓度的N+ 非晶硅层。再于非晶硅层以及一高电子掺杂浓度的N+ 非晶硅层上覆盖第二金属层(未绘示于图中)。接着利用第二掩膜以蚀刻非晶硅层以及N+ 非晶硅层以构成半导体层372，同时蚀刻该第二金属层以形成薄膜晶体管303的源极373、漏极374、下电极板308以及数据线302。半导体层372包含作为晶体管303通道的非晶硅层372a以及用来降低阻抗的欧姆接触层(Ohmic contact layer)372b。虽然图5并未标示出数据线302，但本领域的技术人员可以了解源极373实质上是数据线302的一部分。
除此之外，在本实施例中，图5的结构是用第二掩膜同时蚀刻非晶硅层、N+ 非晶硅层和第二金属层。另一实施例中，可以先形成非晶硅层、N+ 非晶硅层于绝缘层351之上，先以第二掩膜蚀刻非晶硅层、N+ 非晶硅层以形成半导体层372；之后，形成第二金属层于半导体层372和绝缘层351之上，以另一掩膜蚀刻该第二金属层以形成薄膜晶体管303的源极373、漏极374以及数据线302。
请参阅图3和图6，接着沉积以氮化硅为材质的保护层(passivation layer)375，再利用第三掩膜来进行第三微影蚀刻用以去除漏极374上方的部份保护层375，直至漏极374表面，以形成第一开孔(Via)531、第二开孔532和第三开孔533。第一开孔531投射于玻璃基板350上的位置，是位于扫描线301/控制电压线307投射于玻璃基板350的位置之间。第二开孔532贯穿保护层375和绝缘层351，且位在控制电压线307和第二子像素电极332之间，另外，图4至图6虽然并未所绘示晶体管323，但是本领域的技术人员可以了解晶体管303和晶体管323的形成次序是相同的，在此不另赘述。
请参阅图3和图7，图7也是图3所示的平面显示面板300沿线段A-A’和线段C-C’的剖面图。在保护层375上形成以氧化铟锡物(Indium tin oxide，ITO)为材质的透明导电层，接着利用第四掩膜蚀刻该透明导电层以形成第一子像素电极331、第二子像素电极332和第二导电区334。第一子像素电极331通过第一开孔531与晶体管303的漏极374电性连接。第二子像素电极332通过第三开孔533与晶体管303的漏极374电性连接。共通电极305通过第二开孔532与第二导电区334电性连接。第二子像素电极332包含一第一导电区332a，第一导电区332a跨过控制信号线306。第一导电区332a与第二导电区334皆位于下电极片308的上方，而形成第一存储电容Cs1和第二存储电容Cs2。
如图2所示，由下电极片308和第二子像素电极332的第一导电区332a以及第二导电区334形成的第一存储电容Cs1和第二存储电容Cs2是位在扫描线301和控制电压线306之间，所以第二子像素电极332的布局区域可以增大。相较于图1，本发明的第二子像素电极332的开口率可以由67.17%增加到69.9%。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
序列表自由内容

Claims (9)

  1. 一种液晶显示面板，所述液晶显示面板包括一玻璃基板，其包含：
    一扫描线，由一第一金属层构成且位于所述玻璃基板上，用于传输一扫描信号；
    一控制电压线，由所述第一金属层构成且位于所述玻璃基板上，用来传输一控制信号；
    一绝缘层，位于所述扫描线和所述控制电压线之上；
    一数据线，由一第二金属层构成且位于所述绝缘层之上，用于传输一数据信号；
    一第一晶体管，电性连接于所述第一子像素电极；
    一第二晶体管，电性连接于所述控制电压线和所述第一晶体管；
    一第一子像素电极以及一第二子像素电极，皆由一透明导电层形成，所述第二子像素电极包含一第一导电区；
    一共通电极，由所述第一金属层构成且位于所述玻璃基板上，用来传输一共通信号；
    一第二导电区，由所述透明导电层形成，电性连接所述共通电极；
    一下电极片，由所述第二金属层构成且位于所述绝缘层之上且位于所述扫描线以及所述控制电压线之间，所述下电极片电性连接第二晶体管；及
    一第一存储电容以及一第二存储电容，所述第一存储电容是由所述下电极片以及所述第二子像素电极的所述第一导电区组成，所述第二存储电容是由所述下电极片以及所述第二导电区组成。
  2. 根据权利要求1所述的液晶显示面板，其中所述液晶显示面板另包含：
    一保护层，位于所述第二金属层之上；
    一第一开孔，开设于所述保护层中且位在所述扫描线和所述控制电压线之间，使得所述第一子像素电极通过所述第一开孔与所述第一晶体管电性连接；以及
    一第二开孔，贯穿所述保护层和所述绝缘层，且位在所述控制电压线和所述第二子像素电极之间，使得所述共通电极通过所述第二开孔与所述第二导电区电性连接。
  3. 根据权利要求2所述的液晶显示面板，其中所述第一存储电容和所述第二存储电容投射于所述玻璃基板的位置，是位于所述扫描线和所述控制电压线投射于所述玻璃基板的位置之间。
  4. 根据权利要求1所述的液晶显示面板，其中所述透明导电层的材料是氧化铟锡。
  5. 根据权利要求1所述的液晶显示面板，其中所述第一晶体管、所述第二晶体管、所述扫描线和所述控制电压线位于所述第一子像素电极以及所述第二子像素电极之间。
  6. 一种液晶显示面板的制造方法，其包含：
    提供一玻璃基板；
    形成一第一金属层于所述玻璃基板上；
    蚀刻所述第一金属层，以形成一晶体管的栅极、一控制电压线、一共通电压线以及一扫描线；
    在所述晶体管的栅极、所述控制电压线、所述共通电压线以及所述扫描线上形成一绝缘层；
    形成一第二金属层，并蚀刻所述第二金属层，以形成所述晶体管的源极和漏极、一下电极片以及一数据线，所述下电极片位于所述控制电压线和所述扫描线之间；
    形成一保护层于所述第二金属层之上；
    蚀刻所述保护层以形成一第一开孔和一第二开孔；
    形成一透明导电层，并蚀刻所述透明导电层以形成一第一子像素电极、一第二子像素电极以及一第二导电区，所述第二子像素电极包含一第一导电区，其中所述第一子像素电极通过所述第一开孔与所述晶体管电性连接，所述共通电极通过所述第二开孔与所述第二导电区电性连接，所述下电极片以及所述第二子像素电极的所述第一导电区形成一第一存储电容，所述下电极片以及所述第二导电区形成一第二存储电容。
  7. 根据权利要求6所述的制造方法，其中所述第一存储电容和所述第二存储电容投射于所述玻璃基板的位置，是位于所述扫描线和所述控制电压线投射于所述玻璃基板的位置之间。
  8. 根据权利要求6所述的制造方法，其中所述透明导电层的材料是氧化铟锡。
  9. 根据权利要求6所述的制造方法，其中所述晶体管、所述扫描线和所述控制电压线位于所述第一子像素电极以及所述第二子像素电极之间。
PCT/CN2012/073091 2012-03-26 2012-03-27 液晶显示面板以及其制造方法 WO2013143064A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/502,744 US20150009446A1 (en) 2012-03-26 2012-03-27 Lcd panel and a method of manufacturing the same
DE112012006096.2T DE112012006096B4 (de) 2012-03-26 2012-03-27 LCD-Panel und Verfahren zur Herstellung desselben

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210081847.8 2012-03-26
CN201210081847.8A CN102608816B (zh) 2012-03-26 2012-03-26 液晶显示面板以及其制造方法

Publications (1)

Publication Number Publication Date
WO2013143064A1 true WO2013143064A1 (zh) 2013-10-03

Family

ID=46526293

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/073091 WO2013143064A1 (zh) 2012-03-26 2012-03-27 液晶显示面板以及其制造方法

Country Status (4)

Country Link
US (1) US20150009446A1 (zh)
CN (1) CN102608816B (zh)
DE (1) DE112012006096B4 (zh)
WO (1) WO2013143064A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI683152B (zh) * 2018-12-28 2020-01-21 友達光電股份有限公司 畫素結構

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102059371B1 (ko) * 2013-05-24 2019-12-27 엘지디스플레이 주식회사 액정 디스플레이 장치와 이의 제조방법
KR102098639B1 (ko) * 2013-09-30 2020-04-08 코오롱인더스트리 주식회사 고분자 전해질막, 이의 제조 방법 및 이를 포함하는 막-전극 어셈블리
TWI570492B (zh) * 2015-09-18 2017-02-11 友達光電股份有限公司 畫素結構
CN105895706A (zh) * 2016-07-01 2016-08-24 深圳市华星光电技术有限公司 薄膜晶体管及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2702338Y (zh) * 2002-07-11 2005-05-25 精工爱普生株式会社 电光学装置和电子设备
CN101728399A (zh) * 2008-10-13 2010-06-09 华映视讯（吴江）有限公司 薄膜晶体管数组基板及其制造方法
JP2010237687A (ja) * 2010-05-21 2010-10-21 Seiko Epson Corp 電気光学装置およびプロジェクタ
CN101978315A (zh) * 2008-04-25 2011-02-16 夏普株式会社 液晶显示装置、电视接收机
JP2011128334A (ja) * 2009-12-17 2011-06-30 Seiko Epson Corp 液晶装置および電子機器

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1031873A3 (en) * 1999-02-23 2005-02-23 Sel Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
US7557886B2 (en) * 2004-06-29 2009-07-07 Lg Display Co., Ltd. Liquid crystal display device and method of fabricating the same
JP4438665B2 (ja) * 2005-03-29 2010-03-24 シャープ株式会社 液晶表示装置
KR101202530B1 (ko) * 2005-12-27 2012-11-16 엘지디스플레이 주식회사 액정표시패널 및 그 제조방법
KR101320494B1 (ko) * 2006-04-12 2013-10-22 엘지디스플레이 주식회사 수평전계방식 액정표시장치 및 그 제조방법
TWI380110B (en) * 2009-04-02 2012-12-21 Au Optronics Corp Pixel array, liquid crystal display panel, and electro-optical apparatus
KR101623160B1 (ko) * 2009-09-16 2016-05-23 삼성디스플레이 주식회사 액정 표시 장치
US8259249B2 (en) * 2009-10-12 2012-09-04 Samsung Electronics Co., Ltd. Display substrate, method of manufacturing the display substrate and display device having the display substrate
TWI424234B (zh) * 2009-10-26 2014-01-21 Au Optronics Corp 畫素陣列、聚合物穩定配向液晶顯示面板以及光電裝置
CN101738804B (zh) * 2009-12-30 2011-10-05 友达光电股份有限公司 像素结构
KR101702105B1 (ko) * 2010-06-16 2017-02-03 삼성디스플레이 주식회사 액정 표시 장치 및 그 구동 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2702338Y (zh) * 2002-07-11 2005-05-25 精工爱普生株式会社 电光学装置和电子设备
CN101978315A (zh) * 2008-04-25 2011-02-16 夏普株式会社 液晶显示装置、电视接收机
CN101728399A (zh) * 2008-10-13 2010-06-09 华映视讯（吴江）有限公司 薄膜晶体管数组基板及其制造方法
JP2011128334A (ja) * 2009-12-17 2011-06-30 Seiko Epson Corp 液晶装置および電子機器
JP2010237687A (ja) * 2010-05-21 2010-10-21 Seiko Epson Corp 電気光学装置およびプロジェクタ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI683152B (zh) * 2018-12-28 2020-01-21 友達光電股份有限公司 畫素結構

Also Published As

Publication number Publication date
US20150009446A1 (en) 2015-01-08
CN102608816B (zh) 2014-07-16
CN102608816A (zh) 2012-07-25
DE112012006096B4 (de) 2020-08-13
DE112012006096T5 (de) 2015-01-22

Similar Documents

Publication Publication Date Title
US8988624B2 (en) Display pixel having oxide thin-film transistor (TFT) with reduced loading
WO2013086746A1 (zh) 液晶显示面板以及其制造方式
US10209596B2 (en) Pixel structure, method of manufacturing the same, array substrate and display device
US10197870B2 (en) Array substrate and display device
US10217778B2 (en) Array substrate and manufacturing method thereof
JP6370003B2 (ja) 画素構造及びその製造方法
WO2017016014A1 (zh) Coa阵列基板及液晶面板
WO2013143064A1 (zh) 液晶显示面板以及其制造方法
WO2018126676A1 (zh) 像素结构及其制作方法、阵列基板和显示装置
WO2013056460A1 (zh) 液晶显示面板及形成液晶显示面板的方法
TWI676837B (zh) 畫素陣列基板
WO2021184506A1 (zh) 液晶显示面板
WO2013139040A1 (zh) 液晶显示面板以及其制造方法
WO2023217261A1 (zh) 显示面板和显示装置
CN105093756A (zh) 液晶显示像素结构及其制作方法
WO2015180302A1 (zh) 阵列基板及其制备方法、显示装置
TWI656386B (zh) 顯示裝置及其形成方法
WO2023000406A1 (zh) 显示面板及显示装置
TWI690838B (zh) 畫素陣列基板
WO2017143660A1 (zh) 阵列基板、显示面板以及液晶显示装置
TW201901267A (zh) 陣列基板及液晶顯示面板
US9477127B2 (en) Thin film transistor substrate, manufacture method thereof and liquid crystal display
WO2023015646A1 (zh) 显示面板及显示面板制作方法
US20130106679A1 (en) Lcd panel and method of manufacturing the same
WO2013063814A1 (zh) 液晶显示面板及其制造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13502744

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12872537

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 112012006096

Country of ref document: DE

Ref document number: 1120120060962

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12872537

Country of ref document: EP

Kind code of ref document: A1