WO2019006832A1 - 一种场效应晶体管及其制备方法 - Google Patents

一种场效应晶体管及其制备方法 Download PDF

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Publication number
WO2019006832A1
WO2019006832A1 PCT/CN2017/098256 CN2017098256W WO2019006832A1 WO 2019006832 A1 WO2019006832 A1 WO 2019006832A1 CN 2017098256 W CN2017098256 W CN 2017098256W WO 2019006832 A1 WO2019006832 A1 WO 2019006832A1
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Prior art keywords
layer
pattern layer
black phosphorus
substrate
active layer
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PCT/CN2017/098256
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English (en)
French (fr)
Inventor
谢华飞
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/557,456 priority Critical patent/US10418490B2/en
Publication of WO2019006832A1 publication Critical patent/WO2019006832A1/zh

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    • H01L29/786—
    • H01L29/24—
    • H01L29/66969—

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a field effect transistor and a method of fabricating the same.
  • the field effect transistor utilizes the surface effect of the semiconductor to control the depletion or accumulation of holes and electrons on the surface of the semiconductor active layer by the gate voltage, determines the conduction state of the channel, and realizes the switching function.
  • Field effect transistors are widely used in the manufacture of electronic devices and integrated circuits due to their simple principle, mature process and high reliability.
  • the performance of a field effect transistor is affected by many factors such as process, process, material and device structure.
  • the channel material and device structure fundamentally determine the mobility and working efficiency of the field effect transistor. .
  • Two-dimensional nanomaterials such as graphene and transition metal sulfides have shown extraordinary application potential in many fields such as electronics, sensing and optoelectronic devices due to their excellent physical and structural properties.
  • graphene has been widely studied as the most representative two-dimensional material, and it has ultra-high carrier mobility, but the lack of band gap seriously hinders the application of graphene in semiconductor devices such as field effect transistors.
  • the disulfide bond in the transition metal sulfide has a significant band gap and exhibits excellent switching ratio characteristics in the transistor.
  • the structural defects of the disulfide bond may cause a decrease in electron mobility, thereby affecting its electrical properties. Therefore, a method of introducing a band gap in graphene is used.
  • Black phosphorus has attracted wide attention in the scientific community due to its excellent performance. It has a corrugated layered structure similar to but different from the graphene sheet layer structure, and has a semiconductor gap which is not found in graphene. More importantly, its semiconductor band gap is the direct band gap, that is, the bottom of the electron conduction band and the top of the non-conductive band are at the same position. Therefore, it is considered by the scientific community to be a "super material" in two-dimensional materials. At the same time, due to the quantum confinement effect, the black phosphorus quantum dots have better photoelectric properties than the black phosphorus bulk materials, and can be widely used in the fields of photovoltaics and transistors.
  • the invention mainly provides a field effect transistor and a preparation method thereof, aiming at solving the problem of how to prepare a field effect transistor by using a black phosphorus nanosheet or a black phosphorus quantum dot.
  • a technical solution adopted by the present invention is to provide a method for fabricating a field effect transistor, wherein the method comprises forming a solution on a substrate by a solution containing black phosphorus nanosheets or black phosphorus quantum dots.
  • a source layer a source pattern layer and a drain pattern layer in contact with the active layer; wherein the forming an active layer over the substrate by using a solution containing black phosphorus nanosheets or black phosphorus quantum dots comprises: using Spin-coating the solution containing the black phosphorus nanosheet or black phosphorus quantum dot on the substrate to form a black phosphorus film layer; vacuum drying the black phosphor film layer to form a black phosphorus active layer; Forming the source pattern layer and the drain pattern layer in contact with the active layer includes: forming a conductive material layer on the substrate and transferring the conductive material layer onto the active layer by a transfer process; passing plasma The conductive material layer is patterned by bulk photolithography to form the source pattern layer and the drain pattern layer.
  • another technical solution adopted by the present invention is to provide a method for preparing a field effect transistor, wherein the method comprises forming a solution on a substrate by a solution containing a black phosphorus nanosheet or a black phosphorus quantum dot. a source layer; a source pattern layer and a drain pattern layer in contact with the active layer.
  • another technical solution adopted by the present invention is to provide a field effect transistor, wherein the field effect transistor includes an active layer formed over a substrate, the active layer including black phosphorus nanosheets Or a black phosphor quantum dot; a source pattern layer and a drain pattern layer in contact with the active layer.
  • the present invention forms an active layer above the substrate by a solution containing black phosphorus nanosheets or black phosphorus quantum dots; forming a source pattern layer in contact with the active layer And the method of draining the pattern layer, using the black phosphorus nanosheet or the black phosphorus quantum dot as the material to prepare the active layer in the field effect transistor, enriching the preparation material of the field effect transistor, and reducing the metal dot film layer used in the prior art Environmental pollution during the preparation of the active layer, while reducing the dependence on metal elements.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a field effect transistor according to the present invention
  • FIG. 2 is a schematic structural view of a first embodiment of a field effect transistor provided by the present invention.
  • FIG. 3 is a schematic diagram of a specific process of step S13 in FIG. 1;
  • step S14 in FIG. 1 is a schematic diagram of a specific process of step S14 in FIG. 1;
  • FIG. 5 is a schematic flow chart of a second embodiment of a method for fabricating a field effect transistor according to the present invention.
  • FIG. 6 is a schematic structural view of a second embodiment of a field effect transistor provided by the present invention.
  • FIG. 7 is a schematic flow chart of a third embodiment of a method for fabricating a field effect transistor according to the present invention.
  • FIG. 8 is a schematic structural view of a third embodiment of a field effect transistor provided by the present invention.
  • a first embodiment of a method for fabricating a field effect transistor provided by the present invention includes:
  • a recess at a position of the bottom gate pattern layer 102 as shown in FIG. 2 is formed on the substrate 101 by a nanoimprint process, and then a conductive material is deposited to form a bottom gate pattern.
  • the layer 102 may also be formed by forming a conductive material together with the substrate 101 to form the substrate 101 doped with the conductive material, and depositing a film of the conductive material on the substrate 101 by physical vapor deposition, and then passing through the photoresist.
  • a photolithography process of coating, exposing, developing, and stripping forms a bottom gate pattern layer 102; a layer of insulating material of a certain thickness may be deposited on the substrate 101 by physical vapor deposition or plasma vapor deposition to form a bottom gate insulating layer.
  • Layer 103 A photolithography process of coating, exposing, developing, and stripping forms a bottom gate pattern layer 102; a layer of insulating material of a certain thickness may be deposited on the substrate 101 by physical vapor deposition or plasma vapor deposition to form a bottom gate insulating layer.
  • the substrate 101 is a quartz substrate, a glass substrate or a silicon wafer substrate including but not limited to;
  • the conductive material is a conductive carbon material including but not limited to graphene and metal type carbon nano, and the insulating material is including, but not limited to, oxidation. Insulation of silicon, aluminum oxide, silicon nitride or ionic gel.
  • the isolation layer 104 is an organic isolation layer.
  • the substrate 101 after the completion of the above step S11 is immersed and rinsed with a solution of acetone, methanol and isopropyl alcohol, and dried at a certain temperature and then placed in an environment having hexamethyldisilazide vapor for three minutes to An organic isolation layer is formed on the bottom gate insulating layer 103, and the organic isolation layer has a good waterproof and oxygen barrier effect.
  • the material of the isolation layer 104 is a material of, but not limited to, hexamethyldisilazane or polymethyl methacrylate.
  • the solution containing the black phosphorus nanosheet or the black phosphorus quantum dot can be prepared by, but not limited to, a liquid stripping method, a micro mechanical stripping method, an electrochemical method, and a laser ablation method, for example, under anaerobic conditions, the block is The black phosphorus is immersed in an organic solvent to form a solution, and an inert gas is introduced and is in 2000. Stir at rpm for 25 h, then centrifuge the solution at 8000 rpm in a glove box with a water oxygen content of less than 5 ppm.
  • the organic solvent is N-methylpyrrolidone or absolute ethanol.
  • the step S13 may specifically include:
  • S131 spin-coating a solution containing black phosphorus nanosheets or black phosphorus quantum dots on the substrate 101 to form a black phosphorus film layer;
  • the above solution containing black phosphorus nanosheets or black phosphorus quantum dots may be dropped onto the separator 104 in a glove box containing a high purity inert gas, and a certain thickness is formed in a certain period of time by spin coating. Black phosphorus film layer.
  • the inert gas is nitrogen
  • the number of revolutions of the spin coating method is 3000 rpm
  • the spin coating time is 30 s.
  • the black phosphor film layer is evaporated at a low temperature to form a black phosphorus active layer.
  • the black phosphorus film layer is baked in a vacuum environment of 80 ° C for a certain time, and after the baking is finished, the black phosphorus film layer is patterned to obtain a black phosphorus active layer, in other
  • the patterning process of the black phosphor film layer in the step S132 may be performed after the patterning process of the source pattern layer 106 and the drain pattern layer 107 in step S14.
  • step S14 may specifically include:
  • a layer of a conductive material is deposited on the copper foil by chemical vapor deposition, and then the conductive material layer is transferred to the active layer 105 in step S13 by a transfer technique.
  • S142 patterning a conductive material layer by plasma photolithography to form a source pattern layer 106 and a drain pattern layer 107;
  • the black phosphor film layer of the step S132 is further patterned by reactive ion etching to form the active layer 105. .
  • the conductive material is a conductive carbon material including, but not limited to, graphene and metal type carbon nano.
  • a silicon oxide layer covering the source pattern layer 106, the drain pattern layer 107, and the active layer 105 is formed on the isolation layer 104 by a chemical vapor deposition method as the protective layer 108.
  • the via hole 1081 communicating with the source pattern layer 106 or the drain pattern layer 107 is etched in the protective layer 108 by a photolithography process of photoresist coating, exposure, development, and lift-off.
  • the via is connected to the drain pattern layer 107 as an example.
  • the steps S21, S22, S23 and S24 are the same as the steps S11, S12, S13 and S14 in the first embodiment. This is not described again.
  • This embodiment also includes:
  • insulating material layer may be deposited on the isolation layer 204 by physical vapor deposition or plasma vapor deposition to form the top gate insulating layer 209.
  • the insulating material is an insulating material including, but not limited to, silicon oxide, aluminum oxide, silicon nitride or ionic gel.
  • a conductive material film may be deposited on the top gate insulating layer 209 by a spin coating method or a pulling method, and a plasma etching method is used to form a patterned conductive material film after vacuum low temperature evaporation, thereby forming a top gate pattern layer.
  • a conductive material film may be deposited on the top gate insulating layer 209 by physical vapor deposition or chemical vapor deposition, and then a top gate pattern is formed by a photolithography process of exposure, development, etching, and lift-off. Layer 210.
  • the conductive material is a conductive carbon material including, but not limited to, graphene and metal type carbon nano.
  • silicon oxide is deposited on the top gate insulating layer 209 by chemical vapor deposition to form a protective layer 208 covering the top gate pattern layer 210 and the top gate insulating layer 209.
  • a via 2081 communicating with the source pattern layer 206 or the drain pattern layer 207 is etched in the protective layer 208 and the top gate insulating layer 209 by a photolithography process of photoresist coating, exposure, development, and lift-off.
  • a third embodiment of a method for fabricating a field effect transistor provided by the present invention includes:
  • the isolation layer 302 is an organic isolation layer.
  • the substrate 301 is immersed and rinsed with a solution of acetone, methanol, and isopropyl alcohol, and dried at a certain temperature and placed in an environment having hexamethyldisilazide vapor for three minutes to form an organic barrier on the substrate 301.
  • Layer, organic barrier layer has a good waterproof and oxygen barrier effect.
  • the material of the isolation layer 302 is a material of, but not limited to, hexamethyldisilazane or polymethyl methacrylate.
  • This step S32 is the same as step S13 in the first embodiment described above, and details are not described herein again.
  • step S33 is the same as step S14 in the first embodiment described above, and details are not described herein again.
  • insulating material layer may be deposited on the isolation layer 302 by physical vapor deposition or plasma vapor deposition to form the top gate insulating layer 306;
  • the insulating material is an insulating material including, but not limited to, silicon oxide, aluminum oxide, silicon nitride or ionic gel.
  • a conductive material film may be deposited on the top gate insulating layer 306 by a spin coating method or a pulling method, and a plasma etching method is used to form a patterned conductive material film after vacuum low temperature evaporation, thereby forming a top gate pattern layer.
  • a conductive material film may be deposited on the top gate insulating layer 306 by physical vapor deposition or chemical vapor deposition, and then a top gate pattern is formed by a photolithography process of exposure, development, etching, and lift-off. Layer 307.
  • the conductive material is a conductive carbon material including, but not limited to, graphene, metal type carbon nanotubes.
  • silicon oxide is deposited on the top gate insulating layer 306 by chemical vapor deposition to form a protective layer 308 covering the top gate pattern layer 307.
  • a via 3081 communicating with the source pattern layer 304 or the drain pattern layer 305 is etched in the protective layer 308 and the top gate insulating layer 306 by a photolithography process of photoresist coating, exposure, development, and lift-off.
  • a first embodiment of a field effect transistor provided by the present invention includes a bottom gate pattern layer 102 and a bottom gate insulating layer 103 sequentially formed on a substrate 101, and an isolation layer 104 formed on the substrate 101, formed over the substrate 101.
  • the isolation layer 104 is formed on the bottom gate insulating layer 103, and the active layer 105 is formed on the isolation layer 104 and includes black phosphorus nanosheets or black phosphorus quantum dots.
  • each layer in this embodiment is prepared by using the corresponding steps in the first embodiment of the method for fabricating the field effect transistor described above, and details are not described herein again.
  • the second embodiment of the field effect transistor provided by the present invention further includes a top gate insulating layer 209 and a top gate pattern layer 210.
  • the other structures in this embodiment are the same as the first embodiment of the field effect transistor described above, and are no longer used herein. Narration.
  • the top gate insulating layer 209 covers the source pattern layer 206, the drain pattern layer 207, and the active layer 205, and the top gate pattern layer 210 is formed on the bottom gate insulating layer 209.
  • each layer in this embodiment is prepared by using the corresponding steps in the second embodiment of the method for fabricating the field effect transistor described above, and details are not described herein again.
  • a third embodiment of the field effect transistor includes: an isolation layer 302 and an active layer 303 over the substrate 301 , a source pattern layer 304 and a drain pattern layer 305 in contact with the active layer 303 , a top gate insulating layer 306 covering the source pattern layer 304, the drain pattern layer 305 and the active layer 303, a top gate pattern layer 307 formed on the top gate insulating layer 306, a top gate insulating layer 306, and a top gate pattern layer Protective layer 308.
  • each layer in this embodiment is prepared by using the corresponding steps in the third embodiment of the above-mentioned field effect transistor manufacturing method, and details are not described herein again.
  • the present invention forms an active layer over a substrate by a solution containing black phosphorus nanosheets or black phosphorus quantum dots; a method of forming a source pattern layer and a drain pattern layer in contact with the active layer,
  • a variety of field effect transistor structures and solution methods are used to prepare active layers in field effect transistors using black phosphorus nanosheets or black phosphorus quantum dots.
  • the process is simple to reduce production cost, enrich the preparation materials of field effect transistors, and reduce the environment.
  • the pollution and dependence on metal elements, while using carbon materials such as graphene or carbon nano to prepare source, drain and top gate pattern layers, can form an effective ohmic contact with the black phosphorus active layer, reducing contact resistance.

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Abstract

一种场效应晶体管及其制备方法，通过这种方法，使用溶液法以黑磷纳米片或黑磷量子点为材料制备场效应晶体管中的有源层（105、205、303），制程简单降低生产成本，丰富了场效应晶体管的制备材料，减少了环境的污染及对金属元素的依赖性，同时采用石墨烯或碳纳米等碳材料制备源极图案层（106、206、304）、漏极图案层（107、207、305）与顶栅图案层（210、307），可与黑磷有源层（105、205、303）形成有效的欧姆接触，降低接触电阻。

Description

一种场效应晶体管及其制备方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种场效应晶体管及其制备方法。
【背景技术】
场效应晶体管是利用半导体的表面效应，以栅极电压控制半导体有源层表面的空穴与电子耗尽或积累，决定沟道的导通状况，实现开关功能。场效应晶体管因原理简单，工艺成熟，可靠性高，现已普遍应用于电子器件和集成电路的制造。场效应晶体管的性能受到工艺、制程、材料和器件结构等多个因素的影响，其中沟道材料和器件结构从根本上决定着场效应晶体管的迁移率和工作效率。.
二维纳米材料如石墨烯、过渡金属硫化物等，以其优异的物理和结构特性已经在电子、传感和光电器件等多领域表现出非凡的应用潜力。其中，石墨烯作为最具代表性的二维材料已经被广泛研究，它具有超高的载流子迁移率，但缺乏带隙却严重阻碍了石墨烯在半导体器件如场效应晶体管中的应用，而过渡金属硫化物中的二硫化钥具有明显的带隙，且在晶体管中表现出优异的开关比特性。然而，二硫化钥的结构缺陷可能会导致电子迁移率的降低，从而影响它的电学性能。因此，在石墨烯中引入带隙的方法被使用。
黑磷由于其优异的性能得到了科学界广泛关注，它有着类似但不同于石墨烯片层装结构的波形层状结构，并且具备石墨烯所没有的半导体间隙。更重要的是它的半导体带隙是直接带隙，即电子导电能带底部和非导电能带顶部在同一位置。因而被科学界认为是二维材料中的“超级材料”。同时由于量子限域效应，黑磷量子点具有比黑磷块体材料更优异的光电性能，可在广泛应用于光伏、晶体管领域得到广泛的应用。
【发明内容】
本发明主要是提供一种场效应晶体管及其制备方法，旨在解决如何使用黑磷纳米片或黑磷量子点制备场效应晶体管的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种场效应晶体管的制备方法，其中，所述方法包括通过含有黑磷纳米片或黑磷量子点的溶液在基板的上方形成有源层；形成与所述有源层接触的源极图案层和漏极图案层；其中，所述通过含有黑磷纳米片或黑磷量子点的溶液在基板的上方形成有源层包括：使用旋涂法在所述基板的上方将所述含有黑磷纳米片或黑磷量子点的溶液旋涂形成黑磷膜层；低温真空蒸发所述黑磷膜层以形成黑磷有源层；所述形成与所述有源层接触的源极图案层和漏极图案层包括：在基体上形成导电材料层并通过转印工艺将所述导电材料层转移至所述有源层上；通过等离子体光刻法对所述导电材料层图案化处理以形成所述源极图案层和所述漏极图案层。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种场效应晶体管的制备方法，其中，该方法包括通过含有黑磷纳米片或黑磷量子点的溶液在基板的上方形成有源层；形成与所述有源层接触的源极图案层和漏极图案层。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种场效应晶体管，其中，该场效应晶体管包括在基板的上方形成的有源层，所述有源层包括黑磷纳米片或黑磷量子点；与所述有源层接触的源极图案层和漏极图案层。
本发明的有益效果是：区别于现有技术的情况，本发明通过含有黑磷纳米片或黑磷量子点的溶液在基板的上方形成有源层；形成与有源层接触的源极图案层和漏极图案层的方法，使用黑磷纳米片或黑磷量子点为材料制备场效应晶体管中的有源层，丰富了场效应晶体管的制备材料，减少了现有技术中使用金属点膜层制备有源层时对环境的污染，同时降低了对金属元素的依赖性。
【附图说明】
图1是本发明提供的场效应晶体管的制备方法第一实施例的流程示意图；
图2是本发明提供的场效应晶体管第一实施例的结构示意图；
图3是图1中步骤S13的具体流程示意图；
图4是图1中步骤S14的具体流程示意图；
图5是本发明提供的场效应晶体管的制备方法第二实施例的流程示意图；
图6是本发明提供的场效应晶体管第二实施例的结构示意图；
图7是本发明提供的场效应晶体管的制备方法第三实施例的流程示意图；
图8是本发明提供的场效应晶体管第三实施例的结构示意图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种场效应晶体管及其制备方法做进一步详细描述。
参阅图1和图2，本发明提供的场效应晶体管的制备方法第一实施例包括：
S11：在基板101上依次形成底栅图案层102及覆盖底栅图案层102的底栅绝缘层103；
可选的，可将基板101清洗干净之后，通过纳米压印工艺在基板101上形成如图2所示的底栅图案层102所处位置的凹槽，然后再沉积导电材料以形成底栅图案层102，也可以在形成基板101时将导电材料与基板101共同形成，以形成掺杂有导电材料的基板101，还可以通过物理气相沉积法在基板101上沉积导电材料膜，然后通过光阻涂布、曝光、显影及剥离的光刻工艺形成底栅图案层102；进一步地可通过物理气相沉积法或等离子体气相沉积法在基板101上沉积一定厚度的绝缘材料层，以形成底栅绝缘层103。
可选的，基板101是包括但不限于的石英基板、玻璃基板或硅片基板；导电材料是包括但不限于石墨烯、金属型碳纳米的导电碳材料，绝缘材料是包括但不限于的氧化硅、氧化铝、氮化硅或离子凝胶的绝缘材料。
S12：在基板101的上方形成隔离层104；
可选的，隔离层104为有机隔离层。
具体地，将完成上述步骤S11后的基板101用丙酮、甲醇和异丙醇的溶液浸泡冲洗，并在一定温度烘干之后放入具有六甲基二硅胺蒸汽的环境中三分钟，以在底栅绝缘层103上形成有机隔离层，有机隔离层具有很好的防水隔氧效果。
可选的，隔离层104的材料为但不限于六甲基二硅胺或聚甲基丙烯酸甲酯的材料。
S13：通过含有黑磷纳米片或黑磷量子点的溶液在基板101的上方形成有源层105；
其中，含有黑磷纳米片或黑磷量子点的溶液可通过包括但不限于液态剥离方法、微机械剥离法、电化学方法和激光消融方法制备而成，比如：在无氧条件下，将块状黑磷浸入有机溶剂中形成溶液，通入惰性气体并在2000 rpm转速下搅拌25h，然后在水氧含量低于5ppm的手套箱中将溶液进行转速为8000 rpm的低速离心10 min，最后收集离心转动后的上清液，即可得到纳米黑磷片溶液；还可以在无氧条件下将100μm大小的黑磷块状颗粒分散在有机溶剂中形成溶液，然后将该溶液先在功率为1000W~1400W下进行探针式超声2~4h，然后在功率为200W~400W下进行水浴超声8~12h，最后在水氧含量低于5ppm的手套箱中进行转速为8000 rpm的离心20min，并收集上清液，即可得到黑磷量子点溶液。
可选的，有机溶剂为N-甲基吡咯烷酮或无水乙醇。
参阅图3，该步骤S13可具体包括：
S131：使用旋涂法在基板101的上方将含有黑磷纳米片或黑磷量子点的溶液旋涂形成黑磷膜层；
具体地，可在含有高纯惰性气体的手套箱中，将上述的含有黑磷纳米片或黑磷量子点的溶液滴加至隔离层104上，并使用旋涂法在一定时间内形成一定厚度的黑磷膜层。
可选的，惰性气体为氮气，旋涂法的转数为3000rpm，旋涂时间为30s。
S132：低温真空蒸发黑磷膜层以形成黑磷有源层。
可选的，在80℃的真空环境中对黑磷膜层进行烘烤一定时间，并在烘烤结束之后，对黑磷膜层进行图案化处理，即可得到黑磷有源层，在其他实施例中，该步骤S132中对黑磷膜层进行图案化处理也可以在步骤S14中源极图案层106及漏极图案层107的图案化处理之后进行。
S14：形成与有源层105接触的源极图案层106及漏极图案层107；
参阅图4，该步骤S14可具体包括：
S141：在基体上形成导电材料层并通过转印工艺将该导电材料层转移至有源层105上；
可选的，通过化学气相沉积法在铜箔上沉积导电材料层，然后通过转印技术将该导电材料层转移至步骤S13中的有源层105上。
S142：通过等离子体光刻法对导电材料层图案化处理以形成源极图案层106和漏极图案层107；
可选的，在其他实施例中，在形成源极图案层106及漏极图案层107之后，还使用反应型离子刻蚀法对步骤S132黑磷膜层进行图案化处理以形成有源层105。
可选的，导电材料是包括但不限于石墨烯、金属型碳纳米的导电碳材料。
S15：形成覆盖源极图案层106、漏极图案层107及有源层105的保护层108；
可选的，通过化学气相沉积法在隔离层104上形成覆盖源极图案层106、漏极图案层107及有源层105的氧化硅层以作为保护层108。
S16：开设贯穿保护层108且连通源极图案层106或漏极图案层107的过孔1081。
具体地，通过光阻涂布、曝光、显影及剥离的光刻工艺在保护层108中蚀刻出与源极图案层106或漏极图案层107连通的过孔1081，本实施例图示中以过孔与漏极图案层107连通为例。
共同参阅图5及图6，本发明提供的场效应晶体管的制备方法第二实施例中步骤S21、S22、S23及S24与上述第一实施例中的步骤S11、S12、S13及S14相同，在此不再赘述，本实施例还包括：
S25：形成覆盖源极图案层206、漏极图案层207及有源层205的顶栅绝缘层209；
具体地，可通过物理气相沉积法或等离子体气相沉积法在隔离层204上沉积一定厚度的绝缘材料层以形成顶栅绝缘层209。
可选的，绝缘材料是包括但不限于的氧化硅、氧化铝、氮化硅或离子凝胶的绝缘材料。
S26：在顶栅绝缘层209上形成顶栅图案层210；
可选的，可通过旋涂法或提拉法在顶栅绝缘层209上沉积导电材料膜，并在真空低温蒸发之后使用等离子蚀刻法以形成图案化的导电材料膜，进而形成顶栅图案层210；在其他实施例中，也可以使用物理气相沉积法或化学气相沉积法在顶栅绝缘层209上沉积导电材料膜，然后通过曝光、显影、刻蚀和剥离的光刻工艺形成顶栅图案层210。
可选的，导电材料是包括但不限于石墨烯、金属型碳纳米的导电碳材料。
S27：形成覆盖顶栅图案层210及顶栅绝缘层209的保护层208。
可选的，通过化学气相沉积法在顶栅绝缘层209上沉积氧化硅，以形成覆盖顶栅图案层210及顶栅绝缘层209的保护层208。
S28：开设贯穿保护层208及顶栅绝缘层209且连通源极图案层206或漏极图案层207的过孔2081。
具体地，通过光阻涂布、曝光、显影及剥离的光刻工艺在保护层208及顶栅绝缘层209中蚀刻出与源极图案层206或漏极图案层207连通的过孔2081。
共同参阅图7及图8，本发明提供的场效应晶体管的制备方法第三实施例包括：
S31：在基板301的上方形成隔离层302；
可选的，隔离层302为有机隔离层。
具体地，将基板301用丙酮、甲醇和异丙醇的溶液浸泡冲洗，并在一定温度烘干之后放入具有六甲基二硅胺蒸汽的环境中三分钟，以在基板301上形成有机隔离层，有机隔离层具有很好的防水隔氧效果。
可选的，隔离层302的材料为但不限于六甲基二硅胺或聚甲基丙烯酸甲酯的材料。
S32：通过含有黑磷纳米片或黑磷量子点的溶液在基板301的上方形成有源层303；
该步骤S32与上述第一实施例中的步骤S13相同，在此不再赘述。
S33：形成与有源层303接触的源极图案层304及漏极图案层305。
该步骤S33与上述第一实施例中的步骤S14相同，在此不再赘述。
S34：形成覆盖源极图案层304、漏极图案层305及有源层303的顶栅绝缘层306；
具体地，可通过物理气相沉积法或等离子体气相沉积法在隔离层302上沉积一定厚度的绝缘材料层以形成顶栅绝缘层306；
可选的，绝缘材料是包括但不限于的氧化硅、氧化铝、氮化硅或离子凝胶的绝缘材料。
S35：在顶栅绝缘层306上形成顶栅图案层307；
可选的，可通过旋涂法或提拉法在顶栅绝缘层306上沉积导电材料膜，并在真空低温蒸发之后使用等离子蚀刻法以形成图案化的导电材料膜，进而形成顶栅图案层307；在其他实施例中，也可以使用物理气相沉积法或化学气相沉积法在顶栅绝缘层306上沉积导电材料膜，然后通过曝光、显影、刻蚀和剥离的光刻工艺形成顶栅图案层307。
可选的，导电材料是包括但不限于石墨烯、金属型碳纳米管的导电碳材料。
S36：形成覆盖顶栅绝缘层306及顶栅图案层307的保护层308。
可选的，通过化学气相沉积法在顶栅绝缘层306上沉积氧化硅，以形成覆盖顶栅图案层307的保护层308。
S37：开设贯穿保护层308及顶栅绝缘层306且连通源极图案层304或漏极图案层305的过孔3081。
具体地，通过光阻涂布、曝光、显影及剥离的光刻工艺在保护层308及顶栅绝缘层306中蚀刻出与源极图案层304或漏极图案层305连通的过孔3081。
参阅图2，本发明提供的场效应晶体管第一实施例包括依次形成于基板上101的底栅图案层102及底栅绝缘层103、形成于基板101上方的隔离层104、形成于基板101上方的有源层105、与有源层105接触的源极图案层106及漏极图案层107、覆盖源极图案层106、漏极图案层107及有源层105的保护层108。
其中，隔离层104形成于底栅绝缘层103上，有源层105形成于隔离层104上且包括黑磷纳米片或黑磷量子点。
本实施例中各层结构采用上述场效应晶体管的制备方法第一实施例中相对应的步骤制备而成，在此不再赘述。
参阅图6，本发明提供的场效应晶体管第二实施例进一步包括顶栅绝缘层209及顶栅图案层210，本实施例中其他结构与上述场效应晶体管第一实施例相同，在此不再赘述。
其中，顶栅绝缘层209覆盖源极图案层206、漏极图案层207及有源层205，顶栅图案层210形成于底栅绝缘层209上。
本实施例中各层结构采用上述场效应晶体管的制备方法第二实施例中相对应的步骤制备而成，在此不再赘述。
参阅图8，本发明提供的场效应晶体管第三实施例包括：在基板301上方的隔离层302及有源层303、与有源层303接触的源极图案层304及漏极图案层305、覆盖源极图案层304、漏极图案层305及有源层303的顶栅绝缘层306、形成于顶栅绝缘层306上的顶栅图案层307、覆盖顶栅绝缘层306及顶栅图案层的保护层308。
本实施例中各层结构采用上述场效应晶体管的制备方法第三实施例中相对应的步骤制备而成，在此不再赘述。
区别于现有技术，本发明通过含有黑磷纳米片或黑磷量子点的溶液在基板的上方形成有源层；形成与有源层接触的源极图案层和漏极图案层的方法，提供多种场效应晶体管结构且使用溶液法以黑磷纳米片或黑磷量子点为材料制备场效应晶体管中的有源层，制程简单降低生产成本，丰富了场效应晶体管的制备材料，减少了环境的污染及对金属元素的依赖性，同时采用石墨烯或碳纳米等碳材料制备源、漏极与顶栅图案层，可与黑磷有源层形成有效的欧姆接触，降低接触电阻。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种场效应晶体管的制备方法，其中，所述方法包括：
    通过含有黑磷纳米片或黑磷量子点的溶液在基板的上方形成有源层；
    形成与所述有源层接触的源极图案层和漏极图案层；
    其中，所述通过含有黑磷纳米片或黑磷量子点的溶液在基板的上方形成有源层包括：
    使用旋涂法在所述基板的上方将所述含有黑磷纳米片或黑磷量子点的溶液旋涂形成黑磷膜层；
    低温真空蒸发所述黑磷膜层以形成黑磷有源层；
    所述形成与所述有源层接触的源极图案层和漏极图案层包括：
    在基体上形成导电材料层并通过转印工艺将所述导电材料层转移至所述有源层上；
    通过等离子体光刻法对所述导电材料层图案化处理以形成所述源极图案层和所述漏极图案层。
  2. 根据权利要求1所述的方法，其中，所述导电材料为石墨烯或碳纳米的导电碳材料。
  3. 根据权利要求1所述的方法，其中，所述方法还包括：
    在所述基板上依次形成底栅图案层及覆盖所述底栅图案层的底栅绝缘层。
  4. 根据权利要求3所述的方法，其中，所述方法还包括：
    形成覆盖所述源极图案层、所述漏极图案层及所述有源层的顶栅绝缘层；
    在所述顶栅绝缘层上形成顶栅图案层。
  5. 根据权利要求1所述的方法，其中，所述方法还包括：
    在所述基板的上方形成隔离层，其中，所述有源层形成于所述隔离层上。
  6. 一种场效应晶体管的制备方法，其中，所述方法包括：
    通过含有黑磷纳米片或黑磷量子点的溶液在基板的上方形成有源层；
    形成与所述有源层接触的源极图案层和漏极图案层。
  7. 根据权利要求6所述的方法，其中，所述通过含有黑磷纳米片或黑磷量子点的溶液在基板的上方形成有源层包括：
    使用旋涂法在所述基板的上方将所述含有黑磷纳米片或黑磷量子点的溶液旋涂形成黑磷膜层；
    低温真空蒸发所述黑磷膜层以形成黑磷有源层。
  8. 根据权利要求6所述的方法，其中，所述形成与所述有源层接触的源极图案层和漏极图案层包括：
    在基体上形成导电材料层并通过转印工艺将所述导电材料层转移至所述有源层上；
    通过等离子体光刻法对所述导电材料层图案化处理以形成所述源极图案层和所述漏极图案层。
  9. 根据权利要求8所述的方法，其中，所述导电材料为石墨烯或碳纳米的导电碳材料。
  10. 根据权利要求6所述的方法，其中，所述方法还包括：
    在所述基板上依次形成底栅图案层及覆盖所述底栅图案层的底栅绝缘层。
  11. 根据权利要求10所述的方法，其中，所述方法还包括：
    形成覆盖所述源极图案层、所述漏极图案层及所述有源层的顶栅绝缘层；
    在所述顶栅绝缘层上形成顶栅图案层。
  12. 根据权利要求6所述的方法，其中，所述方法还包括：
    在所述基板的上方形成隔离层，其中，所述有源层形成于所述隔离层上。
  13. 一种场效应晶体管，其中，所述场效应晶体管包括：
    在基板的上方形成的有源层，所述有源层包括黑磷纳米片或黑磷量子点；
    与所述有源层接触的源极图案层和漏极图案层。
  14. 根据权利要求13所述的场效应晶体管，其中，所述场效应晶体管还包括底栅图案层及底栅绝缘层，所述底栅图案层形成于所述基板上，所述底栅绝缘层覆盖所述底栅图案层。
  15. 根据权利要求14所述的场效应晶体管，其中，所述场效应晶体管还包括顶栅图案层及顶栅绝缘层，所述顶栅绝缘层覆盖所述源极图案层、所述漏极图案层及所述有源层，所述顶栅图案层形成于所述顶栅绝缘层上。
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