CN109326651A - 双栅结构黑磷场效应管 - Google Patents

双栅结构黑磷场效应管 Download PDF

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CN109326651A
CN109326651A CN201810994244.4A CN201810994244A CN109326651A CN 109326651 A CN109326651 A CN 109326651A CN 201810994244 A CN201810994244 A CN 201810994244A CN 109326651 A CN109326651 A CN 109326651A
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black phosphorus
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沈志豪
赵剑飞
江斌
王伟
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Nanjing Post and Telecommunication University
Nanjing University of Posts and Telecommunications
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

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  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种双栅结构黑磷场效应管，包括导电沟道、源区、漏区、栅极氧化层、二氧化硅隔离层、硅材料衬底、源极、漏极和第一栅极，所述的导电沟道、源区和漏区为黑磷材料，栅极氧化层在所述导电沟道、源区和漏区上方，第一栅极设置在导电沟道上方栅极氧化层的外表面，在漏区上方栅极氧化层的外表面上设置第二栅极。本发明能够在降低闭态电流，消除短沟道效应的同时，维持较大的导通电流，在未来纳米电子应用领域有着广阔的前景。

Description

双栅结构黑磷场效应管
技术领域
本发明涉及一种黑磷场效应管，特别是一种双栅结构黑磷场效应管。
背景技术
近段时间，由于分层黑磷(BP)在电子，光学和热学设备中的潜在应用，它受到了业界广泛的关注。研究表明，黑磷场效应管已经显示出优良的电性能，其开关电流比高达105，并且具有1000cm2V-1S-1的高迁移率。即使存在电子空穴散射和外来杂质散射，从黑磷场效应管提取的载流子迁移率也高于过渡金属二硫族化合物(TMDCs)。但是传统结构的黑磷场效应管会出现明显的短沟道效应，且随着器件尺寸不断缩小，会出现更加严重的短沟道效应，导致了闭态电流的上升，从而影响器件性能。
现有技术中的单栅结构黑磷场效应管如图1所示，它利用了单栅结构降低了闭态电流，但这个方法同时也会降低场效应管的导通电流，对其性能产生了不利影响。
发明内容
发明目的：本发明要解决的技术问题是提供一种双栅结构黑磷场效应管，它在降低闭态电流，消除短沟道效应的同时，也能够克服现有单栅结构场效应管导通电流低的缺点，维持较大的导通电流。
技术方案：本发明所述的双栅结构黑磷场效应管，包括导电沟道、源区、漏区、栅极氧化层、二氧化硅隔离层、硅材料衬底、源极、漏极和第一栅极，所述的导电沟道、源区和漏区为黑磷材料，栅极氧化层在所述导电沟道、源区和漏区上方，第一栅极设置在导电沟道上方栅极氧化层的外表面，第二栅极设置在漏区上方栅极氧化层的外表面。
为了提高导通电流，导电沟道、源区、漏区为多层黑磷材料。随着黑磷材料层数增加，闭态电流也会增加，为了在追求大导通电流和小闭态电流之间取得了一个较好的平衡，导电沟道、源区、漏区为3层黑磷材料。
为了更好地抑制闭态电流，所述的第二栅极的长度等于漏区的长度。
为了获得更多的有效载流子浓度，增大导通电流，所述的源区和漏区采用分子或金属离子进行N型重掺杂。
有益效果：本发明能够显著改善器件的闭态电流、导通电流等电学性能，在未来纳米电子应用领域有着广阔的前景。
附图说明
图1是现有技术中的单栅结构黑磷场效应管纵向截面图；
图2是本发明的纵向截面图；
图3为基于非平衡格林函数(NEGF)的自洽迭代求解过程。
具体实施方式
如图2所示，本发明双栅结构黑磷场效应管包括导电沟道1、源区2、漏区3、栅极氧化层4、二氧化硅隔离层5、硅材料衬底6、源极7、漏极8、第一栅极9和第二栅极10，导电沟道1、源区2和漏区3均采用黑磷材料制作，作为优选方案，源区2和漏区3还可以进一步采用分子或金属离子进行N型重掺杂。在所述的导电沟道1、源区2和漏区3上方，采用原子沉积等方法生成一层栅极氧化层4，在所述的导电沟道1、源区2和漏区3下方，覆盖一层二氧化硅隔离层5，在二氧化硅隔离层5外表面再覆盖一层硅材料衬底6，在导电沟道1上方的栅极氧化层4外表面沉淀一层金属电极，作为场效应管的第一栅极9，在漏区3上方的栅极氧化层4外表面沉淀一层金属电极，作为第二栅极10。通过在漏极区域上方的第二栅极，此场效应管不仅可以在很大程度上地降低闭态电流，而且还可以维持其较大的导通电流。为了进一步提升器件性能，本发明还可以使用3层黑磷材料来制作场效应管的导电沟道1、源区2和漏区3，这样可以在追求大导通电流和小闭态电流之间取得了一个更好的平衡。为了最大程度的抑制闭态电流，还可以将第二栅极10的长度等于漏区3的长度。
为了验证本发明的技术效果，验证过程的计算是采用非平衡格林函数(NEGF)的方法，它的求解过程如图3所示。该方法在开放边界条件下，自洽求解三维泊松和薛定谔方程。具体过程是在栅极9和栅极10给定同一个栅极电压VG，利用NEGF方程计算出其电荷密度，再将电荷密度代入泊松方程求解出黑磷场效应管沟道中的静电势，然后又将求得的电势重新代入NEGF方程中进行计算，如此反复迭代直到得到自洽解为止。在选定了合适的基组和用于描述沟道的哈密顿量以及自能项后，对于给定的自洽电势，系统的迟滞格林函数有如下形式[DATTA S.Nanoscale device modeling:The Green’s function method[J].Superlattices Microstruct,2000,28(4):253–278.]：
G(E)＝[(E+i0+)I-H-U-∑S-∑D]-1 (1)
式中，E为源极2与漏极3的电势差，I是单位矩阵，U是解泊松方程得出的电势的对角矩阵，ΣS和ΣD分别为器件源极的自能项和漏极的自能项，可根据表面格林函数通过迭代求出。
在紧束缚近似下，描述黑磷场效应管沟道的哈密顿矩阵[HSL]可表示为三对角矩阵的形式[DATTA S.Nanoscale device modeling:The Green’s function method[J].Superlattices Microstruct,2000,28(4):253–278.]：
其中N为纳米带宽度中所含磷原子数目，NT是器件沟道内的原子总数等于传输方向上单位单元数的2N倍，αSL是带状宽度上每个独立单位组成的列，是一个是2N阶的对角矩；[βSL]是2N阶的对角矩阵用来描述两个列之间的耦合关系；[αu]是每个独立单元的哈密顿矩阵；[βu,w]描述了在宽度方向上每两个相邻单位单元之间的相互作用；[βu,L]描述了在运输方向上每两个相邻单位单元之间的相互作用；
另外，扶手型黑磷场效应管的能带结构在紧束缚近似下可以表示为[MICHETTI P,IANNACCONE G.Analytical model of one-dimensional carbon-based schottky-barrier transistors[J].IEEE Trans Electron Devices,2010,57(7):1616-1625.]：
其中，K是动量，αSL和βSL如前所述。我们使用格林函数来数值计算透射率和电子密度。然后，将电子密度放入泊松方程中以找出器件中的电势。电子密度和化学势在经过多次迭代后自洽地确定。当达到量子输运方程和泊松方程之间的自洽性时，通过使用如下的Landauer公式计算导电沟道1电流Ids：
其中q是电子电荷，h是普朗克常量，T(E)是电子通过沟道的透射系数[DATTAS.Nanoscale device modeling:The Green’s function method[J].SuperlatticesMicrostruct,2000,28(4):253–278.]：
T(E)＝Trace[ΓS(E)G(E)ΓD(E)G′(E)] (7)
其中ΓS(D)是每个接触利用自能矩阵进行数值计算的扩张数量。
在上述计算模型框架下，比较分析了本发明双栅结构黑磷场效应管的性能。结果表明，本发明与一般的单栅结构黑磷场效应管相比，不仅可以最大限度地减小截止电流，而且可以维持技术人员所希望的较大的导通电流，它在抑制短沟道效应达到一定数量级的方面是非常有效的。

Claims (5)

1.一种双栅结构黑磷场效应管，包括导电沟道(1)、源区(2)、漏区(3)、栅极氧化层(4)、二氧化硅隔离层(5)、硅材料衬底(6)、源极(7)、漏极(8)和第一栅极(9)；其特征在于：所述的导电沟道(1)、源区(2)和漏区(3)为黑磷材料，在漏区(3)上方栅极氧化层(4)的外表面上设置第二栅极(10)。
2.根据权利要求1所述的双栅结构黑磷场效应管，其特征在于：所述的导电沟道(1)、源区(2)和漏区(3)为多层黑磷材料。
3.根据权利要求2所述的双栅结构黑磷场效应管，其特征在于：所述的导电沟道(1)、源区(2)和漏区(3)为3层黑磷材料。
4.根据权利要求1所述的双栅结构黑磷场效应管，其特征在于：所述的第二栅极(10)的长度等于漏区(3)的长度。
5.根据权利要求1至4所述的双栅结构黑磷场效应管，其特征在于：所述的源区(2)和漏区(3)采用分子或金属离子进行N型重掺杂。
CN201810994244.4A 2018-08-29 2018-08-29 双栅结构黑磷场效应管 Pending CN109326651A (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070194366A1 (en) * 2006-02-22 2007-08-23 Macronix International Co., Ltd. Single poly non-volatile memory device with inversion diffusion regions and methods for operating the same
CN103066107A (zh) * 2013-01-14 2013-04-24 南京邮电大学 一种并联型石墨烯纳米条带结构
CN104681631A (zh) * 2015-03-24 2015-06-03 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板及显示装置
KR101668629B1 (ko) * 2015-07-16 2016-10-24 포항공과대학교 산학협력단 2차원 구조의 질화물 반도체를 이용한 심자외선 발광 소자 및 그 제조 방법
CN107342228A (zh) * 2017-07-04 2017-11-10 深圳市华星光电半导体显示技术有限公司 一种场效应晶体管及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070194366A1 (en) * 2006-02-22 2007-08-23 Macronix International Co., Ltd. Single poly non-volatile memory device with inversion diffusion regions and methods for operating the same
CN103066107A (zh) * 2013-01-14 2013-04-24 南京邮电大学 一种并联型石墨烯纳米条带结构
CN104681631A (zh) * 2015-03-24 2015-06-03 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板及显示装置
KR101668629B1 (ko) * 2015-07-16 2016-10-24 포항공과대학교 산학협력단 2차원 구조의 질화물 반도체를 이용한 심자외선 발광 소자 및 그 제조 방법
CN107342228A (zh) * 2017-07-04 2017-11-10 深圳市华星光电半导体显示技术有限公司 一种场效应晶体管及其制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
王伟等: "异质栅碳纳米管场效应管电学特性研究", 《微电子学》 *

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