WO2019095556A1 - 阵列基板、显示面板及阵列基板的制作方法 - Google Patents

阵列基板、显示面板及阵列基板的制作方法 Download PDF

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WO2019095556A1
WO2019095556A1 PCT/CN2018/074011 CN2018074011W WO2019095556A1 WO 2019095556 A1 WO2019095556 A1 WO 2019095556A1 CN 2018074011 W CN2018074011 W CN 2018074011W WO 2019095556 A1 WO2019095556 A1 WO 2019095556A1
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layer
active layer
array substrate
gate
substrate
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PCT/CN2018/074011
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English (en)
French (fr)
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谢华飞
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/002,220 priority Critical patent/US10600816B2/en
Publication of WO2019095556A1 publication Critical patent/WO2019095556A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

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  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a method for fabricating an array substrate.
  • the existing electronic device carbon-based thin film transistor research focuses on how to improve the density and uniformity of the semiconductor film, how to regulate the polarity of carriers in the channel, and how to improve the carrier mobility and other aspects, the active layer and The contact resistance of the source-drain metal electrode is rarely studied, and the contact resistance has an important influence on the performance of the regulating electronic device, such as the on-state current of the electronic device and the mobility of the carrier.
  • An object of the present invention is to provide an array substrate, a display panel, and a method for fabricating an array substrate, which are used for reducing contact resistance between an active layer and source and drain metal electrodes, and improving an on-state current of an electronic device and carriers. Mobility.
  • the present invention provides an array substrate comprising: a substrate, an active layer disposed on the substrate, a conductive layer, a source, and a drain, wherein the conductive layer is disposed on opposite sides of the active layer and Contacting the active layer, the conductive layer forming a gap on the active layer exposing a surface of the active layer portion, wherein the source and the drain are respectively disposed on opposite sides of the active layer On the conductive layer.
  • the material of the conductive layer is graphene.
  • the surface of the substrate is provided with a gate and a gate insulating layer covering the gate, and the active layer is disposed on the gate insulating layer.
  • the array substrate further includes an insulating protective layer, a gate disposed on the insulating protective layer, and a passivation protective layer covering the gate, the insulating protective layer covering the source, the drain, and the The gap on the active layer.
  • the array substrate further includes an insulating layer covering the source, the drain, and a gap on the active layer.
  • the present invention also provides a display panel comprising the above array substrate, a color filter substrate and a liquid crystal molecular layer sealed between the array substrate and the color filter substrate.
  • the invention also provides a method for preparing an array substrate, comprising:
  • a source and a drain are respectively formed on the conductive layers on opposite sides of the active layer.
  • the step of forming a conductive layer in contact with the active layer on opposite sides of the active layer comprises: depositing a bottom gate on the substrate, and depositing a bottom gate on the bottom gate The gate insulation of the pole.
  • the step of forming a source and a drain respectively on the conductive layers on opposite sides of the active layer further includes depositing insulation protection on the source, the drain, and the active layer.
  • a layer, a top gate is deposited on the insulating protective layer, and a passivation protective layer covering the top gate is deposited on the top gate.
  • a gap on the active layer is protected by a photoresist, the substrate is immersed in a conductive layer solution to deposit the conductive layer, and the deposited substrate is baked at 150 ° C for 30 minutes to remove excess A conductive layer solution is used to dry the substrate.
  • the present invention adds a layer of graphene conductive layer between the active layer and the source and the drain to form a good electrical conductivity between the source and the drain.
  • the contact resistance between the active layer and the source and the drain is effectively reduced, thereby effectively improving the on-state current of the electronic device and the mobility of carriers.
  • FIG. 1 is a schematic structural diagram of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural view of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 3 is a schematic structural diagram of an array substrate according to Embodiment 3 of the present invention.
  • FIG. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the invention.
  • an array substrate includes: a substrate 10 , an active layer 20 disposed on the substrate, a conductive layer 30 , a source 40 , and a drain 50 .
  • the conductive layer 30 is disposed on the substrate.
  • the opposite sides of the active layer 20 are in contact with the active layer 20, and the conductive layer 30 forms a gap on the active layer 20 exposing a portion of the surface of the active layer 20, the source 40 and the drain electrode 50 are respectively disposed on the conductive layer 30 on opposite sides of the active layer 20.
  • the material of the conductive layer 30 is graphene.
  • the beneficial effect is that a graphene conductive layer 30 is added between the active layer 20 and the source 40 and the drain 50 to connect the source 40 and the drain 50.
  • Good electrical conductivity is formed, and the contact resistance between the active layer 20 and the source 40 and the drain 50 is effectively reduced, thereby effectively increasing the on-state current of the electronic device and the mobility of carriers.
  • a surface of the substrate 10 is provided with a bottom gate 60 and a gate insulating layer 70 covering the bottom gate 60.
  • the gate insulating layer 70 is used to The insulating layer 20 is insulated from the active layer 20, and the active layer 20 is disposed on the gate insulating layer 70.
  • the array substrate further includes an insulating layer 80 covering the source 40, the drain 50, and a gap on the active layer.
  • the substrate 10 includes, but is not limited to, silicon wafer, quartz, glass, and flexible plastic;
  • the bottom gate 60 includes, but is not limited to, copper, molybdenum, aluminum, and indium tin oxide.
  • the gate insulating layer 70 and the insulating layer 80 include, but are not limited to, silicon dioxide, graphene oxide, and an organic insulating material; the active layer 20 includes, but is not limited to, a semiconductor carbon nanotube nano carbon-based material and doped graphene. Nano carbon-based materials.
  • the array substrate further includes an insulating protective layer 90, a top gate 100 disposed on the insulating protective layer 90, and a passivation covering the top gate 100.
  • the protective layer 110 covers the gap between the source 40, the drain 50, and the active layer 20.
  • the substrate 10 includes, but is not limited to, silicon wafer, quartz, glass, and flexible plastic; the top gate 100 includes, but is not limited to, copper, molybdenum, aluminum, and indium tin oxide.
  • the insulating protective layer 90 and the passivation protective layer 110 include, but are not limited to, silicon dioxide, graphene oxide, and an organic insulating material; the active layer 20 includes, but is not limited to, a semiconductor carbon nanotube nano carbon-based material and doped graphite. Alkene nanocarbon based material.
  • the surface of the substrate 10 is provided with a bottom gate 60 and a gate insulating layer 70 covering the bottom gate 60.
  • the gate insulating layer 70 is used for The bottom gate 60 is insulated from the active layer 20, and the active layer 20 is disposed on the gate insulating layer 70.
  • the array substrate further includes an insulating layer 80 and a top gate 100 disposed on the insulating layer 80.
  • the insulating layer 80 covers the source 40, the drain 50, and a gap on the active layer. .
  • the substrate 10 includes, but is not limited to, silicon wafer, quartz, glass, and flexible plastic; the bottom gate 60 and the top gate 100 include, but are not limited to, copper, molybdenum, aluminum, and indium tin oxide. Things.
  • the gate insulating layer 70 and the insulating layer 80 include, but are not limited to, silicon dioxide, graphene oxide, and an organic insulating material; the active layer 20 includes, but is not limited to, a semiconductor carbon nanotube nano carbon-based material and doped graphene. Nano carbon-based materials.
  • the present invention further provides a display panel comprising the above array substrate, a color filter substrate 120 and a liquid crystal molecular layer 130 sealed between the array substrate and the color filter substrate 120 .
  • the liquid crystal molecular layer 130 can control the brightness of the light emitted from the display screen by twisting.
  • the color film substrate 120 combined with the liquid crystal molecular layer 40 can adjust the brightness of the three primary colors to obtain a desired color display.
  • the present invention also provides a method for preparing an array substrate, comprising:
  • step 1 a substrate 10 is provided on which an active layer 20 is deposited.
  • the material of the active layer 20 is a carbon nanotube nano carbon-based material.
  • Step 2 forming a conductive layer 30 in contact with the active layer 20 on opposite sides of the active layer 20, wherein the conductive layer 30 is formed on the active layer 20 to expose the active layer 20 The gap between the surfaces.
  • the material of the conductive layer 30 is graphene.
  • Step 3 forming a source 40 and a drain 50 on the conductive layer 30 on opposite sides of the active layer 20, respectively.
  • the step of forming the conductive layer 30 in contact with the active layer 20 on opposite sides of the active layer 20 includes depositing a bottom gate 60 on the substrate 10, and depositing a cover on the bottom gate 60 The gate insulating layer 70 of the bottom gate 60.
  • the steps of forming the source 40 and the drain 50 on the conductive layer 30 on opposite sides of the active layer 20 further include the source 40, the drain 50, and the active source.
  • An insulating layer 80 is deposited over the gaps on the layer, and a top gate 100 is deposited over the insulating layer 80.
  • the steps of forming the source 40 and the drain 50 on the conductive layer 30 on opposite sides of the active layer 20 further include the source 40, the drain 50, and the active layer 20
  • the gap is deposited with an insulating protective layer 90, a top gate 100 is deposited on the insulating protective layer 90, and a passivation protective layer 110 covering the top gate 100 is deposited on the top gate 100.
  • the material of the passivation protective layer 110 is silicon dioxide.
  • the bottom gate 60 and the top gate 100 are prepared by vapor deposition of a metal film on the substrate 10 by magnetron sputtering or electron beam evaporation, through photoresist and chemistry.
  • the bottom gate 60 and the top gate 100 are patterned by exposure.
  • the preparation of the gate insulating layer 70 is referred to as depositing a gate insulating layer 70 on the bottom gate 60 by chemical vapor deposition.
  • the carbon nanotube active layer 20 is prepared by: immersing the substrate 10 covered with the gate insulating layer 70 with acetone, methanol, and isopropanol, and then drying it with nitrogen to cover the cover.
  • the substrate 10 having the gate insulating layer 70 is immersed in a carbon nanotube solution to deposit a carbon nanotube film.
  • the substrate 10 is taken out and baked at 150 ° C for 30 minutes to obtain a carbon nanotube network film. Excess carbon nanotubes are removed by oxygen plasma.
  • the graphene conductive layer 30 is prepared by using a photoresist to protect a gap on the active layer 20, and the substrate 10 is immersed in a graphene solution to deposit the graphene film.
  • the substrate 10 was baked at 150 ° C for 30 minutes to remove excess of the graphene solution, and the substrate 10 was dried.
  • the source electrode 40 and the drain electrode 50 are prepared by depositing a metal conductive film on the substrate 10 on which the graphene conductive layer 30 is deposited by magnetron sputtering or electron beam evaporation. Stripping technique removes the graphene and the metal film on the photoresist and the photoresist to obtain a complete carbon nanotube active layer gap, the graphene conductive layer 30, and the source 40 and the drain 50.
  • the silicon dioxide passivation protective layer 110 is prepared by covering the silicon dioxide as a blunt by chemical vapor deposition on the gap between the source 40, the drain 50 and the active layer. Protective layer 110.

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种阵列基板，包括：基板（10）、设于基板上的有源层（20）、导电层（30）、源极（40）、漏极（50），导电层设于有源层的相对两侧并且与有源层接触，导电层在有源层上形成露出有源层部分表面的间隙，源极及漏极分别设于有源层相对两侧的导电层上。导电层的材料为石墨烯。通过在有源层与源极以及与漏极之间增加一层石墨烯导电层，使源极与漏极之间形成良好的导电，有效降低有源层与源极以及漏极之间的接触电阻，进而有效提高电子器件的开态电流以及载流子的迁移率。

Description

阵列基板、显示面板及阵列基板的制作方法
本发明要求2017年11月17日递交的发明名称为“阵列基板、显示面板及阵列基板的制作方法”的申请号201711143747.2的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板、显示面板及阵列基板的制作方法。
背景技术
由于现有电子器件碳基薄膜晶体管研究集中在如何提高半导体薄膜的密度、均匀度，如何调控沟道中载流子的极性，以及如何提高载流子迁移率等性能方面，对有源层与源漏极金属电极的接触电阻研究很少，而接触电阻对调控电子器件的性能有重要影响，例如电子器件开态电流及载流子的迁移率。
发明内容
本发明的目的在于提供一种阵列基板、显示面板及阵列基板的制作方法，用于减小有源层与源、漏极金属电极的接触电阻，提高电子器件的开态电流以及载流子的迁移率。
本发明提供了一种阵列基板，包括:基板、设于所述基板上的有源层、导电层、源极、漏极，所述导电层设于所述有源层的相对两侧并且与所述有源层接触，所述导电层在所述有源层上形成露出所述有源层部分表面的间隙，所述源极及所述漏极分别设于所述有源层相对两侧的所述导电层上。
其中，所述导电层的材料为石墨烯。
其中，所述基板的表面设有栅极及覆盖所述栅极的栅极绝缘层，所述有源层设于所述栅极绝缘层上。
其中。所述阵列基板还包括绝缘保护层、设于所述绝缘保护层上的栅极及覆盖所述栅极的钝化保护层，所述绝缘保护层覆盖所述源级、所述漏极及所述 有源层上的间隙。
其中，所述阵列基板还包括绝缘层，所述绝缘层覆盖所述源极、所述漏极及所述有源层上的间隙。
本发明还提供了一种显示面板，所述显示面板包括上述的阵列基板，彩膜基板及密封于所述阵列基板与彩膜基板之间的液晶分子层。
本发明还提供了一种阵列基板的制备方法，包括：
提供一基板，在所述基板上沉积有源层；
在所述有源层的相对两侧形成与所述有源层接触的导电层，其中，所述导电层在有源层上形成露出所述有源层部分表面的间隙；
在所述有源层相对两侧的所述导电层上分别形成源极及漏极。
其中，在所述有源层的相对两侧形成与所述有源层接触的导电层的步骤包括：在所述基板上沉积底栅极，在所述底栅极上沉积覆盖所述底栅极的栅极绝缘层。
其中，在所述有源层相对两侧的所述导电层上分别形成源极及漏极的步骤还包括在所述源极、所述漏极及所述有源层上的间隙沉积绝缘保护层,在所述绝缘保护层上沉积顶栅极及在所述顶栅极上沉积覆盖所述顶栅极的钝化保护层。
其中，采用光刻胶保护所述有源层上的间隙，将所述基板浸入到导电层溶液中沉积所述导电层，沉积完成后的所述基板在150℃下烘烤30分钟去除多余的导电层溶液，将所述基板干燥。
综上所述，本发明在所述有源层与所述源极以及与所述漏极之间增加一层石墨烯导电层，使所述源极与所述漏极之间形成良好的导电，有效降低所述有源层与所述源极以及所述漏极之间的接触电阻，进而有效提高电子器件的开态电流以及载流子的迁移率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付 出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例一提供的一种阵列基板的结构示意图。
图2是本发明实施例二提供的一种阵列基板的结构示意图。
图3是本发明实施例三提供的一种阵列基板的结构示意图。
图4是本发明实施例提供的一种显示面板的结构示意图。
图5是本发明实施例的阵列基板制作方法流程示意图。
具体实施方式
请参阅图1，本发明提供了一种阵列基板，包括:基板10、设于所述基板上的有源层20、导电层30、源极40、漏极50，所述导电层30设于所述有源层20的相对两侧并且与所述有源层20接触，所述导电层30在所述有源层20上形成露出所述有源层20部分表面的间隙，所述源极40及所述漏极50分别设于所述有源层20相对两侧的所述导电层30上。所述导电层30的材料为石墨烯。其有益效果在于：在所述有源层20与所述源极40以及与所述漏极50之间增加一层石墨烯导电层30，使所述源极40与所述漏极50之间形成良好的导电，有效降低所述有源层20与所述源极40以及所述漏极50之间的接触电阻，进而有效提高电子器件的开态电流以及载流子的迁移率。
本发明的第一实施例中，所述基板10的表面设有底栅极60及覆盖所述底栅极60的栅极绝缘层70，所述栅极绝缘层70用于将所述栅极60与所述有源层20绝缘，所述有源层20设于所述栅极绝缘层70上。
所述阵列基板还包括绝缘层80，所述绝缘层80覆盖所述源极40、所述漏极50及所述有源层上的间隙。
在本实施例中，所述基板10包括但不限于硅片、石英、玻璃以及柔性塑料；所述底栅极60包括但不限于铜、钼、铝及铟锡氧化物。
所述栅极绝缘层70以及绝缘层80包括但不限于二氧化硅、氧化石墨烯以及有机绝缘材料；所述有源层20包括但不限于半导体碳纳米管纳米碳基材料以及掺杂石墨烯纳米碳基材料。
请参阅图2，本发明的第二实施例中，所述阵列基板还包括绝缘保护层90、设于所述绝缘保护层90上的顶栅极100及覆盖所述顶栅极100的钝化保护层 110，所述绝缘保护层90覆盖所述源极40、所述漏极50及所述有源层20上的间隙。
在本实施例中，所述基板10包括但不限于硅片、石英、玻璃以及柔性塑料；所述顶栅极100包括但不限于铜、钼、铝及铟锡氧化物。
所述绝缘保护层90以及钝化保护层110包括但不限于二氧化硅、氧化石墨烯以及有机绝缘材料；所述有源层20包括但不限于半导体碳纳米管纳米碳基材料以及掺杂石墨烯纳米碳基材料。
请参阅图3，本发明的第三实施例中，所述基板10的表面设有底栅极60及覆盖所述底栅极60的栅极绝缘层70，所述栅极绝缘层70用于将所述底栅极60与所述有源层20绝缘，所述有源层20设于所述栅极绝缘层70上。
所述阵列基板还包括绝缘层80及设于所述绝缘层80上的顶栅极100，所述绝缘层80覆盖所述源极40、所述漏极50及所述有源层上的间隙。
在本实施例中，所述基板10包括但不限于硅片、石英、玻璃以及柔性塑料；所述底栅极60及所述顶栅极100包括但不限于铜、钼、铝及铟锡氧化物。
所述栅极绝缘层70以及绝缘层80包括但不限于二氧化硅、氧化石墨烯以及有机绝缘材料；所述有源层20包括但不限于半导体碳纳米管纳米碳基材料以及掺杂石墨烯纳米碳基材料。
请参阅图4，本发明还提供了一种显示面板，所述显示面板包括上述的阵列基板，彩膜基板120及密封于所述阵列基板与彩膜基板120之间的液晶分子层130。
所述液晶分子层130通过扭转可以控制射出显示屏的光线亮度。所述彩膜基板120结合所述液晶分子层40可以调节三原色的光亮，得到需要的彩色显示。
请参阅图5，本发明还提供一种阵列基板的制备方法，包括：
步骤1，提供一基板10，在所述基板10上沉积有源层20。所述有源层20的材料为碳纳米管纳米碳基材料。
步骤2，在所述有源层20的相对两侧形成与所述有源层20接触的导电层30，其中，所述导电层30在有源层20上形成露出所述有源层20部分表面的间隙。所述导电层30的材料为石墨烯。
步骤3，在所述有源层20相对两侧的所述导电层30上分别形成源极40及漏极50。
在所述有源层20的相对两侧形成与所述有源层20接触的导电层30的步骤包括：在所述基板10上沉积底栅极60，在所述底栅极60上沉积覆盖所述底栅极60的栅极绝缘层70。
进一步地，在所述有源层20相对两侧的所述导电层30上分别形成源极40及漏极50的步骤还包括在所述源极40、所述漏极50及所述有源层上的间隙上沉积绝缘层80，及在所述绝缘层80上沉积顶栅极100。
在所述有源层20相对两侧的所述导电层30上分别形成源极40及漏极50的步骤还包括在所述源极40、所述漏极50及所述有源层20上的间隙沉积绝缘保护层90，在所述绝缘保护层90上沉积顶栅极100及在所述顶栅极100上沉积覆盖所述顶栅极100的钝化保护层110。所述钝化保护层110的材料为二氧化硅。
进一步地，所述底栅极60及所述顶栅极100的制备过程为：采用磁控溅射或电子束蒸发技术在所述基板10上蒸镀一层金属膜，通过光刻胶与化学曝光使所述底栅极60及所述顶栅极100图案化。所述栅极绝缘层70的制备过称为：通过化学气相沉积法在所述底栅极60上沉积一层栅极绝缘层70。
进一步地，所述碳纳米管有源层20的制备过程为：将覆盖有所述栅极绝缘层70的基板10用丙酮、甲醇和异丙醇浸泡冲洗后用氮气吹干，将所述覆盖有所述栅极绝缘层70的基板10浸入到碳纳米管溶液中沉积碳纳米管薄膜，沉积结束后，将所述基板10取出在150℃下烘烤30min，得到碳纳米管网络状薄膜，用氧气等离子体将多余的碳纳米管去除掉。
进一步地，所述石墨烯导电层30的制备方法为：采用光刻胶保护所述有源层20上的间隙，所述基板10浸入到石墨烯溶液中沉积所述石墨烯薄膜，沉积完成后的所述基板10在150℃下烘烤30分钟去除多余的所述石墨烯溶液，将所述基板10干燥。
进一步地，所述源极40及所述漏极50的制备过程为：将沉积有所述石墨烯导电层30的基板10用磁控溅射或电子束蒸发技术沉积一层金属导电膜，通过剥离技术将所述光刻胶及所述光刻胶上的所述石墨烯及金属膜去掉，得到完 整的所述碳纳米管有源层间隙、所述石墨烯导电层30、所述源极40及所述漏极50。
进一步地，所述二氧化硅钝化保护层110的制备方法为：在所述源极40、所述漏极50及所述有源层上的间隙用化学气相沉积法覆盖二氧化硅作为钝化保护层110。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (14)

  1. 一种阵列基板，其中，包括:基板、设于所述基板上的有源层、导电层、源极、漏极，所述导电层设于所述有源层的相对两侧并且与所述有源层接触，所述导电层在所述有源层上形成露出所述有源层部分表面的间隙，所述源极及所述漏极分别设于所述有源层相对两侧的所述导电层上。
  2. 如权利要求1所述的阵列基板，其中，所述导电层的材料为石墨烯。
  3. 如权利要求2所述的阵列基板，其中，所述基板的表面设有栅极及覆盖所述栅极的栅极绝缘层，所述有源层设于所述栅极绝缘层上。
  4. 如权利要求2所述的阵列基板，其中，所述阵列基板还包括绝缘保护层、设于所述绝缘保护层上的栅极及覆盖所述栅极的钝化保护层，所述绝缘保护层覆盖所述源级、所述漏极及所述有源层上的间隙。
  5. 如权利要求3所述的阵列基板，其中，所述阵列基板还包括绝缘层，所述绝缘层覆盖所述源极、所述漏极及所述有源层上的间隙。
  6. 一种显示面板，其特征在于，所述显示面板包括权利要求1所述的阵列基板，彩膜基板及密封于所述阵列基板与彩膜基板之间的液晶分子层。
  7. 如权利要求6所述的显示面板，其中，所述导电层的材料为石墨烯。
  8. 如权利要求7所述的显示面板，其中，所述基板的表面设有栅极及覆盖所述栅极的栅极绝缘层，所述有源层设于所述栅极绝缘层上。
  9. 如权利要求7所述的显示面板，其中，所述阵列基板还包括绝缘保护层、设于所述绝缘保护层上的栅极及覆盖所述栅极的钝化保护层，所述绝缘保护层覆盖所述源级、所述漏极及所述有源层上的间隙。
  10. 如权利要求8所述的显示面板，其中，所述阵列基板还包括绝缘层，所述绝缘层覆盖所述源极、所述漏极及所述有源层上的间隙。
  11. 一种阵列基板的制备方法，其中，包括：
    提供一基板，在所述基板上沉积有源层；
    在所述有源层的相对两侧形成与所述有源层接触的导电层，其中，所述导电层在有源层上形成露出所述有源层部分表面的间隙；
    在所述有源层相对两侧的所述导电层上分别形成源极及漏极。
  12. 如权利要求11所述的阵列基板的制备方法，其中，在所述有源层的相对两侧形成与所述有源层接触的导电层的步骤包括：在所述基板上沉积底栅极，在所述底栅极上沉积覆盖所述底栅极的栅极绝缘层。
  13. 如权利要求11所述的阵列基板的制备方法，其中，在所述有源层相对两侧的所述导电层上分别形成源极及漏极的步骤还包括在所述源极、所述漏极及所述有源层上的间隙沉积绝缘保护层,在所述绝缘保护层上沉积顶栅极及在所述顶栅极上沉积覆盖所述顶栅极的钝化保护层。
  14. 如权利要求11所述的阵列基板的制备方法，其中，采用光刻胶保护所述有源层上的间隙，将所述基板浸入到导电层溶液中沉积所述导电层，沉积完成后的所述基板在150℃下烘烤30分钟去除多余的导电层溶液，将所述基板干燥。
PCT/CN2018/074011 2017-11-17 2018-01-24 阵列基板、显示面板及阵列基板的制作方法 WO2019095556A1 (zh)

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