WO2019010737A1 - 薄膜晶体管的制作方法及薄膜晶体管 - Google Patents

薄膜晶体管的制作方法及薄膜晶体管 Download PDF

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WO2019010737A1
WO2019010737A1 PCT/CN2017/095744 CN2017095744W WO2019010737A1 WO 2019010737 A1 WO2019010737 A1 WO 2019010737A1 CN 2017095744 W CN2017095744 W CN 2017095744W WO 2019010737 A1 WO2019010737 A1 WO 2019010737A1
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layer
thin film
film transistor
drain
source
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PCT/CN2017/095744
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English (en)
French (fr)
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李松杉
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武汉华星光电技术有限公司
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Priority to US15/565,498 priority Critical patent/US10818704B2/en
Publication of WO2019010737A1 publication Critical patent/WO2019010737A1/zh

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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a method of fabricating a thin film transistor and a thin film transistor.
  • Oxide semiconductors have attracted wide attention due to their high electron mobility, low leakage current, and low preparation temperature.
  • the conventional top gate self-aligned structure after the source and drain electrodes are completed the passivation layer and the organic insulating film are required to be processed by using two molds, and the process is complicated and the manufacturing cost is high. Due to the uniformity of the passivation layer film formation and the uniformity of dry etching, the top film of the source drain electrode is easily eroded to expose aluminum, and in the yellow light process of the organic insulating film, the alkaline developing solution methyl group Ammonia hydroxide (TMAH) corrodes aluminum, causing poor contact between the indium tin oxide anode and the source and drain electrodes, which ultimately affects product characteristics.
  • TMAH methyl group Ammonia hydroxide
  • the present invention provides a method of fabricating a thin film transistor and a thin film transistor.
  • the present invention provides a method of fabricating a thin film transistor, comprising: sequentially forming a buffer layer, an active layer, a gate insulating layer, and a gate layer on a substrate and patterning the same;
  • An organic light-emitting device was fabricated through the obtained pores of the passivation layer.
  • the buffer layer, the active layer, the gate insulating layer, and the gate layer are patterned using a photolithography process.
  • a plasma conductor treatment is performed on a contact region between the source and the drain and the active layer.
  • the plasma is ionized nitrogen or argon or helium or ammonia.
  • the passivation layer is deposited using plasma enhanced chemical vapor deposition.
  • An organic light emitting material is evaporated on the indium tin oxide electrode to form an organic light emitting device.
  • the passivation layer material is a nano silicon oxide.
  • the source/drain electrodes are made of molybdenum or aluminum.
  • the dielectric layer material is a nano silicon oxide.
  • a thin film transistor fabricated by the above method for fabricating a thin film transistor comprising: a substrate on which a buffer layer, an active layer, a gate insulating layer and a gate layer are sequentially disposed;
  • a dielectric layer is further disposed on the buffer layer, the active layer and the gate layer, and the dielectric layer is provided with a source and a drain, and the source and the drain pass through the dielectric layer
  • the active layers are in contact;
  • a passivation layer is disposed on the dielectric layer, the source and the drain, and an organic photoresist layer is disposed on the passivation layer;
  • the organic photoresist layer is provided with an indium tin oxide electrode, and the indium tin oxide electrode is in contact with the source or the drain through a hole of the passivation layer;
  • An organic light emitting device is disposed within the pixel defining layer, and the organic light emitting device contacts the indium tin oxide electrode through the pixel defining layer.
  • the method for fabricating the thin film transistor provided by the present invention is self-aligned in the top gate After quasi-structure and completion of the source and drain electrodes, a passivation layer is deposited using a plasma-enhanced chemical phase, and no pattern is formed after deposition. Then, an organic photoresist layer is formed and patterned. After the organic photoresist layer is patterned and annealed, the passivation layer is dry etched using the organic photoresist layer as a mold, and the appropriate power is adjusted to obtain a passivation layer. .
  • the thin film transistor constructed by the method should also have a corresponding technical effect.
  • FIG. 1 is a flow chart of a method of fabricating a thin film transistor in one embodiment of the present application.
  • FIG. 2 is a schematic structural view of a thin film transistor in one embodiment of the present application.
  • a method of fabricating the thin film transistor is schematically illustrated, and the method includes:
  • Step S101 A buffer layer 2, an edge layer (IGZO) 3, a gate insulating layer 4, and a gate electrode 5 are sequentially formed on the glass substrate 1 and patterned.
  • Step S102 An inter layer dielectric 6 is formed on the buffer layer 2, the active layer 3, and the gate layer 5 and patterned.
  • Step S103 forming a source 12 and a drain 13 on the dielectric layer 6 so that the source 12 and the drain 13 are in contact with the active layer 3 through the dielectric layer 6 to the source 12 And the drain 13 is patterned;
  • Step S104 sequentially forming a passivation layer (PV) 7 and an organic photoresist layer (PLN) 8 on the dielectric layer 6, the source 12 and the drain 13, and patterning the organic photoresist layer 8; After the organic photoresist layer 8 is patterned, the organic photoresist layer 8 needs to be annealed;
  • PV passivation layer
  • PPN organic photoresist layer
  • Step S105 performing dry etch processing on the passivation layer 7 with the organic photoresist layer 8 as a mask to obtain an etch of the passivation layer 7, wherein the passivation layer 7 has holes and The source 12 or the drain 13 are connected;
  • Step S106 The fabrication of the organic light emitting device (OLED) 10 is completed by the obtained holes of the passivation layer 7.
  • the passivation layer 7 is deposited, and no pattern is formed after deposition. Then, the organic photoresist layer 8 is patterned and patterned. After the organic photoresist layer 8 is patterned and annealed, the passivation layer 7 is dry etched by using the organic photoresist layer 8 as a mold to adjust the appropriate power. Thereby, the pores of the passivation layer 7 are obtained. In this way, a mold can be omitted, the process is simple, the manufacturing cost is saved, and the developer does not directly contact the aluminum (AI) exposed by the source 12 or the drain 13 due to the etch of the passivation layer 7. The purpose of improving the characteristics of the product can be achieved.
  • AI aluminum
  • step S101 the buffer layer 2, the active layer 3, the gate insulating layer 4, and the gate layer 5 are patterned using a photolithography process.
  • step S103 the contact regions of the source 12 and the drain 13 and the active layer 3 are subjected to plasma conduction processing.
  • the plasma is ionized nitrogen or argon or helium or ammonia.
  • the passivation layer 7 is deposited using plasma enhanced chemical vapor deposition in step S104.
  • step S106 further includes:
  • Step S1061 forming an indium tin oxide electrode (ITO) 9 on the organic photoresist layer 8, and passing the indium tin oxide electrode 9 through the hole of the passivation layer 7 and the source 12 or drain The pole 13 is in contact with each other, and the indium tin oxide electrode 9 is patterned;
  • ITO indium tin oxide electrode
  • Step S1062 forming a pixel definition layer (PDL) 11 on the organic photoresist layer 8 and the indium tin oxide electrode 9 and patterning the processing;
  • PDL pixel definition layer
  • Step S1063 The organic light-emitting material is vapor-deposited on the indium tin oxide electrode 9 to complete the fabrication of the organic light-emitting device 10.
  • the passivation layer 7 material is nano silicon oxide (SiOx).
  • the source drain 12 electrode material is molybdenum or aluminum (Mo/Al/Mo).
  • the dielectric layer 6 material is nano silicon oxide (SiOx).
  • the thin film transistor includes:
  • a buffer layer 2 In the glass substrate 1, a buffer layer 2, an active layer 3, a gate insulating layer 4, and a gate layer 5 are sequentially formed on the glass substrate 1.
  • a dielectric layer 6 is also formed on the buffer layer 2, the active layer 3 and the gate layer 5.
  • the source layer 6 and the drain electrode 13 are formed on the dielectric layer 6, and the source electrode 12 and the drain electrode 13 pass through the dielectric layer.
  • the electrical layer 6 is in contact with the active layer 3.
  • a passivation layer 7 is formed on the dielectric layer 6, the source 12 and the drain 13, and an organic photoresist layer 8 is formed on the passivation layer.
  • An indium tin oxide electrode 9 is formed on the organic photoresist layer 8, and the indium tin oxide electrode 9 is in contact with the source 12 or the drain 13 through the hole of the passivation layer 7.
  • a pixel defining layer 11 is formed on the organic photoresist layer 8 and the indium tin oxide electrode 9.
  • An organic light emitting device 10 is disposed within the pixel defining layer 11, and the organic light emitting device 10 is in contact with the indium tin oxide electrode 9 through the pixel defining layer 11.

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  • Thin Film Transistor (AREA)
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Abstract

一种薄膜晶体管的制作方法及薄膜晶体管，该方法包括：在玻璃基板（1）上依次制作缓冲层（2）、有源层（3）、栅极绝缘层（4）和栅极层（5）并图形化处理；在缓冲层（2）、有源层（3）和栅极层（5）上制作介电层（6）并图形化处理；在介电层（6）上制作源极（12）和漏极（13），使源极（12）和漏极（13）与有源层（3）相接触，对源极（12）和漏极（13）图形化处理；在介电层（6）、源极（12）和漏极（13）上依次制作钝化层（7）和有机光阻层（8），并对有机光阻层（8）图形化处理；以有机光阻层（8）为模具对钝化层（7）干法刻蚀得到钝化层（7）的孔；通过钝化层（7）的孔制作有机发光器件。可以省掉一块模具，工艺简单，节省制造成本，而且显影液不会直接接触到由于钝化层过蚀刻造成的源漏极电极露出的铝，从而可以达到改善产品的特性的目的。

Description

薄膜晶体管的制作方法及薄膜晶体管
相关申请的交叉引用
本申请要求享有于2017年7月12日提交的名称为“薄膜晶体管的制作方法及薄膜晶体管”的中国专利申请CN201710565553.5的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示器技术领域，尤其涉及薄膜晶体管的制作方法及薄膜晶体管。
背景技术
氧化物半导体由于电子迁移率高，漏电流低，制备温度低等特点，引起了广泛的关注。传统的顶栅自对准结构在完成源漏极电极后，制作钝化层和有机绝缘膜需要使用两道模具加工完成，工艺复杂，制造成本高。由于钝化层成膜的均一性和干燥侵蚀的均一性，源漏极电极的顶膜容易被侵蚀掉露出铝，在有机绝缘膜的黄光工艺(photo)中，碱性的显影液甲基氢氧化氨(TMAH)会腐蚀铝，从而造成铟锡氧化物阳极和源漏极电极的表面接触不良，最终会影响产品特性。
发明内容
针对上述问题中存在的不足之处，本发明提供一种薄膜晶体管的制作方法及薄膜晶体管。
为实现上述目的，本发明提供一种薄膜晶体管的制作方法，该方法包括：在基板上依次制作缓冲层、有源层、栅极绝缘层和栅极层并图形化处理；
在所述缓冲层、有源层和栅极绝缘层上制作介电层并图形化处理；
在所述介电层上制作源极和漏极，使所述源极和漏极穿过所述介电层与所述有源层相接触，对所述源漏极电极进行图形化处理；
在所述介电层、源极和漏极上制作钝化层，在所述钝化层上制作有机光阻层，并对所述有机光阻层进行图形化处理；
以所述有机光阻层为模具对所述钝化层进行干法刻蚀处理从而得到所述钝 化层的孔；
通过得到的所述钝化层的孔制作有机发光器件。
上述的薄膜晶体管的制作方法，使用光刻工艺对所述缓冲层、有源层、栅极绝缘层和栅极层进行图形化处理。
上述的薄膜晶体管的制作方法，对所述源极及漏极与所述有源层的接触区域进行等离子体导体化处理。
上述的薄膜晶体管的制作方法，所述等离子体为电离的氮气或氩气或氦气或氨气。
上述的薄膜晶体管的制作方法，使用等离子体增强化学气相沉积法沉积所述钝化层。
上述的薄膜晶体管的制作方法，通过得到的所述钝化层的孔完成对有机发光器件的制作的具体步骤为：
在所述有机光阻层上制作铟锡氧化物电极，使所述铟锡氧化物电极穿过所述钝化层的孔与所述源极或漏极相接触，对所述铟锡氧化物电极图形化处理；
在所述有机光阻层和铟锡氧化物电极上制作像素定义层并图形化处理；
在所述铟锡氧化物电极上蒸镀有机发光材料以形成有机发光器件。
上述的薄膜晶体管的制作方法，所述钝化层材料为纳米硅氧化物。
上述的薄膜晶体管的制作方法，所述源漏极电极为钼或铝材质。
上述的薄膜晶体管的制作方法，所述介电层材料为纳米硅氧化物。
一种利用上述薄膜晶体管的制作方法制作的薄膜晶体管，包括：基板，在所述基板上依次设置有缓冲层、有源层、栅极绝缘层和栅极层；
在所述缓冲层、有源层和栅极层上还设置有介电层，所述介电层上设置有源极和漏极，所述源极和漏极穿过所述介电层与所述有源层相接触；
所述介电层、源极和漏极上设置有钝化层，在所述钝化层上设置有机光阻层；
所述有机光阻层上设置有铟锡氧化物电极，所述铟锡氧化物电极穿过所述钝化层的孔与所述源极或漏极相接触；
在所述有机光阻层和铟锡氧化物电极上设置有像素定义层；
在所述像素定义层内设置有有机发光器件，且所述有机发光器件穿过所述像素定义层与所述铟锡氧化物电极相接触。
在上述技术方案中，本发明提供的薄膜晶体管的制作方法，通过在顶栅自对 准结构、完成源漏极电极后，使用等离子增强化学相沉积钝化层，沉积完后先不制作图形。接着制作有机光阻层并图形化，在有机光阻层图形化并退火后，以有机光阻层为模具，对钝化层进行干法刻蚀，调节适当的功率从而得到钝化层的孔。这样既可以省掉一块模具，工艺简单，节省制造成本，而且显影液不会直接接触到由于钝化层过蚀刻造成的源漏极电极露出的铝，从而可以达到改善产品的特性的目的。
由于上述薄膜晶体管的制作方法具有上述技术效果，利用该方法构造的薄膜晶体管也应具有相应的技术效果。
上述技术特征可以各种适合的方式组合或由等效的技术特征来替代，只要能够达到本发明的目的。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1为本申请的一个实施例中薄膜晶体管的制作方法的流程图。
图2为本申请的一个实施例中薄膜晶体管的结构示意图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
结合附图和本发明具体实施方式的描述，能够更加清楚地了解本发明的细节。但是，在此描述的本发明的具体实施方式，仅用于解释本发明的目的，而不能以任何方式理解成是对本发明的限制。在本发明的教导下，技术人员可以构想基于本发明的任意可能的变形，这些都应被视为属于本发明的范围，下面将结合附图对本发明作进一步说明。
以下将结合附图对本发明的内容作出详细的说明，下文中的“上”“下”“左”“右”均为相对于图示方向，不应理解为对本发明的限制。
下面将结合附图对本发明作进一步说明。
如图1所示，示意性地显示了该薄膜晶体管的制作方法，该方法包括：
步骤S101：在玻璃基板(glass)1上依次制作缓冲层(Buffer)2、有缘层(IGZO)3、栅极绝缘层(Gate insulator)4和栅极层(Gate electrode)5并图形化处理。
步骤S102：在缓冲层2、有源层3和栅极层5上制作介电层(inter layer dielectric)6并图形化处理。
步骤S103：在介电层6上制作源极(Source)12和漏极(Drain)13，使源极12和漏极13穿过介电层6与有源层3相接触，对源极12和漏极13进行图形化处理；
步骤S104：在介电层6、源极12及漏极13上依次制作钝化层(PV)7和有机光阻层(PLN)8，并对有机光阻层8进行图形化处理，另外，对有机光阻层8图形化处理之后，还需对有机光阻层8进行退火(anneal)处理；
步骤S105：以有机光阻层8为模具(mask)对钝化层7进行干法刻蚀(dry etch)处理从而得到钝化层7的孔(etch)，其中，钝化层7的孔与所述源极12或漏极13相连；
步骤S106：通过得到的钝化层7的孔完成对有机发光器件(OLED)10的制作。
在顶栅自对准结构、完成源极12和漏极13后，沉积钝化层7，沉积完后先不制作图形。接着制作有机光阻层8并图形化，在有机光阻层8图形化并退火后，以有机光阻层8为模具，对钝化层7进行干法刻蚀，调节适当的功率(power)从而得到钝化层7的孔。这样既可以省掉一块模具，工艺简单，节省制造成本，而且显影液不会直接接触到由于钝化层7过蚀刻(etch)造成的源极12或漏极13露出的铝(AI)，从而可以达到改善产品的特性的目的。
在一个实施例中，在步骤S101中，使用光刻工艺对缓冲层2、有源层3、栅极绝缘层4和栅极层5进行图形化处理。
在一个实施例中，在步骤S103中，对所述源极12及漏极13与所述有源层3的接触区域进行等离子体导体化处理。
在一个实施例中，等离子体为电离的氮气或氩气或氦气或氨气。
在一个实施例中，在步骤S104中，使用等离子体增强化学气相沉积法沉积所述钝化层7。
在一个实施例中，步骤S106进一步包括：
步骤S1061：在所述有机光阻层8上制作铟锡氧化物电极(ITO)9，使所述铟锡氧化物电极9穿过所述钝化层7的孔与所述源极12或漏极13相接触，对所述铟锡氧化物电极9图形化处理；
步骤S1062：在所述有机光阻层8和铟锡氧化物电极9上制作像素定义层(PDL)11并图形化处理；
步骤S1063：在铟锡氧化物电极9上蒸镀有机发光材料，完成对有机发光器件10的制作。
在一个实施例中，钝化层7材料为纳米硅氧化物(SiOx)。
在一个实施例中，源漏极12电极材料为钼或铝(Mo/Al/Mo)。
在一个实施例中，介电层6材料为纳米硅氧化物(SiOx)。
在一个实施中，如图2所示，薄膜晶体管，包括：
玻璃基板1，在玻璃基板1上依次构造有缓冲层2、有源层3、栅极绝缘层4和栅极层5。
在缓冲层2、有源层3和栅极层5上还构造有介电层6，介电层6上构造有源极12和漏极13，源极12和漏极13穿过所述介电层6与有源层3相接触。
介电层6、源极12和漏极13上构造有钝化层7，钝化层上构造有有机光阻层8。
有机光阻层8上构造有铟锡氧化物电极9，铟锡氧化物电极9穿过钝化层7的孔与源极12或漏极13相接触。
在有机光阻层8和铟锡氧化物电极9上构造有像素定义层11。
在所述像素定义层11内设置有有机发光器件10，且所述有机发光器件10穿过所述像素定义层11与所述铟锡氧化物电极9相接触。
最后说明的是，以上实施例仅用于说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换。尤其是，只要不存在结构上的冲突，各实施例中的特征均可相互结合起来，所形成的组合式特征仍属于本发明的范围内。只要不脱离本发明技术方案的宗旨和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (17)

  1. 薄膜晶体管的制作方法，其中，所述制作方法包括：
    步骤S101：在基板上依次制作缓冲层、有源层、栅极绝缘层和栅极层并图形化处理；
    步骤S102：在所述缓冲层、有源层和栅极层上制作介电层并图形化处理；
    步骤S103：在所述介电层上制作源极和漏极，使所述源极和漏极穿过所述介电层与所述有源层相接触，对所述源极和漏极进行图形化处理；
    步骤S104：在所述介电层、源极和漏极上制作钝化层，在所述钝化层上制作有机光阻层，并对所述有机光阻层进行图形化处理；
    步骤S105：以所述有机光阻层为模具对所述钝化层进行干法刻蚀处理从而得到所述钝化层的孔；
    步骤S106：通过得到的所述钝化层的孔制作有机发光器件。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其中，在步骤S101中，使用光刻工艺对所述缓冲层、有源层、栅极绝缘层和栅极层进行图形化处理。
  3. 根据权利要求1所述的薄膜晶体管的制作方法，其中：在步骤S103中，对所述源极及漏极与所述有源层的接触区域进行等离子体导体化处理。
  4. 根据权利要求3所述的薄膜晶体管的制作方法，其中，所述等离子体为电离的氮气或氩气或氦气或氨气。
  5. 根据权利要求1所述的薄膜晶体管的制作方法，其中，在步骤S104中，使用等离子体增强化学气相沉积法沉积所述钝化层。
  6. 根据权利要求1所述的薄膜晶体管的制作方法，其中，步骤S106进一步包括：
    步骤S1061：在所述有机光阻层上制作铟锡氧化物电极，使所述铟锡氧化物电极穿过所述钝化层的孔与所述源极或漏极相接触，对所述铟锡氧化物电极图形化处理；
    步骤S1062：在所述有机光阻层和铟锡氧化物电极上制作像素定义层并图形化处理；
    步骤S1063：在所述铟锡氧化物电极上蒸镀有机发光材料以形成有机发光器件。
  7. 根据权利要求1所述的薄膜晶体管的制作方法，其中，所述钝化层材料为纳米硅氧化物。
  8. 根据权利要求1所述的薄膜晶体管的制作方法，其中，所述源极和漏极为钼或铝材质。
  9. 根据权利要求1所述的薄膜晶体管的制作方法，其中，所述介电层材料为纳米硅氧化物。
  10. 薄膜晶体管，其利用一种制作方法进行制作，其中，所述制作方法包括：
    步骤S101：在基板上依次制作缓冲层、有源层、栅极绝缘层和栅极层并图形化处理；
    步骤S102：在所述缓冲层、有源层和栅极层上制作介电层并图形化处理；
    步骤S103：在所述介电层上制作源极和漏极，使所述源极和漏极穿过所述介电层与所述有源层相接触，对所述源极和漏极进行图形化处理；
    步骤S104：在所述介电层、源极和漏极上制作钝化层，在所述钝化层上制作有机光阻层，并对所述有机光阻层进行图形化处理；
    步骤S105：以所述有机光阻层为模具对所述钝化层进行干法刻蚀处理从而得到所述钝化层的孔；
    步骤S106：通过得到的所述钝化层的孔制作有机发光器件；
    其中，所述薄膜晶体管包括：
    基板，在所述基板上依次设置有缓冲层、有源层、栅极绝缘层和栅极层；
    在所述缓冲层、有源层和栅极层上还设置有介电层，所述介电层上设置有源极和漏极，所述源极和漏极穿过所述介电层与所述有源层相接触；
    所述介电层、源极和漏极上设置有钝化层，所述钝化层上设置有有机光阻层；
    所述有机光阻层上设置有铟锡氧化物电极，所述铟锡氧化物电极穿过所述钝化层的孔与所述源极或漏极相接触；
    在所述有机光阻层和铟锡氧化物电极上设置有像素定义层；
    在所述像素定义层内设置有有机发光器件，且所述有机发光器件穿过所述像素定义层与所述铟锡氧化物电极相接触。
  11. 根据权利要求10所述的薄膜晶体管，其中，在步骤S101中，使用光刻工艺对所述缓冲层、有源层、栅极绝缘层和栅极层进行图形化处理。
  12. 根据权利要求10所述的薄膜晶体管，其中，在步骤S103中，对所述源极 及漏极与所述有源层的接触区域进行等离子体导体化处理。
  13. 根据权利要求12所述的薄膜晶体管，其中，所述等离子体为电离的氮气或氩气或氦气或氨气。
  14. 根据权利要求10所述的薄膜晶体管，其中，在步骤S104中，使用等离子体增强化学气相沉积法沉积所述钝化层。
  15. 根据权利要求10所述的薄膜晶体管，其中，步骤S106进一步包括：
    步骤S1061：在所述有机光阻层上制作铟锡氧化物电极，使所述铟锡氧化物电极穿过所述钝化层的孔与所述源极或漏极相接触，对所述铟锡氧化物电极图形化处理；
    步骤S1062：在所述有机光阻层和铟锡氧化物电极上制作像素定义层并图形化处理；
    步骤S1063：在所述铟锡氧化物电极上蒸镀有机发光材料以形成有机发光器件。
  16. 根据权利要求10所述的薄膜晶体管，其中，所述钝化层材料为纳米硅氧化物。
  17. 根据权利要求10所述的薄膜晶体管，其中，所述源极和漏极为钼或铝材质。
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