WO2017114323A1 - 封装结构、电子设备及封装方法 - Google Patents

封装结构、电子设备及封装方法 Download PDF

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Publication number
WO2017114323A1
WO2017114323A1 PCT/CN2016/111924 CN2016111924W WO2017114323A1 WO 2017114323 A1 WO2017114323 A1 WO 2017114323A1 CN 2016111924 W CN2016111924 W CN 2016111924W WO 2017114323 A1 WO2017114323 A1 WO 2017114323A1
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WIPO (PCT)
Prior art keywords
chip
pin array
fan
substrate
out unit
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PCT/CN2016/111924
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English (en)
French (fr)
Inventor
赵南
谢文旭
张晓东
符会利
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to KR1020187021806A priority Critical patent/KR102115874B1/ko
Priority to EP16881112.3A priority patent/EP3399547A4/en
Priority to BR112018013514-3A priority patent/BR112018013514A2/zh
Publication of WO2017114323A1 publication Critical patent/WO2017114323A1/zh
Priority to US16/023,181 priority patent/US20180308789A1/en

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Definitions

  • the present invention relates to the field of microelectronic packaging technologies, and in particular, to a package structure and a packaging method.
  • Silicon Interposer technology is a technical solution for interconnecting wafers and interconnecting wafers and substrates in 3D integrated circuits and 2.5D IC packaging technologies.
  • the 2.5D IC package in the prior art integrates at least two wafers into a fan-out unit by a fan-out type circular packaging technology, and the fan-out unit is interposed by silicon.
  • the layer is packaged on the substrate.
  • the interconnection between at least two wafers and the interconnection between the wafer and the substrate are achieved by a silicon interposer.
  • the silicon interposer technology scheme uses a semiconductor process to fabricate interconnection lines on the silicon wafer that have much smaller line widths and node pitch than the resin substrate.
  • the silicon interposer is routed through through silicon via (TSV) technology.
  • TSV silicon via
  • DRIE deep ion etching
  • PVD physical vapor deposition
  • the implementation scheme of the 2.5D IC package in the prior art has the disadvantages of high process difficulty and high production cost.
  • the size of the silicon interposer is larger than the sum of all the wafer sizes, and the large-sized silicon interposer leads to high consumables (ie, high cost), which makes the cost of the 2.5D IC package re-increased, and is also disadvantageous for miniaturization of the package structure.
  • the present invention provides a package structure having a small process, low cost, and miniaturization, and an electronic device having the package structure.
  • the present invention also provides a package method for manufacturing the package structure.
  • the present invention provides a package structure including a substrate, a fan-out unit, and a wiring layer, the fan-out unit including a first chip and a second chip, the first chip including a first pin array, The second chip includes a second pin array, the fan-out unit further includes a third pin array, wherein the first pin array, the second pin array, and the third pin array face
  • the first pin array includes a plurality of first pins
  • the second pin array includes a plurality of second pins
  • the third pin array includes a plurality of third pins
  • a wiring layer is connected across the first pin array and the second pin array for connecting each of the first pin arrays to the second pin Corresponding second pins in the array to achieve electrical connection between the first chip and the second chip
  • the substrate is provided with a pad electrically connected to the internal wiring layer of the substrate, Three pins are connected to the pads to achieve an electrical connection between the fan-out unit and the substrate.
  • the type of the first chip may be a memory chip, or a 3D stacked chip module, or a silicon wafer, or a flip chip package structure, or a passive component.
  • the second chip and the first chip may be of the same type or different types.
  • Each of the third pins in the third pin array is columnar or spherical, and the third pin is made of copper or tin or lead.
  • the first chip and the second chip are disposed adjacent to each other, the first pin array is disposed adjacent to the second pin array, and the third pin array is located at An area of the fan-out unit other than the first pin array and the second pin array.
  • the package structure of the present invention has the beneficial effect of bridging between the first pin array and the second pin array through a wiring layer for using the first pin in the first pin array Connecting to a corresponding second pin of the second pin array to achieve electrical connection between the first chip and the second chip without disposing an interposer having a via structure, and because
  • the manufacturing process of the wiring layer is simple (can be realized by an ordinary build-up process), and the cost is also low; and the direct connection between the fan-out unit and the substrate by the third pin array and the substrate does not need to be provided with a large area.
  • the interposer also eliminates the process of making through holes in the interposer (in the prior art, the through silicon via (TSV) technology on the silicon interposer is used to realize the electrical connection between the fan-out unit and the substrate. Wiring, resulting in high process difficulty and high cost). Therefore, the invention has the advantages of low process difficulty and low cost.
  • the electrical connection wiring structure between the fan-out unit and the substrate of the invention is also advantageous for the small package structure. Modeled design.
  • the package structure further includes an interposer disposed between the fan-out unit and the substrate, the wiring layer being formed on a surface of the interposer .
  • the wiring layer is disposed on the interposer, and the interposer is mounted to the fan-out unit, and the manufacturing process is easy to implement.
  • the interposer is made of silicon or glass or an organic substrate.
  • the interposer and the substrate are isolated from each other, and the isolated architecture increases the signal isolation of the traces on the wiring layer. Conducive to the transmission of high-density signals.
  • the interposer and the substrate may also form a laminated contact structure by providing an insulating layer, and the structure of the laminated contact may be as small as possible.
  • the wiring layer is formed on a surface of the first pin array and the second pin array facing the substrate.
  • This embodiment directly sets the wiring layer on the fan-out unit, so that the number of components of the package structure is simplified (no interposer is required), and the size can be made as small as possible.
  • the wiring layer includes a first circuit layer, a reference layer, and a second circuit layer which are sequentially stacked, and the reference layer is the first circuit layer and the The reference plane of the second circuit layer.
  • the setting of the reference plane is beneficial to improve signal quality and improve crosstalk between signals.
  • the surface of the first chip and the surface of the second chip form a heat dissipation surface of the fan-out unit, so the heat dissipation surface is located in the fan-out unit
  • the package structure of the embodiment has good heat dissipation performance, and can improve the service life and working stability of the package structure.
  • the package structure further includes a heat sink, the heat sink illuminates the fan-out unit on the substrate And the heat sink is in contact with the heat dissipation surface.
  • the design of the heat sink further enhances the heat dissipation performance, service life and operational stability of the package structure.
  • the package structure further includes a heat sink and a thermal conductive paste, the heat sink shielding the fan-out unit in the On the substrate, the thermal conductive adhesive is disposed between the heat dissipation surface and the heat sink.
  • the thermal conductive adhesive has a good fit between the heat sink and the fan-out unit and enhanced heat dissipation performance.
  • the present invention provides an electronic device, comprising the package structure according to any one of the first aspects.
  • the present invention provides a packaging method, including:
  • the fan-out unit comprising a first chip and a second chip, the first chip comprising a first pin array, the second chip comprising a second pin array, the fan-out unit further comprising a third pin array, the first pin array, the second pin array, and the third pin array are both disposed facing the substrate, and the first pin array includes a plurality of first leads a second pin array comprising a plurality of second pins, the third pin array comprising a plurality of third pins;
  • Forming a wiring layer the wiring layer being bridged between the first pin array and the second pin array for connecting each first pin in the first pin array to Determining a second pin in the second pin array to implement electrical connection between the first chip and the second chip;
  • the substrate Connecting the third pin array to a substrate, the substrate is provided with a pad electrically connected to the internal wiring layer of the substrate, and the third pin is connected to the pad to realize the fan
  • the outlet unit is mounted to and electrically connected to the substrate.
  • the packaging method of the present invention has the beneficial effect of bridging between the first pin array and the second pin array through a wiring layer for using the first pin in the first pin array Connecting to a corresponding second pin of the second pin array to achieve electrical connection between the first chip and the second chip without disposing an interposer having a via structure, and because
  • the manufacturing process of the wiring layer is simple (can be realized by an ordinary build-up process), and the cost is also low; and the direct connection between the fan-out unit and the substrate by the third pin array and the substrate does not need to be provided with a large area.
  • the interposer also eliminates the process of making through holes in the interposer (in the prior art, the through silicon via (TSV) technology on the silicon interposer is used to realize the electrical connection between the fan-out unit and the substrate. Wiring, resulting in high process difficulty and high cost). Therefore, the present invention has the advantages of low process difficulty and low cost. On the basis of this, the electrical connection wiring structure between the fan-out unit and the substrate of the present invention is also advantageous for the miniaturization design of the package structure.
  • TSV through silicon via
  • the type of the first chip may be a memory chip, or a 3D stacked chip module, or a silicon wafer, or a flip chip package structure, or a passive component.
  • the second chip and the first chip may be of the same type or different types.
  • Each of the third pins in the third pin array is columnar or spherical, and the third pin is made of copper or tin or lead.
  • the step of fabricating a fan-out unit The first chip and the second chip are molded by using a molding compound to form the fan-out unit, and a distance between the first chip and the second core is less than or equal to 50 um.
  • a chip and a side of the second chip are wrapped by the molding compound, a front surface of the first chip and the second chip forming an outer surface of the fan-out unit, the first pin array and the The second pin array is respectively disposed on a front surface of the first chip and a front surface of the second chip.
  • the density of the first pin array and the density of the second pin array are both smaller than the density of the third pin array, and the size of each third pin is larger than the size of each first pin, and each third lead The size of the foot is also larger than the size of each second pin, and the size of the first pin and the size of the second pin may be the same.
  • the step of fabricating the fan-out unit further includes: grinding the first chip of the fan-out unit and the first One side of the back side of the two chips is such that the back surfaces of the first chip and the second chip form an outer surface of the fan-out unit to form a heat dissipation surface of the fan-out unit.
  • the method further includes: fabricating a heat sink, mounting the heat sink on the substrate, so that the heat sink covers the The fan-out unit is in contact with the heat dissipation surface.
  • the method further includes: forming a heat sink, the heat sink is a metal or non-metal heat conductive material; applying a thermal conductive adhesive on the heat dissipating surface; The heat sink is mounted on the substrate such that the heat sink covers the fan-out unit and is in contact with the thermal conductive adhesive.
  • the method further includes providing an interposer, the wiring layer being a circuit layer formed on a surface of the interposer according to a build-up process; and the interposer Bonding to the fan-out unit, and causing the wiring layer to connect a first pin of the first pin array to a corresponding second pin of the second pin array.
  • the step of connecting the third pin array to the substrate further includes the step of adjusting the mounting height by adjusting the third pin array and the substrate The size of the connection structure is varied to vary the height difference between the fan-out unit and the substrate.
  • the step of connecting the third pin array to the substrate further includes the step of adjusting a mounting height by providing a groove on the substrate The groove is disposed opposite to the wiring layer, and a height difference between the fan-out unit and the substrate is changed by the manner in which the wiring layer cooperates with the groove.
  • FIG. 1 is a schematic view of a package structure provided by a first embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a package structure provided by a second embodiment of the present invention.
  • FIG 3 is a schematic view of a package structure provided by a third embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a package structure according to a fourth embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a first layer wiring of a wiring layer of a package structure according to an embodiment of the present invention, including a first pin array, a second pin array, a third pin array, and a pad on the substrate.
  • FIG. 6 is a schematic diagram of a third layer wiring of a wiring layer of a package structure according to an embodiment of the present invention, including a first pin array, a second pin array, a third pin array, and a pad on the substrate.
  • FIG. 7 is a schematic diagram of a fan-out unit of a package structure in an embodiment of the present invention.
  • the present invention relates to a package structure and an electronic device having the package structure.
  • the present invention also provides a package method for fabricating the package structure.
  • FIG. 1 is a schematic diagram of a package structure according to a first embodiment of the present invention.
  • the package structure includes a substrate 108, a fan-out unit 111, and a wiring layer 104, and the fan-out unit 111 includes a first chip 101 and a second chip 102.
  • FIG. 7 schematically shows the structure of the fan-out unit 111, in which hidden lines (lines invisible in the view direction) are indicated by broken lines.
  • the first chip 101 includes a first pin array A1, wherein the first pin array A1 includes a plurality of first pins 32a, and the second chip 102 includes a second pin array A2, wherein the second pin array A2 includes a plurality of second pins 32b.
  • the fan-out unit 111 further includes a third pin array A3, and the first pin array A1, the second pin array A2, and the third pin A3 array are disposed facing the substrate 108.
  • the surfaces of the first chip 101 and the second chip 102 facing the substrate 108 are defined as front faces, and the opposite surfaces are defined as back faces, and the first pin array A1, the second pin array A2, and the third pin array A3 are distributed.
  • the first chip 101 and the second chip 102 are disposed adjacent to each other, the first pin array A1 is disposed adjacent to the second pin array A2, and the third pin array A3 is distributed in the fan-out unit.
  • the adjacent arrangement of the first chip 101 and the second chip 102 indicates that the first chip 101 and the second chip 102 have no other chips to separate the two.
  • a third pin array A3 is distributed on both the first chip 101 and the second chip 102. In other embodiments, the third pin array A3 may also be distributed only on one of the first chip 101 and the second chip 102 (as shown in the embodiment of FIG. 3).
  • the first chip 101 includes a first pin array A1 and a third pin array A3
  • the second chip 102 includes a second pin array A2 and a third pin array A3.
  • the first pin array A1 of the first chip 101 is adjacent to the second pin array A2 of the second chip 102 and is located in a central region of the fan-out unit 111.
  • the third pin array A3 of the first chip 101 and the third pin array A3 of the second chip 102 are distributed in the edge region of the fan-out unit 111, and are located in the first pin array A1 and the second pin array A2, respectively. On both sides.
  • the first chip 101 includes a first pin array A1 and a third pin array A3, and the second chip 102 includes only the second pin array A2, that is, a figure
  • the third pin array A3 is distributed only on the first chip 101.
  • the type of the first chip 101 may be a memory chip, or a 3D stacked chip module, or a silicon wafer, or a flip chip package structure, or a passive component.
  • the second chip 102 and the first chip 101 may be of the same type or different types. In the embodiment shown in FIGS. 1 and 2, the first chip 101 and the second chip 102 are of the same type. In the embodiment shown in FIG. 3, the first chip 101 and the second chip 102 are of different types.
  • the first chip 101 is a silicon wafer
  • the second chip 102 is a 3D stacked chip module, but is not limited thereto. Combination.
  • the density of the first pin array A1 and the density of the second pin array A2 are both smaller than the density of the third pin array A3.
  • the first pin array A1 includes a plurality of first pins 32a distributed in an array
  • the second pin array A2 includes a plurality of second pins 32b distributed in an array
  • Array A3 includes a plurality of third pins 41 distributed in an array. The size of each of the third pins 41 is larger than the size of each of the first pins 32a, and the size of each of the third pins 41 is also larger than the size of each of the second pins 32b.
  • the size of the first pin 32a and the second pin 32b The dimensions can be the same.
  • the labels A1 and A2 in the four figures are indicated by arrows with arrows, indicating the specific positions of the first pin array A1 and the second pin array A2, which are located at the arrows.
  • the line shown represents a plane perpendicular to the plane of the paper.
  • the specific positions of the first pin array A1 and the second pin array A2 are located on the surface of the fan-out unit 111 corresponding to the solder ball 103 (the solder ball 103 may also be a copper pillar or a solder ball or a lead bump).
  • the solder ball 103 is used to connect the wiring layer 104 to the first pin array A1 and the second pin array A2; the specific position of the third pin array A3 is located on the copper pillar 107 (the copper pillar 107 may also be a copper pillar or The surface of the fan-out unit 111 corresponding to the structure such as a solder ball or a lead bump is used to connect the fan-out unit 111 to the substrate 108.
  • the distance between the first chip 101 and the second chip 102 needs to be designed to be as small as possible, usually between the first chip 101 and the second chip 102. The distance is less than or equal to 50um.
  • a wiring layer 104 is connected across the first pin array A1 and the second pin array A2 for connecting the first pin 32a in the first pin array A1 to the second A corresponding second pin 32b in the pin array A2 to achieve an electrical connection between the first chip 101 and the second chip 102.
  • the wiring layer 104 is connected to the first pin array A1 and the second pin array A2 by solder balls 103.
  • the third pin array A3 is connected to the substrate 108 to achieve an electrical connection between the fan-out unit 111 and the substrate 108.
  • the third pin array A3 is connected to the substrate 108 by a copper post 107.
  • a solder pad 42 shown in FIGS.
  • the third pin array A3 is electrically connected to the pad 42 on the surface of the substrate 108. Specifically, the third pin array A3 and the pad 42 are connected by the copper post 107.
  • the shape of the first pin 32a, the second pin 32b and the third pin 41 may be, but not limited to, a spherical shape, a disk shape or a columnar structure, and the material thereof may be Copper or tin or lead.
  • the shape and material of the first pin 32a and the second pin 32b may be the same as or different from the third pin 41.
  • the present invention is not limited.
  • the first pin 32a and the second pin 32b are The size is smaller than the size of the third pin 41.
  • the first pin 32a, the second pin 32b, and the third pin 41 are exemplified by a ball shape, and the diameters of the first pin 32a and the second pin 32b may be less than or equal to 1 um, and the third lead The diameter of the foot 41 can be less than or equal to 10 um.
  • the first pin 32a, the second pin 32b, and the third pin 41 may be flush with the surface of the fan-out unit 111, or may be designed as a convex structure or a concave structure.
  • the structure of the first pin 32a, the second pin 32b, and the third pin 41 is similar to the design of the surface pad of the board.
  • the fan-out unit 111 and the substrate 108 are also filled with a sealant, and the sealant is covered with solder balls 103 and copper.
  • the pillars 107 and the wiring layer 104 are used to reinforce the package structure.
  • the encapsulation process is completed by filling the encapsulation between the fan-out unit 111 and the substrate 108.
  • the wiring layer 104 may be first packaged to the fan-out unit 111, and the sealing layer is filled between the wiring layer 104 and the fan-out unit. 110.
  • the fan-out unit 111 is further encapsulated on the substrate 108 through the encapsulant 106.
  • the encapsulant 110 and the encapsulant 106 may be made of different materials.
  • the package between the fan-out unit 111 and the substrate 108 can also be completed in a one-pack process.
  • the wiring layer 104 may be disposed on a separate carrier, and the carrier may be mounted to the fan-out unit 111.
  • the wiring layer 104 may be directly formed on the fan-out unit 111 regardless of whether the carrier of the wiring layer 104 is a fan-out unit. 111 or a separate carrier, the fabrication process of the wiring layer 104 can be realized by a layer-adding process, similar to the manufacturing method of the circuit board surface layer in the prior art, without the need for a via process, and therefore, the wiring layer 104 is easy Production, low cost.
  • the package structure further includes an interposer 105 disposed between the fan-out unit 111 and the substrate 108.
  • the wiring layer 104 is formed on the surface of the interposer 105, and then intervenes.
  • the board 105 is mounted on the first pin array A1 and the second pin array A2 of the fan-out unit 111 by solder balls 103.
  • the material of the interposer 105 is silicon or glass or an organic substrate 108.
  • the interposer 105 and the substrate 108 are isolated from each other. In other embodiments, an insulating layer may be disposed between the interposer 105 and the substrate 108 to form a stacked contact structure.
  • the wiring layer 104 is formed on a surface of the first lead array A1 and the second lead array A2 facing the substrate 108. In this embodiment, no soldering is required.
  • the design of the ball 103 and the interposer 105 is formed on the surface of the interposer 105, and then intervenes.
  • the board 105 is mounted on the first pin array A1 and the second pin array A2 of the fan-out unit 111 by solder balls 103.
  • the surface of the first chip 101 and the surface of the second chip 102 form a heat dissipation surface of the fan-out unit 111, so the heat dissipation surface is located at the fan-out.
  • the surface of the unit 111 is away from the side of the substrate 108.
  • the formation of the heat dissipation surface facilitates heat dissipation of the package structure.
  • a surface of the fan-out unit 111 away from the substrate 108 may have a molding compound covering the first chip 101 and the second chip 102. That is, the first chip 101 and the second chip 102 need not be exposed, as shown in FIG. 1, thereby simplifying the process and reducing the processing cost.
  • the package structure further includes a heat sink 112 that masks the fan-out unit 111 on the substrate 108, and the heat sink 112 and the heat dissipation surface contact.
  • the package structure further includes a heat sink 112 and a thermal conductive adhesive.
  • the heat sink 112 shields the fan-out unit 111 on the substrate 108, and the thermal conductive adhesive is disposed on the heat dissipation layer. Between the surface and the heat sink 112, the thermal adhesive is disposed to facilitate the heat sink 112 and the fan-out unit The fit between the 111 units enhances the heat dissipation.
  • the heat sink 112 includes a cover body and a side wall.
  • the side wall and the cover body together form a receiving cavity.
  • One end of the side wall is connected to the cover body, and the other end is fixed to the substrate 108, and can be fixed by adhesive.
  • the mounting between the side wall and the substrate 108 can also be achieved by a fixing means such as welding, snapping or screwing.
  • the cover body has a flat shape, and the cover body is attached to the heat dissipation surface of the fan-out unit 111, or the cover body and the heat dissipation surface are connected by a thermal conductive adhesive, and the cover body is equivalent to the structure of the flat heat sink for conducting the heat of the fan-out unit 111. .
  • the cover body and the side wall may be a one-piece structure or a separate structure, and the cover body and the side wall may be fixed by soldering.
  • the heat sink 112 shields the fan-out unit 111 on the substrate 108, and has the function of electromagnetic shielding in addition to the function of heat dissipation.
  • the structure of the heat sink 112 also contributes to the structural stability of the package structure and reduces the possibility of warpage of the package structure.
  • the wiring layer 104 includes a first circuit layer, a reference layer, and a second circuit layer which are sequentially stacked, and the reference layer is a reference surface of the first circuit layer and the second circuit layer.
  • the reference layer facilitates improved signal quality and improved crosstalk between signals. Referring to FIG. 5 and FIG. 6, the first pin array A1 and the third pin array A3 on the first chip 101, the second pin array A2 on the second chip 102, and the substrate 108 are respectively shown.
  • the distribution of the pads 42 is based on which, in addition, FIG. 5 also shows the wiring structure of the first wiring layer 14 of the wiring layer 104, and FIG. 6 also shows the wiring structure of the third wiring layer 16 of the wiring layer 104.
  • the first chip 101 is provided with a first pin 32a distributed in an array and a third pin 41 distributed in an array.
  • the second chip 102 is provided with a second pin 32b distributed in an array, and a pad 42 is disposed on the substrate 108.
  • the first pin 32a and the second pin 32b are connected by a wiring layer 104, and the third pin 41 and the pad 42 on the substrate 108 are connected by a copper post 107.
  • the first pin array A1 on the first chip 101 includes a first group Z1 and a second group Z2, that is, the first pins 32a are divided into two groups.
  • the second pin array A2 on the second chip 102 includes a third group Z3 and a fourth group Z4, that is, the second pin 32b is divided into two groups, and the second group Z2 and the third group Z3 are passed through the same as shown in FIG.
  • the first circuit layer 14 of the wiring layer 104 is electrically connected, and the first group Z1 and the fourth group Z4 are electrically connected by the third wiring layer 16 of the wiring layer 104 shown in FIG.
  • the wiring layer 104 may also include a third circuit layer, a fourth circuit layer, etc., that is, the wiring layer 104 may include a plurality of circuit layers, and the specific design is based on the electrical connection between the first chip 101 and the second chip 102. The condition of the signal connection is determined.
  • the interposer 105 is a silicon substrate, and the minimum line width of the wiring layer 104 on the interposer 105 can be less than or equal to 0.4 um. In another embodiment, the interposer 105 is a fan-out substrate, and the minimum line width of the wiring layer 104 thereon can be less than or equal to 2 um.
  • the wiring layer 104 passes through a build-up process on the surface of the fan-out unit 111 or the surface of the interposer 105 (the build-up process is a process of forming a thin film on the surface of the wafer, and these films may be insulators, semiconductors Or the conductor) can be realized, and the through hole structure is not required, so the wiring layer 104 is simple in fabrication process and low in cost; and the direct connection between the third pin array A3 and the substrate 108 is such that the fan-out unit 111 and the substrate 108 are The connection between the two does not require a large-area interposer, and the process of making via holes on the interposer is eliminated (in the prior art, fan-out is realized by through silicon via (TSV) technology on the silicon interposer).
  • TSV through silicon via
  • the wiring of the electrical connection between the unit and the substrate causes a process difficulty and a high cost). Therefore, the present invention has the advantages of low process difficulty and low cost.
  • the electrical connection wiring structure between the fan-out unit 111 and the substrate 108 of the present invention is also advantageous for the miniaturization design of the package structure.
  • the present invention also provides a packaging method.
  • the packaging method includes the following steps:
  • a fan-out unit 111 is formed.
  • the fan-out unit 111 includes a first chip 101 and a second chip 102.
  • the first chip 101 includes a first pin array A1, and the second chip 102 includes a second pin array A2.
  • the fan-out unit 111 further includes a third pin array A3.
  • the first pin array A1, the second pin array A2, and the third pin A3 array are all disposed facing the substrate 108.
  • the first chip 101 and the second chip 102 are disposed adjacent to each other, the first pin array A1 is adjacent to the second pin array A2, and the third pin array A3 is distributed on the fan.
  • An area of the unit 111 other than the first pin array A1 and the second pin array A2.
  • the wiring layer 104 is connected between the first pin array A1 and the second pin array A2 for using the first pin in the first pin array A1
  • An electrical connection between the first chip 101 and the second chip 102 is achieved by connecting to a corresponding second pin of the second pin array A2.
  • the third pin array A3 is connected to the substrate 108 to mount and electrically connect the fan-out unit 111 to the substrate 108.
  • a solder pad 42 (shown in FIGS. 5 and 6) electrically connected to the internal wiring layer of the substrate 108 is disposed on the substrate 108. The position of the pad on the substrate 108 in FIG. 1 to FIG. 4 is located in the copper pillar 107.
  • the third pin array A3 is electrically connected to the pad 42 on the surface of the substrate 108. Specifically, the third pin array A3 and the pad 42 are connected by the copper post 107.
  • the step of fabricating the fan-out unit 111 includes: molding the first chip 101 and the second chip 102 by using a molding compound to form the fan-out unit.
  • the present invention is described by taking two chips as an example, and the fan-out unit 111 can integrate a plurality of chips. Taking the first chip 101 and the second chip 102 as a wafer as an example, the original wafer is first thinned as needed, and the specific thickness of the first chip 101 and the second chip 102 is determined according to product requirements and process requirements. The original wafer is then diced to form a plurality of individual wafers.
  • the fan-out unit 111 is formed by a method of reconstituting and molding plastic molding.
  • the distance between the first chip 101 and the second chip 102 is less than or equal to 50 um.
  • the sides of the first chip 101 and the second chip 102 are wrapped by the molding compound, and the thickness of the side surface wrapped by the molding compound can be flexibly designed, usually less than 5 mm.
  • the front surface of the first chip 101 and the second chip 102 form an outer surface of the fan-out unit 111, and the first pin array A1, the second pin array A2, and the third pin array A3 are disposed on The front side of the first chip 101 and the second chip 102.
  • the density of the first pin array A1 and the density of the second pin array A2 are both smaller than the density of the third pin array A3.
  • the first pin array A1 includes a plurality of first pins 32a distributed in an array
  • the second pin array A2 includes a plurality of second pins 32b distributed in an array
  • Array A3 includes a plurality of third pins 41 distributed in an array.
  • each of the third pins 41 is larger than the size of each of the first pins 32a, and the size of each of the third pins 41 is also larger than the size of each of the second pins 32b.
  • the size of the first pin 32a and the second pin 32b The dimensions can be the same.
  • the step of fabricating the wiring layer 104 is specifically: providing an interposer 105, which is a circuit layer formed on one surface of the interposer 105 according to a build-up process; 105 is attached to the fan-out unit 111, and the wiring layer 104 is electrically connected between the first pin array A1 and the second pin array A2.
  • solder balls 103 are formed on the surface of the wiring layer 104. The number and size of the solder balls 103 are identical to the number and size of the first and second pins, respectively, and the interposer 105 is attached to the fan-out unit 111.
  • the process is performed by hot air remelting or hot pressing bonding, and the wiring layer 104 is connected by the corresponding cooperation of the solder ball 103 and the first pin and the corresponding cooperation of the solder ball 103 and the second pin.
  • a connection between the first chip 101 and the second chip 102 is achieved between the first pin array A1 and the second pin array A2.
  • the wiring layer 104 is formed directly on the surface of the fan-out unit 111, and the interposer 105 and the solder balls 103 are not required.
  • the fabrication process of the wiring layer 104 can be made by a build-up process, which is difficult to manufacture and has the advantage of low cost.
  • the wiring layer 104 is fabricated by passivation, sputtering, electroplating, etc., and the wiring material can be selected from copper, and the minimum line width of the wiring can be less than or equal to 0.4 um.
  • the copper pillar 107 is first fixed at the position of the third pin, and then the copper pillar 107 is aligned to the corresponding pad on the substrate 108.
  • the fan-out unit 111 may be attached to the substrate 108 by a process of hot air remelting or thermocompression bonding.
  • the packaging method of the present invention further includes the step of adjusting the mounting height by changing the size of the connection structure between the third lead array A3 and the substrate 108 (i.e., the copper pillar 107 shown in FIGS. 1 to 4).
  • the height difference between the fan-out unit 111 and the substrate 108 is described. Specifically, the size of the copper pillar 107 on the third pin array A3 on the side of the fan-out unit 111 may be increased to change the height difference, or the height difference may be changed by increasing the height of the pad on the substrate 108. .
  • the step of adjusting the mounting height can be achieved by adjusting the structure between the wiring layer 104 and the substrate 108. Specifically, by providing a groove 1081 on the substrate 108, and the groove 1081 is disposed opposite to the wiring layer 104, the fan is changed by the wiring layer 104 and the groove 1081. The height difference between the output unit 111 and the substrate 108, and the arrangement of the recess 1081 on the substrate 108, so that the height difference between the fan-out unit 111 and the substrate 108 becomes small, which is advantageous for the miniaturization of the package structure. Moreover, the substrate 108 is isolated from the wiring layer 104, and the isolated structure increases the signal isolation of the traces on the wiring layer 104, facilitating the transmission of high-density signals.
  • the step of fabricating the fan-out unit 111 further includes: grinding one of the first chip 101 of the fan-out unit 111 and the back surface of the second chip 102. On the side, the back surfaces of the first chip 101 and the second chip 102 are formed to form an outer surface of the fan-out unit 111 to form a heat dissipation surface of the fan-out unit 111. The heat dissipation surface is exposed to facilitate heat dissipation of the package structure.
  • the packaging method further includes fabricating a heat sink 112 , and mounting the heat sink 112 on the substrate 108 such that the heat sink 112 covers the fan-out.
  • the unit 111 is in contact with the heat dissipating surface.
  • the heat sink 112 is a metal or non-metal heat conductive material.
  • a heat conductive adhesive may be disposed between the heat sink 112 and the heat dissipating surface, and the heat dissipating surface is coated on the heat dissipating surface, and the heat sink 112 is mounted on the substrate 108 such that the heat sink 112 covers the fan-out unit. 111 and in contact with the thermal conductive adhesive.
  • the substrate 108 of the present invention may be a multilayer substrate 108 having a trace layer therein.
  • a fan-out unit 111 is mounted on the front surface of the substrate 108, and a pad 42 corresponding to the third pin array A3 of the fan-out unit 111 is disposed on the front surface of the substrate 108 (see FIGS. 5 and 6), and is connected to the fan through the copper post 107.
  • Out unit Between 111 and substrate 108.
  • the back surface of the substrate 108 is used for connection with a circuit board in an electronic device. As shown in FIGS. 1 to 4, a solder ball 109 is disposed on the back surface of the substrate 108, and the package structure is connected to the circuit board of the electronic device through the solder ball 109.
  • the wiring between the first chip 101 and the second chip 102 is realized by the wiring layer 104, and the number of the wiring layers 104 on the substrate 108 can be reduced.
  • the wiring layer 104 is smaller than the substrate 108, and the wiring layer 104 has a small area and is simply realized.
  • the wiring between the chip 101 and the second chip 102 eliminates the need to make more wiring layers 104 on the substrate 108 over a large area, and therefore, the cost of the package structure can be reduced.

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Abstract

一种封装结构、封装方法和电子设备，封装结构包括基板（108）、扇出单元（111）及布线层（104），扇出单元包括第一芯片（101）和第二芯片（102）。第一芯片包括第一引脚阵列（A1），第二芯片包括第二引脚阵列（A2）。扇出单元还包括第三引脚阵列（A3），第一引脚阵列、第二引脚阵列及第三引脚阵列均面对基板设置。布线层跨接于第一引脚阵列和第二引脚阵列之间，用于将第一引脚阵列中的第一引脚（32a）连接至第二引脚阵列中的对应的第二引脚（32b）。基板上设有与基板内部布线层电连接的焊垫（42），第三引脚阵列连接至焊垫。该封装结构具有制造工艺难度小、成本低及小型化的优势。

Description

封装结构、电子设备及封装方法
本申请要求于2015年12月31日提交中国专利局、申请号为201511030490.0，发明名称为“封装结构、电子设备及封装方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及微电子封装技术领域，特别涉及封装结构及封装方法。
背景技术
随着集成电子技术的不断发展，对芯片性能要求也日渐提高，如功能增强、尺寸减小、耗能与成本降低等，从而催生了3DIC(三维集成电路)技术及2.5D IC封装技术。硅中介层(Silicon Interposer)技术是三维集成电路及2.5D IC封装技术中实现晶圆(Die)之间互连及晶圆与基板互联的一种技术解决方案。
以2.5D IC封装为例，现有技术中的2.5D IC封装是将至少两颗晶圆通过扇出型圆级封装技术集成为扇出单元(Fan out Unit)，将扇出单元通过硅中介层封装在基板上。至少两颗晶圆之间的互联及晶圆与基板之间的互联均通过硅中介层实现。硅中介层技术方案使用半导体工艺在硅片上制作线宽、节点间距都比树脂基板小得多的互连线路。从而不同功能的芯片(比如CPU(中央处理单元)、DRAM(动态随机存取存储器)等)可以连到同一块硅中介层上面，通过硅中介层完成大量运算和数据交流。硅中介层通过硅通孔(TSV,through silicon via)技术实现布线，然而，硅通孔制作工艺是深度离子刻蚀技术(DRIE)，而硅通孔填充工艺为先通过物理气相沉积技术(PVD)在硅通孔内表面生长一层籽晶层，然后用电镀法完成。
可见，现有技术中的2.5D IC封装的实现方案具有工艺难度大、生产成本高的缺点。而且硅中介层的尺寸大于所有晶圆尺寸之和，大尺寸的硅中介层导致其耗材高(即成本高)，使得2.5D IC封装的成本再度提高，也不利于封装结构的小型化。
发明内容
本发明提供一种工艺难度小、低成本及小型化的封装结构有具有所述封装结构的电子设备，本发明还提供制造所述封装结构的封装方法。
为了实现上述目的，本发明实施方式提供如下技术方案：
第一方面，本发明提供一种封装结构，包括基板、扇出单元及布线层，所述扇出单元包括第一芯片和第二芯片，所述第一芯片包括第一引脚阵列，所述第二芯片包括第二引脚阵列，所述扇出单元还包括第三引脚阵列，所述第一引脚阵列、所述第二引脚阵列及所述第三引脚阵列均面对所述基板设置，所述第一引脚阵列包括多个第一引脚，所述第二引脚阵列包括多个第二引脚，所述第三引脚阵列包括多个第三引脚；所述布线层跨接于所述第一引脚阵列和所述第二引脚阵列之间，用于将所述第一引脚阵列中的每个第一引脚连接至所述第二引脚阵列中对应的第二引脚，以实现所述第一芯片和所述第二芯片之间的电连接；所述基板上设有与所述基板内部布线层电连接的焊垫，所述第三引脚连接至所述焊垫，以实现所述扇出单元与所述基板之间的电连接。具体的实施方式中，所述第一芯片的类型可以为存储芯片、或3D叠层芯片模组、或者硅晶圆、或者覆晶封装结构、或者被动元件。第二芯片与第一芯片可以为相同的类型，也可以为不同的类型。所述第三引脚阵列中的各第三引脚呈柱状或球状，所述第三引脚的材质为铜或锡或铅。
优选的实施方式中，所述第一芯片和所述第二芯片相邻设置，所述第一引脚阵列与所述第二引脚阵列相邻设置，且所述第三引脚阵列位于所述扇出单元之除所述第一引脚阵列和所述第二引脚阵列之外的区域。
本发明之封装结构的有益效果在于：通过布线层跨接于所述第一引脚阵列和所述第二引脚阵列之间，用于将所述第一引脚阵列中的第一引脚连接至所述第二引脚阵列中的对应的第二引脚，以实现所述第一芯片和所述第二芯片之间的电连接，无需设置具有通孔结构的中介板，而且，因为布线层的制作工艺简单(通过普通的增层工艺即可实现)，成本也低；且通过第三引脚阵列与基板的直接连接，使得扇出单元与基板之间的连接无需设置大面积的中介板，也省去了在中介板是制作通孔的工艺(现有技术中就是通过硅中介层上的硅通孔(TSV,through silicon via)技术实现扇出单元与基板之间电连接的布线，造成工艺难度大，成本高)。因此本发明具有工艺难度小，成本低的优势，在此基础上，本发明之扇出单元与基板之间的电连接布线结构也有利于封装结构的小 型化的设计。
结合第一方面，在第一种可能的实施方式中，所述封装结构还包括设于所述扇出单元与所述基板之间的中介板，所述布线层形成在所述中介板的表面。在中介板上设置布线层，再将中介板安装至扇出单元，制作工艺易于实现。
结合第一方面之第一种可能的实施方式，在第二种可能的实施方式中，所述中介板的材质为硅或玻璃或有机基板。
结合第一方面之第一种可能的实施方式，在第三种可能的实施方式中，所述中介板与所述基板之间彼此隔离，隔离的架构增加布线层上的走线的信号隔离度，利于高密度信号的传输。其它实施方式中，中介板与基板也可以通过设置绝缘层形成层叠接触架构，层叠接触的架构可以将尺寸做的尽量小。
结合第一方面，在第四种可能的实施方式中，所述布线层形成于所述第一引脚阵列和所述第二引脚阵列的面对所述基板的表面。这种实施方式直接在扇出单元上设置布线层，使得封装结构的元件数量得到简化(无需中介板)，亦可以将尺寸做的尽量小。
结合第一方面，在第五种可能的实施方式中，所述布线层包括依次层叠设置的第一线路层、参考层及第二线路层，所述参考层为所述第一线路层和所述第二线路层的参考面。参考面的设置有利于提高信号质量和改善信号间的串扰。
结合第一方面，在第六种可能的实施方式中，所述第一芯片的表面和所述第二芯片的表面形成所述扇出单元的散热表面，所以散热表面位于所述扇出单元之远离所述基板的一侧的表面上，本实施方式之封装结构的散热性能好，可以提升封装结构的使用寿命和工作稳定性。
结合第一方面之第六种可能的实施方式，在第七种可能的实施方式中，所述封装结构还包括散热片，所述散热片将所述扇出单元遮罩在所述基板上，且所述散热片与所述散热表面接触。散热片的设计进一步地提升了封装结构的散热性能及使用寿命和工作稳定性。
结合第一方面之第六种可能的实施方式，在第八种可能的实施方式中，所述封装结构还包括散热片和导热胶，所述散热片将所述扇出单元遮罩在所述基板上，所述导热胶设于所述散热表面与所述散热片之间。导热胶使得散热片与扇出单元之间具有良好的贴合度，增强的散热性能。
第二方面，本发明提供一种电子设备，所述电子设备包括第一方面任意一种实施方式所述的封装结构。
第三方面，本发明提供一种封装方法，包括：
制作扇出单元，所述扇出单元包括第一芯片和第二芯片，所述第一芯片包括第一引脚阵列，所述第二芯片包括第二引脚阵列，所述扇出单元还包括第三引脚阵列，所述第一引脚阵列、所述第二引脚阵列及所述第三引脚阵列均面对所述基板设置，所述第一引脚阵列包括多个第一引脚，所述第二引脚阵列包括多个第二引脚，所述第三引脚阵列包括多个第三引脚；
制作布线层，所述布线层跨接于所述第一引脚阵列和所述第二引脚阵列之间，用于将所述第一引脚阵列中的每个第一引脚连接至所述第二引脚阵列中对应的第二引脚，实现所述第一芯片和所述第二芯片之间的电连接；及
将所述第三引脚阵列连接至基板，所述基板上设有与所述基板内部布线层电连接的焊垫，所述第三引脚连接至所述焊垫，以实现将所述扇出单元安装至且电连接于所述基板。
本发明之封装方法的有益效果在于：通过布线层跨接于所述第一引脚阵列和所述第二引脚阵列之间，用于将所述第一引脚阵列中的第一引脚连接至所述第二引脚阵列中的对应的第二引脚，以实现所述第一芯片和所述第二芯片之间的电连接，无需设置具有通孔结构的中介板，而且，因为布线层的制作工艺简单(通过普通的增层工艺即可实现)，成本也低；且通过第三引脚阵列与基板的直接连接，使得扇出单元与基板之间的连接无需设置大面积的中介板，也省去了在中介板是制作通孔的工艺(现有技术中就是通过硅中介层上的硅通孔(TSV,through silicon via)技术实现扇出单元与基板之间电连接的布线，造成工艺难度大，成本高)。因此本发明具有工艺难度小，成本低的优势，在此基础上，本发明之扇出单元与基板之间的电连接布线结构也有利于封装结构的小型化的设计。
具体的实施方式中，所述第一芯片的类型可以为存储芯片、或3D叠层芯片模组、或者硅晶圆、或者覆晶封装结构、或者被动元件。第二芯片与第一芯片可以为相同的类型，也可以为不同的类型。所述第三引脚阵列中的各第三引脚呈柱状或球状，所述第三引脚的材质为铜或锡或铅。
结合第三方面，在第一种可能的实施方式中，所述制作扇出单元的步骤包 括：采用模塑料对所述第一芯片和所述第二芯片进行模封形成所述扇出单元，所述第一芯片与所述第二芯处之间的距离小于等于50um，所述第一芯片和所述第二芯片的侧面被所述模塑料包裹，所述第一芯片和所述第二芯片的正面形成所述扇出单元的外表面，所述第一引脚阵列和所述第二引脚阵列分别设于所述第一芯片的正面和所述第二芯片的正面。
进一步而言，第一引脚阵列的密度和第二引脚阵列的密度均小于第三引脚阵列的密度，且各第三引脚的尺寸大于各第一引脚的尺寸，各第三引脚的尺寸亦大于各第二引脚的尺寸，第一引脚的尺寸与第二引脚的尺寸可以相同。
结合第三方面之第一种可能的实施方式，在第二种可能的实施方式中，所述制作扇出单元的步骤还包括：研磨所述扇出单元之所述第一芯片和所述第二芯片的背面的一侧，使得所述第一芯片和所述第二芯片的背面形成所述扇出单元的外表面，以形成所述扇出单元的散热表面。
结合第三方面之第二种可能的实施方式，在第三种可能的实施方式中，还包括制作散热片，将所述散热片安装至所述基板上，使得所述散热片遮罩所述扇出单元且与所述散热表面接触。
结合第三方面之第二种可能的实施方式，在第四种可能的实施方式中，还包括制作散热片，散热片为金属或非金属导热材质；在所述散热表面涂覆导热胶；将所述散热片安装至所述基板上，使得所述散热片遮罩所述扇出单元且与所述导热胶接触。
结合第三方面，在第五种可能的实施方式中，还包括提供中介板，所述布线层为在所述中介板的一个表面上依增层工艺制作的电路层；及将所述中介板贴合至所述扇出单元，且使得所述布线层将所述第一引脚阵列中的第一引脚连接至所述第二引脚阵列中的对应的第二引脚。
结合第三方面，在第六种可能的实施方式中，将所述第三引脚阵列连接至基板的过程中，还包括调节安装高度的步骤，通过调节所述第三引脚阵列与基板之间的连接结构的尺寸来改变所述扇出单元与所述基板之间的高度差。
结合第三方面，在第七种可能的实施方式中，将所述第三引脚阵列连接至基板的过程中，还包括调节安装高度的步骤，通过在所述基板上设置凹槽，且所述凹槽与所述布线层相对设置，通过所述布线层与所述凹槽配合的方式来改变所述扇出单元与所述基板之间的高度差。
附图说明
为了更清楚地说明本发明的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以如这些附图获得其他的附图。
图1是本发明第一种实施方式提供的封装结构的示意图。
图2是本发明第二种实施方式提供的封装结构的示意图。
图3是本发明第三种实施方式提供的封装结构的示意图。
图4是本发明第四种实施方式提供的封装结构的示意图。
图5是本发明一种实施方式中的封装结构之布线层之第一层布线示意图，其中包括第一引脚阵列、第二引脚阵列、第三引脚阵列及基板上的焊垫。
图6是本发明一种实施方式中的封装结构之布线层之第三层布线示意图，其中包括第一引脚阵列、第二引脚阵列、第三引脚阵列及基板上的焊垫。
图7是本发明一种实施方式中的封装结构的扇出单元的示意图。
具体实施方式
本发明涉及一种封装结构和具有所述封装结构的电子设备，本发明还提供一制作所述封装结构的封装方法。下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
图1所示为本发明第一种实施方式提供的封装结构的示意图。封装结构包括基板108、扇出单元111及布线层104，所述扇出单元111包括第一芯片101和第二芯片102。请结合参阅图7，图7示意性地表达了扇出单元111的结构，其中隐藏的线(视图方向看不到的线)用虚线表示。所述第一芯片101包括第一引脚阵列A1，其中第一引脚阵列A1包括多个第一引脚32a，所述第二芯片102包括第二引脚阵列A2，其中第二引脚阵列A2包括多个第二引脚32b。所述扇出单元111还包括第三引脚阵列A3，所述第一引脚阵列A1、所述第二引脚阵列A2及所述第三引脚A3阵列均面对所述基板108设置。第一芯片101和第二芯片102的面对基板108的表面被定义为正面，相反的表面被定义为背面，第一引脚阵列A1、第二引脚阵列A2和第三引脚阵列A3分布于第一芯片 101和第二芯片102的正面。本实施方式中，第一芯片101和第二芯片102相邻设置，第一引脚阵列A1与第二引脚阵列A2相邻设置，所述第三引脚阵列A3分布于所述扇出单元111之除所述第一引脚阵列A1和所述第二引脚阵列A2之外的区域。第一芯片101和第二芯片102相邻设置表明第一芯片101和第二芯片102没有其他芯片将二者区隔开。
在图1所示的实施方式中，第一芯片101和第二芯片102上均分布有第三引脚阵列A3。其它的实施方式中，第三引脚阵列A3也可以只分布在第一芯片101和第二芯片102之一者上(如图3所示的实施例)。换言之，请参照图1，第一芯片101包括第一引脚阵列A1和第三引脚阵列A3，第二芯片102包括第二引脚阵列A2和第三引脚阵列A3。第一芯片101的第一引脚阵列A1与所述第二芯片102的第二引脚阵列A2相邻并位于扇出单元111的中心区域。第一芯片101的第三引脚阵列A3和第二芯片102的第三引脚阵列A3分布在扇出单元111的边缘区域，且分别位于第一引脚阵列A1和第二引脚阵列A2的两侧。另一种实施方式中，如图3所示，第一芯片101包括第一引脚阵列A1和第三引脚阵列A3，第二芯片102只包括第二引脚阵列A2，也就是说，图3所示的实施方式中，第三引脚阵列A3只分布在第一芯片101上。
所述第一芯片101的类型可以为存储芯片、或3D叠层芯片模组、或者硅晶圆、或者覆晶封装结构、或者被动元件。第二芯片102与第一芯片101可以为相同的类型，也可以为不同的类型。图1和图2所示的实施例中，第一芯片101和第二芯片102为相同的类型。图3所示的实施例中，第一芯片101和第二芯片102为不同的类型，例如，第一芯片101为硅晶圆，第二芯片102为3D叠层芯片模组，但不限于此种组合。
一种实施方式中，第一引脚阵列A1的密度和第二引脚阵列A2的密度均小于第三引脚阵列A3的密度。请参阅图5和图6，第一引脚阵列A1包括多个呈阵列分布的第一引脚32a，第二引脚阵列A2包括多个呈阵列分布的第二引脚32b，第三引脚阵列A3包括多个呈阵列分布的第三引脚41。各第三引脚41的尺寸大于各第一引脚32a的尺寸，各第三引脚41的尺寸亦大于各第二引脚32b的尺寸，第一引脚32a的尺寸与第二引脚32b的尺寸可以相同。
请参阅图1至图4，这四幅图中的标号A1和A2用带箭头的引线标示，表示的是第一引脚阵列A1和第二引脚阵列A2的具体设置的位置，位于箭头 所示的线所代表的垂直于纸面方面的平面上。第一引脚阵列A1和第二引脚阵列A2的具体的位置位于焊球103(焊球103也可以为铜柱或锡球或铅凸块等结构)所对应的扇出单元111的表面，焊球103用于将布线层104连接于第一引脚阵列A1和第二引脚阵列A2；第三引脚阵列A3的具体的位置位于铜柱107(铜柱107亦也可以为铜柱或锡球或铅凸块等结构)所对应的扇出单元111的表面，铜柱107用于将扇出单元111连接于基板108。为了保证第一芯片101和第二芯片102之间的高密度互连，第一芯片101与第二芯片102之间的距离需要设计得尽量小，通常第一芯片101和第二芯片102之间的距离小于等于50um。
布线层104跨接于所述第一引脚阵列A1和所述第二引脚阵列A2之间，用于将所述第一引脚阵列A1中的第一引脚32a连接至所述第二引脚阵列A2中的对应的第二引脚32b，以实现所述第一芯片101和所述第二芯片102之间的电连接。一种实施方式中，布线层104通过焊球103连接至所述第一引脚阵列A1和所述第二引脚阵列A2。所述第三引脚阵列A3连接至所述基板108，以实现所述扇出单元111与所述基板108之间的电连接。一种实施方式中，第三引脚阵列A3通过铜柱107连接至基板108。基板108上设有与所述基板108的内部布线层电连接的焊垫42(如图5和图6所示)，图1至图4中基板108上焊垫的位置位于铜柱107所对应的基板108的表面，第三引脚阵列A3与焊垫42电连接，具体而言，第三引脚阵列A3与焊垫42通过铜柱107连接。
请结合参阅图5、图6和图7，第一引脚32a、第二引脚32b和第三引脚41的形状可以为但不限于球状、圆盘状或柱状结构，它们的材质可以为铜或锡或铅。第一引脚32a和第二引脚32b的形状及材质可以与第三引脚41相同或不同，本发明不做限定，优选的实施方式中，第一引脚32a和第二引脚32b的尺寸小于第三引脚41的尺寸。一种实施方式中，第一引脚32a、第二引脚32b和第三引脚41以球状为例，第一引脚32a和第二引脚32b的直径可以达到小于等于1um，第三引脚41的直径可达小于等于10um。第一引脚32a、第二引脚32b和第三引脚41可以与扇出单元111的表面齐平，也可以设计成外凸的结构或内凹结构。第一引脚32a、第二引脚32b和第三引脚41的结构类似于电路板表面焊盘的设计。
扇出单元111和基板108之间还填充有封胶体，封胶体包覆焊球103、铜 柱107及布线层104，以加固封装结构。一种实施方式中，扇出单元111和基板108之间通过两次填充封胶完成封装工艺，可以先将布线层104封装至扇出单元111，布线层104和扇出单元之间填充封胶体110。再将扇出单元111通过封胶体106封装至基板108上，封胶体110和封胶体106可以为不同的材质。当然，扇出单元111和基板108之间的封装也可以在一次封装的制程中完成。
布线层104的可以设于独立的载板上，再将载板安装至扇出单元111，也可以将布线层104直接形成在扇出单元111上，无论布线层104的载体是否为扇出单元111或者为独立的载板，布线层104的制作工艺均可以通过增层工艺实现，类似现有技术中电路板表面线路层的制作方法，无需制作通孔工艺，因此，所述布线层104易于制作，成本低。具体实施方式描述如下。一种实施方式中，所述封装结构还包括设于所述扇出单元111与所述基板108之间的中介板105，所述布线层104形成在所述中介板105的表面，再将中介板105通过焊球103安装在扇出单元111的第一引脚阵列A1和第二引脚阵列A2上。所述中介板105的材质为硅或玻璃或有机基板108。所述中介板105与所述基板108之间彼此隔离。其它实施方式中，中介板105与基板108之间可以设置绝缘层形成层叠接触的架构。另一种实施方式中，所述布线层104形成于所述第一引脚阵列A1和所述第二引脚阵列A2的面对所述基板108的表面，这种实施方式中，无需要焊球103和中介板105的设计。
请参阅图2，图2所示的实施方式中，所述第一芯片101的表面和所述第二芯片102的表面形成所述扇出单元111的散热表面，所以散热表面位于所述扇出单元111之远离所述基板108的一侧的表面上。散热表面的形成有利于封装结构的散热。对于某些功耗较小或对散热要求不高的芯片，扇出单元111之远离所述基板108的一侧的表面上可以有模塑料覆盖所述第一芯片101和所述第二芯片102，即第一芯片101和所述第二芯片102不需要裸露出来，如图1所示，从而，简化工艺制成及降低加工成本。
请参阅图3和图4，所述封装结构还包括散热片112，所述散热片112将所述扇出单元111遮罩在所述基板108上，且所述散热片112与所述散热表面接触。另一种实施方式中，所述封装结构还包括散热片112和导热胶，所述散热片112将所述扇出单元111遮罩在所述基板108上，所述导热胶设于所述散热表面与所述散热片112之间，导热胶的设置有利于散热片112与扇出单元 111单元之间的贴合度，增强散热效果。具体而言，散热片112包括盖体和侧壁，侧壁和盖体共同形成收容腔，侧壁的一端连接至盖体，另一端用于固定至基板108，可以通过粘胶的方式固定，也可以通过焊接、卡扣或者螺丝连接等固定方式实现侧壁与基板108之间的安装。盖体呈平板状，盖体贴合于扇出单元111的散热表面，或者盖体与散热表面之间通过导热胶连接，盖体相当于平板散热器的结构，用于传导扇出单元111的热。盖体和侧壁可以为一体式结构，也可以为分离式结构，盖体和侧壁之间可以通过焊锡焊接固定。散热片112将扇出单元111遮罩在基板108上，除了散热的功能，还有电磁屏蔽之功效。散热片112的结构还有利于封装结构的结构稳定性，降低封装结构翘曲的可能性。
一种实施方式中，所述布线层104包括依次层叠设置的第一线路层、参考层及第二线路层，所述参考层为所述第一线路层和所述第二线路层的参考面，参考层有利于提高信号质量和改善信号间的串扰。请参阅图5和图6，分别示出了第一芯片101上的第一引脚阵列A1和第三引脚阵列A3、第二芯片102上的第二引脚阵列A2和基板108上的焊垫42分布情况，在此基础上，图5亦示出了布线层104之第一线路层14的布线架构，图6亦示出了布线层104之第三线路层16的布线架构。第一芯片101设有呈阵列分布的第一引脚32a和呈阵列分布的第三引脚41，第二芯片102设有呈阵列分布的第二引脚32b，基板108上设有焊垫42，第一引脚32a和第二引脚32b之间通过布线层104连接，第三引脚41和基板108上的焊垫42之间通过铜柱107连接。第一芯片101上的第一引脚阵列A1包括第一组Z1和第二组Z2，即将第一引脚32a分成两组。第二芯片102上的第二引脚阵列A2包括第三组Z3和第四组Z4，即将第二引脚32b分成两组，第二组Z2和第三组Z3之间通过图5所示的布线层104之第一线路层14实现电连接，第一组Z1和第四组Z4之间通过图6所示的布线层104之第三线路层16实现电连接。其它的实施方式中，布线层104也可以包括第三线路层、第四线路层等，即布线层104可以包括多层线路层，具体的设计依据第一芯片101和第二芯片102之间电信号连接的情况确定。
一种实施方式中，中介板105为硅基板，中介板105上的布线层104的最小线宽线距可达到小于等于0.4um。另一种实施方式中，中介板105为扇出基板，其上的布线层104的最小线宽线距可达到小于等于2um。
本发明之封装结构中，布线层104通过在扇出单元111的表面或的中介板105的表面通过增层工艺(增层是在晶圆表面形成薄膜的加工工艺，这些薄膜可以是绝缘体、半导体或导体)即可实现，无需设置通孔结构，因此布线层104的制作工艺简单，成本也低；且通过第三引脚阵列A3与基板108的直接连接，使得扇出单元111与基板108之间的连接无需设置大面积的中介板，也省去了在中介板上制作通孔的工艺(现有技术中就是通过硅中介层上的硅通孔(TSV,through silicon via)技术实现扇出单元与基板之间电连接的布线，造成工艺难度大，成本高)。因此，本发明具有工艺难度小，成本低的优势，在此基础上，本发明之扇出单元111与基板108之间的电连接布线结构也有利于封装结构的小型化的设计。
本发明还提供一种封装方法，请结合参阅图1至图4，所述封装方法包括如下步骤：
制作扇出单元111，所述扇出单元111包括第一芯片101和第二芯片102，所述第一芯片101包括第一引脚阵列A1，所述第二芯片102包括第二引脚阵列A2，所述扇出单元111还包括第三引脚阵列A3。所述第一引脚阵列A1、所述第二引脚阵列A2及所述第三引脚A3阵列均面对所述基板108设置。具体而言，第一芯片101和第二芯片102相邻设置，所述第一引脚阵列A1与所述第二引脚阵列A2相邻，所述第三引脚阵列A3分布于所述扇出单元111之除所述第一引脚阵列A1和所述第二引脚阵列A2之外的区域。
制作布线层104，所述布线层104跨接于所述第一引脚阵列A1和所述第二引脚阵列A2之间，用于将所述第一引脚阵列A1中的第一引脚连接至所述第二引脚阵列A2中的对应的第二引脚，实现所述第一芯片101和所述第二芯片102之间的电连接。
将所述第三引脚阵列A3连接至基板108，以实现将所述扇出单元111安装至且电连接于所述基板108。基板108上设有与所述基板108的内部布线层电连接的焊垫42(如图5和图6所示)，图1至图4中基板108上焊垫的位置位于铜柱107所对应的基板108的表面，第三引脚阵列A3与焊垫42电连接，具体而言，第三引脚阵列A3与焊垫42通过铜柱107连接。
具体而言，本发一种实施方式中，所述制作扇出单元111的步骤包括：采用模塑料对所述第一芯片101和所述第二芯片102进行模封形成所述扇出单元 111，本发明只是以两个芯片为例进行说明，扇出单元111可以集成多个芯片。以第一芯片101和第二芯片102为晶圆为例子，先将原始晶圆根据需要进行磨薄，第一芯片101和第二芯片102具体的厚度根据产品要求和工艺制程的要求而定，然后对原始晶圆进行切割，形成多个单颗晶圆。再将需要集成的晶圆通过重构及模塑料塑封的方法形成扇出单元111。为了保证第一芯片101和第二芯处之间高密度互连的性能要求，所述第一芯片101与所述第二芯片102之间的距离小于等于50um。所述第一芯片101和所述第二芯片102的侧面被所述模塑料包裹，且侧面被模塑料包裹的厚度可以灵活设计，通常小于5mm。
所述第一芯片101和所述第二芯片102的正面形成所述扇出单元111的外表面，所述第一引脚阵列A1、第二引脚阵列A2和第三引脚阵列A3设于所述第一芯片101和所述第二芯片102的正面。一种实施方式中，第一引脚阵列A1的密度和第二引脚阵列A2的密度均小于第三引脚阵列A3的密度。请参阅图5和图6，第一引脚阵列A1包括多个呈阵列分布的第一引脚32a，第二引脚阵列A2包括多个呈阵列分布的第二引脚32b，第三引脚阵列A3包括多个呈阵列分布的第三引脚41。各第三引脚41的尺寸大于各第一引脚32a的尺寸，各第三引脚41的尺寸亦大于各第二引脚32b的尺寸，第一引脚32a的尺寸与第二引脚32b的尺寸可以相同。
一种实施方式中，制作布线层104的步骤具体为：提供中介板105，所述布线层104为在所述中介板105的一个表面上依增层工艺制作的电路层；将所述中介板105贴合至所述扇出单元111，且使得所述布线层104电连接在第一引脚阵列A1和第二引脚阵列A2之间。具体而言，在布线层104表面制作焊球103，焊球103的数量和尺寸分别与第一引脚和第二引脚的数量和尺寸均一致，将中介板105贴合至扇出单元111的过程中，采用热风重熔或热压键合的工艺贴合，通过焊球103与第一引脚的对应配合及焊球103与和第二引脚的对应配合，以将布线层104连接在第一引脚阵列A1和第二引脚阵列A2之间，实现第一芯片101和第二芯片102之间的连接。另一种实施方式中，直接在扇出单元111的表面制作布线层104，无需中介板105和焊球103。这两种不同的实施方式中，布线层104的制作工艺均可以通过增层工艺制成，制作难度底，且具低成本的优势。布线层104采用钝化、溅射、电镀等工艺制作，走线材料可以选择铜，布线最小线宽线距离可达到小于等于0.4um。
将所述第三引脚阵列A3连接至基板108的过程中，先将铜柱107对应固定在第三引脚的位置处，再将铜柱107对准至基板108上的相应的焊垫，可以通过热风重熔或热压键合的工艺将扇出单元111贴合至基板108。
本发明之封装方法还包括调节安装高度的步骤，通过调节所述第三引脚阵列A3与基板108之间的连接结构(即图1至图4所示的铜柱107)的尺寸来改变所述扇出单元111与所述基板108之间的高度差。具体而言，可以增加扇出单元111一侧的第三引脚阵列A3上的铜柱107的尺寸来改变高度差，或者可以通过在所述基板108上增加焊盘高度的方式来改变高度差。
另一种实施方式中，调节安装高度的步骤可以通过调节布线层104与基板108之间的结构来实现。具体为：通过在所述基板108上设置凹槽1081，且所述凹槽1081与所述布线层104相对设置，通过所述布线层104与所述凹槽1081配合的方式来改变所述扇出单元111与所述基板108之间的高度差，基板108上凹槽1081的设置，使得扇出单元111与基板108之间的高度差变小，有利于封装结构小型化的设计。而且基板108与布线层104之间形成隔离，隔离的架构增加布线层104上的走线的信号隔离度，利于高密度信号的传输。
请参阅图2，本发明一种实施方式中，所述制作扇出单元111的步骤还包括：研磨所述扇出单元111之所述第一芯片101和所述第二芯片102的背面的一侧，使得所述第一芯片101和所述第二芯片102的背面形成所述扇出单元111的外表面，以形成所述扇出单元111的散热表面。散热表面外露有利于封装结构的散热。
请参阅图3，本发明一种实施方式中，所述封装方法还包括制作散热片112，将所述散热片112安装至所述基板108上，使得所述散热片112遮罩所述扇出单元111且与所述散热表面接触。
具体而言，散热片112为金属或非金属导热材质。散热片112与散热表面之间可以增设导热胶，在所述散热表面涂覆导热胶，将所述散热片112安装至所述基板108上，使得所述散热片112遮罩所述扇出单元111且与所述导热胶接触。
本发明之基板108可以为多层基板108，基板108内设有走线层。基板108的正面安装扇出单元111，在基板108的正面设置与扇出单元111的第三引脚阵列A3对应的焊垫42(请参阅图5和图6)，通过铜柱107连接在扇出单元 111和基板108之间。基板108的背面用于与电子设备中的电路板连接，如图1至图4所示，基板108的背面设置焊球109，通过焊球109将封装结构连接至电子设备的电路板上。通过布线层104实现第一芯片101和第二芯片102之间的布线，基板108上的布线层104数就可以得到降低，布线层104与基板108相比较，布线层104面积小且单纯实现第一芯片101与第二芯片102之间的布线，无需在大面积上的基板108上制作更多的布线层104，因此，可以降低封装结构的成本。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (19)

  1. 一种封装结构，其特征在于，包括基板、扇出单元及布线层，所述扇出单元包括第一芯片和第二芯片，所述第一芯片包括第一引脚阵列，所述第二芯片包括第二引脚阵列，所述扇出单元还包括第三引脚阵列，所述第一引脚阵列、所述第二引脚阵列及所述第三引脚阵列均面对所述基板设置，所述第一引脚阵列包括多个第一引脚，所述第二引脚阵列包括多个第二引脚，所述第三引脚阵列包括多个第三引脚；所述布线层跨接于所述第一引脚阵列和所述第二引脚阵列之间，用于将所述第一引脚阵列中的每个第一引脚连接至所述第二引脚阵列中对应的第二引脚，以实现所述第一芯片和所述第二芯片之间的电连接；所述基板上设有与所述基板内部布线层电连接的焊垫，所述第三引脚连接至所述焊垫，以实现所述扇出单元与所述基板之间的电连接。
  2. 如权利要求1所述的封装结构，其特征在于，所述封装结构还包括设于所述扇出单元与所述基板之间的中介板，所述布线层形成在所述中介板的表面。
  3. 如权利要求2所述的封装结构，其特征在于，所述中介板的材质为硅或玻璃或有机基板。
  4. 如权利要求2或3所述的封装结构，其特征在于，所述中介板与所述基板之间彼此隔离。
  5. 如权利要求1所述的封装结构，其特征在于，所述布线层形成于所述第一引脚阵列和所述第二引脚阵列的面对所述基板的表面。
  6. 如权利要求1-5任意一项所述的封装结构，其特征在于，所述布线层包括依次层叠设置的第一线路层、参考层及第二线路层，所述参考层为所述第一线路层和所述第二线路层的参考面。
  7. 如权利要求1至6中任一项所述的封装结构，其特征在于，所述第一芯片的表面和所述第二芯片的表面以形成所述扇出单元的散热表面，所以散热表面位于所述扇出单元之远离所述基板的一侧的表面上。
  8. 如权利要求7所述的封装结构，其特征在于，所述封装结构还包括散热片，所述散热片将所述扇出单元遮罩在所述基板上，且所述散热片与所述散热表面接触。
  9. 如权利要求7所述的封装结构，其特征在于，所述封装结构还包括散热片和导热胶，所述散热片将所述扇出单元遮罩在所述基板上，所述导热胶设于所述散热表面与所述散热片之间。
  10. 如权利要求1-9任意一项所述的封装结构，其特征在于，所述第一芯片和所述第二芯片相邻设置，所述第一引脚阵列与所述第二引脚阵列相邻设置，且所述第三引脚阵列位于所述扇出单元之除所述第一引脚阵列和所述第二引脚阵列之外的区域。
  11. 一种电子设备，其特征在于，所述电子设备包括如权利要求1至10任意一项所述的封装结构。
  12. 一种封装方法，其特征在于，包括：
    制作扇出单元，所述扇出单元包括第一芯片和第二芯片，所述第一芯片包括第一引脚阵列，所述第二芯片包括第二引脚阵列，所述扇出单元还包括第三引脚阵列，所述第一引脚阵列包括多个第一引脚，所述第二引脚阵列包括多个第二引脚，所述第三引脚阵列包括多个第三引脚；
    制作布线层，所述布线层跨接于所述第一引脚阵列和所述第二引脚阵列之间，用于将所述第一引脚阵列中的每个第一引脚连接至所述第二引脚阵列中对应的第二引脚，实现所述第一芯片和所述第二芯片之间的电连接；及
    将所述第三引脚阵列连接至基板，所述基板上设有与所述基板内部布线层电连接的焊垫，所述第三引脚连接至所述焊垫，以实现将所述扇出单元安装至且电连接于所述基板。
  13. 如权利要求12所述的封装方法，其特征在于，所述制作扇出单元的步骤包括：采用模塑料对所述第一芯片和所述第二芯片进行模封形成所述扇出单元，所述第一芯片与所述第二芯处之间的距离小于等于50um，所述第一芯片和所述第二芯片的侧面被所述模塑料包裹，所述第一芯片和所述第二芯片的正面形成所述扇出单元的外表面，所述第一引脚阵列和所述第二引脚阵列分别设于所述第一芯片的正面和所述第二芯片的正面，所述第一引脚阵列和所述第二引脚阵列相邻，所述第三引脚阵列位于所述扇出单元之除所述第一引脚阵列和所述第二引脚阵列之外的区域。
  14. 如权利要求13所述的封装方法，其特征在于，所述制作扇出单元的步骤还包括：研磨所述扇出单元之所述第一芯片和所述第二芯片的背面的一侧， 使得所述第一芯片和所述第二芯片的背面形成所述扇出单元的外表面，以形成所述扇出单元的散热表面。
  15. 如权利要求14所述的封装方法，其特征在于，还包括制作散热片，将所述散热片安装至所述基板上，使得所述散热片遮罩所述扇出单元且与所述散热表面接触。
  16. 如权利要求14所述的封装方法，其特征在于，还包括制作散热片；在所述散热表面涂覆导热胶；将所述散热片安装至所述基板上，使得所述散热片遮罩所述扇出单元且与所述导热胶接触。
  17. 如权利要求12-16任意一项所述的封装方法，其特征在于，还包括提供中介板，所述布线层为在所述中介板的一个表面上依增层工艺制作的电路层；及
    将所述中介板贴合至所述扇出单元，且使得所述布线层将所述第一引脚阵列中的第一引脚连接至所述第二引脚阵列中的对应的第二引脚。
  18. 如权利要求12-17任意一项所述的封装方法，其特征在于，将所述第三引脚阵列连接至基板的过程中，还包括调节安装高度的步骤，通过调节所述第三引脚阵列与基板之间的连接结构的尺寸来改变所述扇出单元与所述基板之间的高度差。
  19. 如权利要求12-18任意一项所述的封装方法，其特征在于，将所述第三引脚阵列连接至基板的过程中，还包括调节安装高度的步骤，通过在所述基板上设置凹槽，且所述凹槽与所述布线层相对设置，通过所述布线层与所述凹槽配合的方式来改变所述扇出单元与所述基板之间的高度差。
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