Classifications

• • H—ELECTRICITY
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28158—Making the insulator
  • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
  • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5226—Via connections in a multilevel interconnection structure
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
  • C23C16/16—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal carbonyl compounds
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
  • C23C16/45523—Pulsed gas flow or change of composition over time
  • C23C16/45525—Atomic layer deposition [ALD]
  • C23C16/45553—Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/46—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
• • H—ELECTRICITY
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
  • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• • H—ELECTRICITY
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
  • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
  • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
  • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
• • H—ELECTRICITY
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  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/53204—Conductive materials
  • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
  • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
• • H—ELECTRICITY
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
  • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
  • H01L21/28562—Selective deposition
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
  • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01044—Ruthenium [Ru]

Definitions

• the present invention relates to methods for void-less filling of features such as vias and trenches with low resistivity ruthenium (Ru) metal for microelectronic devices.
• ruthenium (Ru) metal for microelectronic devices.
• An integrated circuit contains various semiconductor devices and a plurality of conducting metal paths that provide electrical power to the semiconductor devices and allow these semiconductor devices to share and exchange information.
• metal layers are stacked on top of one another using intermetal and interlay er dielectric layers that insulate the metal layers from each other.
• each metal layer must form an electrical contact to at least one additional metal layer.
• Such electrical contact is achieved by etching a feature (i.e., a via) in the interlayer dielectric that separates the metal layers, and filling the resulting via with a metal to create an interconnect.
• Metal layers typically occupy etched pathways in the interlayer dielectric.
• a "via” normally refers to any feature such as a hole, line or other similar feature formed within a dielectric layer that provides an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer.
• metal layers connecting two or more vias are normally referred to as trenches.
• Cu metal layers, Cu filled trenches, and Cu filled vias are normally encapsulated with a barrier material to prevent Cu atoms from diffusing into the dielectrics and Si.
• Barrier layers are normally deposited on trench and via sidewalls and bottoms prior to Cu seed deposition, and may include materials that are preferably non-reactive and immiscible in Cu, provide good adhesion to the dielectrics and can offer low electrical resistivity.
• An increase in device performance is normally accompanied by a decrease in device area or an increase in device density.
• An increase in device density requires a decrease in via dimensions used to form interconnects, including a larger aspect ratio (i.e., depth to width ratio).
• via dimensions decrease and aspect ratios increase it becomes increasingly more challenging to form diffusion barrier layers with adequate thickness on the sidewalls of the vias, while also providing enough volume for the metal layer in the via.
• the material properties of the layers and the layer interfaces become increasingly more important. In particular, the processes forming those layers need to be carefully integrated into a
• a method for void-less Ru metal feature fill for interconnects in a microelectronic device is provided.
• method for at least partially filling a feature in a substrate by providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.
• Ru ruthenium
• a method for filling a feature in a substrate by providing a substrate containing a feature, depositing a conformal ruthenium (Ru) metal layer that fills the feature, and heat-treating the substrate to reflow the conformal Ru metal layer in the feature, where the conformal Ru metal layer has seam voids in the feature and the heat-treating seals the seam voids and increases the grain size of the conformal Ru metal layer in the feature.
• Ru ruthenium
• a method for at least partially filling a feature in a substrate by providing a substrate containing a feature formed in a dielectric layer on the substrate, forming a nucleation layer in the feature, depositing a conformal ruthenium (Ru) metal layer on the nucleation layer to at least partially fill the feature, and heat-treating the substrate to reflow the conformal Ru metal layer in the feature, where the heat-treating reduces voids in the feature fill and increases the grain sizes of the conformal Ru metal layer in the feature.
• Ru ruthenium
• FIG. 1 illustrates dimensions of narrow features in a substrate used for Ru metal fill according to an embodiment of the invention
• FIGS. 2A and 2B show cross-sectional and top view scanning electron microscopy (SEM) images of the features in a substrate used for Ru metal film filling according to an embodiment of the invention
• FIG. 3 A shows cross-sectional SEM images of Ru metal deposition in narrow features in a substrate according to an embodiment of the invention
• FIG. 3B shows cross-sectional SEM images of Ru metal deposition in narrow features in a substrate according to an embodiment of the invention
• FIGS. 4A and 4B show cross-sectional SEM images of as-deposited Ru metal layer in features in a substrate according to an embodiment of the invention.
• FIGS. 5A and 5B show cross-sectional SEM images of a heat-treated Ru metal layer in features in a substrate according to an embodiment of the invention.
• a method for at least partially filling a feature in a substrate.
• the method includes providing a substrate containing a feature, depositing a Ru metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.
• the at least partial filling takes advantage of capillary action to pull heat-softened Ru metal down into very narrow features and recrystallization of the Ru metal to form larger Ru metal grains.
• the inventors have discovered that this unique and unexpected result of low temperature Ru metal recrystallization and reflow can be used to replace Cu metal fill with Ru metal fill.
• the large grain size of the reflowed Ru metal has low electrical resistance that is needed for replacing Cu metal fill in narrow features.
• Ru metal with its short effective electron mean free path, is an excellent candidate to meet International Technology Roadmap for Semiconductors (ITRS) resistance requirements as a Cu metal replacement at about lOnm (5nm node) minimum feature sizes. Due to many material and electric properties of Ru metal, it is less affected by downward scaling of feature sizes than Cu metal.
• ITRS International Technology Roadmap for Semiconductors
• the feature can, for example, include a trench or a via.
• the feature diameter can be less than 30nm, less than 20nm, less than lOnm, or less than 5nm.
• the feature diameter can be between 20nm and 30nm, between lOnm and 20nm, between 5nm and lOnm, or between 3nm and 5nm.
• a depth of the feature can, for example be greater 20nm, greater than 50nm, greater than lOOnm, or greater than 200nm.
• the features can, for example, have an aspect ratio (AR, depth:width) between 2: 1 and 20: 1, between 2: 1 and 10: 1, or between 2: 1 and 5: 1.
• the substrate e.g., Si
• the substrate includes a dielectric layer and the feature is formed in the dielectric layer.
• FIG. 1 illustrates dimensions of narrow features in a substrate used for Ru metal fill according to an embodiment of the invention.
• the narrow features were prepared by etching features in a Si substrate and thereafter depositing (backfilling) an oxide layer (Si0 2 ) in the etched features to reduce the diameter of etched features.
• the etched features had diameters of 50nm, 56nm, 64nm, and 80 nm.
• the backfilled features had diameters (widths) of about 11.5nm, about 14nm, about 17.4nm, and about 28.5nm, near the mid-depths of the features.
• FIGS. 2A and 2B show cross-sectional and top view SEM images of the features in a substrate used for Ru metal film filling according to an embodiment of the invention.
• the features in FIG. 2A had a diameter of about 14nm, a depth of about 120nm, an aspect ratio of about 8.5, and a pitch of about 112nm.
• the features in FIG. 2B had a diameter of about 11.5nm, a depth of about 1 lOnm, an aspect ratio of about 9.5, and a pitch of lOOnm.
• FIG. 3 A shows cross-sectional SEM images of Ru metal deposition in narrow features in a substrate according to an embodiment of the invention. Preparation of the features in the substrate was described in FIG. 1. The features had diameters of about 11.5nm, about 17.4nm, and about 28.5nm. Prior to Ru metal deposition, a 15A thick TaN nucleation layer was deposited in the features using atomic layer deposition (ALD) with alternating exposures of tert- butylimido-tris-ethylmethylamido-tantalum (TBTEMT, Ta(NCMe 3 )(NEtMe) 3 ) and ammonia (NH 3 ) at a substrate temperature of about 350°C.
• ALD atomic layer deposition
• a conformal Ru metal layer with a thickness of 70A was deposited on the TaN nucleation layer by chemical vapor deposition (CVD) using Ru 3 (CO) i2 and CO carrier gas at a substrate temperature of about 200°C.
• FIG. 3A shows that the features having diameters or 11.5nm and 14.5nm were effectively filled with Ru metal, whereas the narrow features having a diameters 28.5nm were not completely filled and had a void in the upper part of the narrow features.
• FIG. 3B shows cross-sectional SEM images of Ru metal deposition in narrow features in a substrate according to an embodiment of the invention. Conformal Ru metal deposition of 15 ⁇ shows that all the features were effectively filled with Ru metal.
• FIGS. 4A and 4B show cross-sectional SEM images of as-deposited Ru metal layer in features in a substrate according to an embodiment of the invention.
• the Ru metal layer was deposited by CVD using Ru 3 (CO)i 2 and CO carrier gas at a substrate temperature of about 200°C, and the features also contained a TaN nucleation layer as described in reference to FIG. 3A.
• the SEM magnifications in FIGS. 4A and 4B are 200,000 and 350,000, respectively.
• the ⁇ 28nm wide features at mid-depth are not completely filled but have a void in the Ru metal that is about 9nm wide near the top of the features.
• FIGS. 5 A and 5B shows cross-sectional SEM images of heat-treated Ru metal in features in a substrate according to an embodiment of the invention.
• the SEM magnifications in FIGS. 4A and 4B are 200,000 and 350,000, respectively.
• the as-deposited Ru metal layer was heat-treated at a substrate temperature of 450°C in the presence of a forming gas for 5 min.
• FIGS. 5A and 5B show that the heat-treating reflowed the Ru metal in the features to effectively fill the narrow features with Ru metal having large grain sizes, and reduced or eliminated voids in the Ru metal feature fill.
• the filling takes advantage of capillary action to pull heat-softened Ru metal down into the very narrow features. Further, any Ru metal seam voids in the feature are sealed by the heat-treating.
• the structures in FIGs. 5A and 5B may be further processed, for example by performing a planarization process (e.g., chemical mechanical polishing (CMP)) that removes excess Ru metal from above the features.
• a planarization process e.g., chemical mechanical polishing (CMP)
• CMP chemical mechanical polishing
• the nucleation layer may be deposited in the features by ALD or CVD prior to the Ru metal fill.
• the nucleation can, for example, include a nitride material.
• the nucleation layer may be selected from the group consisting of Mo, MoN, Ta, TaN, W, WN, Ti, and TiN.
• a role of the nucleation layer is to provide a good nucleation surface and an adhesion surface for Ru metal in the feature to ensure conformal deposition of the Ru metal layer with a short incubation time. Unlike when using a Cu metal fill, a good barrier layer is not required between the dielectric material and the Ru metal in the features.
• the nucleation layer in the case of a Ru metal fill, can be very thin and may be non-continuous or incomplete with gaps that expose the dielectric material in the features. This allows for increasing the amount of Ru metal in a feature fill compared to a Cu metal feature fill.
• a thickness of the nucleation layer can be 2 ⁇ or less, 15A or less, lOA or less, or 5A or less.
• the Ru metal layer may be deposited by ALD, CVD, plating, or sputtering.
• the Ru metal layer may be deposited by CVD using Ru 3 (CO)i2 and CO carrier gas.
• Ru 3 (CO)i2 may be used to deposit the Ru metal layer.
• other Ru metal precursors may be used to deposit the Ru metal layer.
• the Ru metal layer may include a Ru-containing alloy.
• the Ru metal layer may be deposited at a first substrate temperature and the subsequent heat-treating of the as-deposited Ru metal layer may be carried out at a second substrate temperature that is higher than the first substrate temperature.
• the heat-treating may be performed at a substrate temperature between 200°C and 600°C, between 300°C and 400°C, between 500°C and 600°C, between 400°C and 450°C, or between 450°C and 500°C.
• the heat-treating may be performed at below atmospheric pressure in the presence of Ar gas, H 2 gas, or both Ar gas and H 2 gas.
• the heat-treating may be performed at below atmospheric pressure in the presence of forming gas. Forming gas is a mixture of H 2 and N 2 .
• the heat-treating may be formed under high-vacuum conditions without flowing a gas into a process chamber used for the heat-treating.
• the heat-treating may be performed in the presence of a gaseous plasma. This allows for lowering the heat-treating temperature compared to when a gaseous plasma is not employed. This allows the use of heat-treating temperatures that are compatible with low-k and ultra-low-k materials.
• the features may be formed in a low-k material with 2.5 ⁇ k ⁇ 3.9 or an ultra-low-k material with k ⁇ 2.5.
• the gaseous plasma can include Ar gas.
• the plasma conditions may be selected to include low-energy Ar ions.
• the substrate prior to depositing the Ru metal layer, the substrate may be exposed to a treatment gas that modifies the surfaces in the features and increases the nucleation rate of Ru metal layer in the features.
• the treatment gas can include a nitrogen plasma, a NH 3 plasma, a NH 3 anneal, or a combination thereof.
• the exposure to the treatment gas can nitride the surfaces in the features.
• the treatment gas increases the hydrophilicity of surfaces in the features and thereby increases the nucleation rate of the Ru metal in the feature.
• the opening of a feature may pinch off (close) and a void may form inside the feature before the feature is completely filled with a Ru metal layer.
• the void may be removed by removing excess Ru metal from above the feature, for example by a planarization process, thereby removing the excess Ru metal that caused the pinch off.
• the heat-treating process may be performed to reflow the Ru metal layer in the feature. According to one embodiment, this may be followed by depositing additional Ru metal layer on reflowed Ru metal layer and repeating the heat-treating process to achieve void-free filling of the feature.

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• 2016
  • 2016-06-03 CN CN201680040035.5A patent/CN107836034B/zh active Active
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