WO2015172428A1 - 三维半导体器件制造方法 - Google Patents

三维半导体器件制造方法 Download PDF

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Publication number
WO2015172428A1
WO2015172428A1 PCT/CN2014/081924 CN2014081924W WO2015172428A1 WO 2015172428 A1 WO2015172428 A1 WO 2015172428A1 CN 2014081924 W CN2014081924 W CN 2014081924W WO 2015172428 A1 WO2015172428 A1 WO 2015172428A1
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layer
channel
semiconductor device
dimensional semiconductor
manufacturing
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PCT/CN2014/081924
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English (en)
French (fr)
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霍宗亮
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中国科学院微电子研究所
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Priority to US15/311,000 priority Critical patent/US10573658B2/en
Publication of WO2015172428A1 publication Critical patent/WO2015172428A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a three-dimensional semiconductor device capable of effectively increasing channel carrier mobility. Background technique
  • a multi-layered stacked structure (for example, a plurality of ON structures in which oxide and nitride are alternated) may be first deposited on a substrate; an interlayer etching structure on the substrate is etched by an anisotropic etching process to form an edge a plurality of channel vias extending perpendicular to the surface of the substrate (either directly to the surface of the substrate or having a certain overetch); a material such as polysilicon is deposited in the via hole to form a columnar shape Channel; etching the multilayer stack structure along the WL direction to form a trench directly to the substrate, exposing a multilayer stack surrounding the columnar channel; wet removing a certain type of material in the stack (eg, hot phosphoric acid to remove nitrogen) Silicon, or HF to remove silicon oxide), leaving a laterally distributed protrusion structure around the columnar channel; depositing a gate dielectric layer (eg, a high-k dielectric material) and a gate conductive layer on the sidewalls
  • a portion of the protrusions of the stacked structure left on the side walls of the columnar channel form an isolation layer between the gate electrodes, and the remaining gate stack is sandwiched between the plurality of isolation layers as a control electrode.
  • the edge electric field of the gate causes a source/drain region to be induced on the columnar channel sidewall of, for example, a polysilicon material, thereby forming a gate array of a plurality of series-parallel MOSFETs to record the stored logic. status.
  • control gate and gate dielectric layers (typically silicon nitride based dielectrics with good bottom contact characteristics using a simple process) enclose a generally hollow column of polysilicon channel layers (for Subthreshold characteristic control has better control), and the inside of the columnar channel layer can be further filled with a dielectric layer (such as silicon oxide for ease of integration).
  • a dielectric layer such as silicon oxide for ease of integration
  • an aspect of the present invention provides a method of fabricating a three-dimensional semiconductor device, comprising the steps of: forming a stacked structure of a first material layer and a second material layer on a substrate of a memory cell region; and etching the stacked structure to form a plurality of a hole groove; a channel layer is formed in the plurality of holes; and at least one surface of the channel layer is annealed to reduce surface roughness and interface state.
  • channel layer before forming the channel layer, further comprising forming a dummy channel sacrificial layer on sidewalls of the plurality of holes.
  • the material of the dummy channel sacrificial layer comprises silicon nitride, silicon oxynitride or a combination thereof, and has a high selective etching ratio with a material of the first material layer and/or the second material layer.
  • the buffer layer material comprises silicon oxide, silicon nitride, silicon oxynitride and its group o
  • the buffer layer is formed on the surface of the channel layer and/or on a surface facing away from the stacked structure.
  • the annealing treatment is performed under a gas atmosphere containing a nitrogen group, a fluorine group, a chlorine group, a bromine group, or a combination thereof.
  • a gas atmosphere containing a nitrogen group, a fluorine group, a chlorine group, a bromine group, or a combination thereof.
  • forming the drain region further comprises selectively removing the second material layer, leaving a discrete vertical stack structure on the substrate, exposing the channel layer toward the surface of the first material layer.
  • the channel layer is annealed toward the surface of the first material layer.
  • the method further includes: in the stacked structure, sidewalls of the plurality of holes form a plurality of lateral grooves, in the plurality of A gate stack structure of a gate dielectric layer and a gate conductive layer is formed in the recess; a source is formed in the substrate.
  • the gate dielectric layer further includes a tunneling layer, a storage layer, and a barrier layer.
  • a metal nitride layer may be further included between the gate dielectric layer and the gate conductive layer.
  • the cross-sectional shape of the channel layer parallel to the surface of the substrate comprises a shape selected from the group consisting of a rectangle, a square, a diamond, a circle, a semicircle, an ellipse, a triangle, a pentagon, a pentagon, a hexagon, and an octagon.
  • first material layer and the second material layer material each comprise an insulating material, and the first material layer has a first etch selectivity, and the second material layer has a different etch selectivity from the first etch. Second etch selectivity.
  • the first material layer material comprises an insulating material
  • the second material layer material may also comprise a doped semiconductor or a conductive material for forming a control gate.
  • the introduction of the dummy channel sacrificial layer to interface the channel surface and the back surface suppresses the formation of the interface state, and/or the introduction of the channel surface and the back surface buffer layer during processing is lowered.
  • the roughness of the channel surface improves the channel mobility and improves the reliability of the memory cell while increasing the channel current.
  • 1 to 17 are cross-sectional views showing respective steps of a method of fabricating a three-dimensional semiconductor device in accordance with the present invention
  • Figure 18 is a schematic flow chart of a method of fabricating a three-dimensional semiconductor device in accordance with the present invention. detailed description
  • a stacked structure 2 of a first material layer 2A and a second material layer 2B is alternately formed on a substrate 1.
  • the material of the substrate 1 may include bulk silicon, bulk Ge, silicon-on-insulator (SOI), germanium on insulator (GeOI) or other compound semiconductor substrates such as SiGe, SiC, GaN, GaAs, InP, etc., and combinations of these substances.
  • the substrate 1 is preferably a silicon-containing substrate such as Si, SOU SiGe, Si:C or the like.
  • the stacked structure 2 is selected from the group consisting of the following materials and includes at least one insulating medium: silicon oxide, silicon nitride, polycrystalline silicon, amorphous silicon, amorphous carbon, diamond-like amorphous carbon (DLC), cerium oxide, aluminum oxide. , aluminum nitride, metal, etc. and combinations thereof.
  • the first material layer 2A has a first etch selectivity
  • the second material layer 2B has a second etch selectivity and is different from the first etch selectivity.
  • the stacked structures 2A/2B are all insulating materials, the combination of layers 2A/ 2B such as a combination of silicon oxide and silicon nitride, a combination of silicon oxide and polysilicon or amorphous silicon, silicon oxide Or a combination of silicon nitride and amorphous carbon, and the like.
  • one of the stacked structures 2A/2B is a metal, a metal alloy, a metal nitride, a polysilicon (preferably doped), or the like for forming a control gate in the front gate process, and
  • One is one of the insulating media as described above for forming an insulating isolation layer between the control gates in the front gate process.
  • layer 2A and layer 2B have a greater etch selectivity (e.g., greater than 5:1) under wet etching conditions or under oxygen plasma dry etching conditions.
  • the deposition method of the layer 2A and the layer 2B includes various processes such as PECVD, LPCVD, HDPCVD, MOCVD, MBE, ALD, thermal oxidation, evaporation, sputtering, and the like.
  • the 2A layer is, for example, silicon oxide
  • the 2B layer is, for example, silicon nitride.
  • the stacked structure 2 is etched until the substrate 1 is exposed, forming a via 2TP vertically penetrating the stacked structure for defining a channel region.
  • the stacked structure 2 of the anisotropically etched layer 2A/layer 2B is dry etched to expose the substrate 1 and the sidewalls of the layer 2A/layer 2B alternately stacked on the substrate 1.
  • the process conditions of the anisotropic etch stack structure 2 are controlled such that the lateral etch rate is significantly smaller than the longitudinal etch rate to obtain a vertical deep hole having a high aspect ratio (for example, an aspect ratio AR of 10:1 or more) Or deep groove 2TP.
  • the cross-sectional shape of the hole 2 ⁇ cut parallel to the surface of the substrate 1 may be rectangular, square, diamond, circular, semicircular, elliptical, triangular, pentagonal, pentagonal, hexagonal, octagonal, etc. Various geometric shapes.
  • a dummy channel sacrificial layer 3 is formed on the sidewall of the trench 2.
  • the etching ratio is selected, for example, silicon nitride, silicon oxynitride or a combination thereof, in order to temporarily protect the channel layer toward the side of the sidewall of the trench 2TP in each of the later processes, thereby reducing the future trench on the side surface. Interface defects in the layer.
  • the thickness of the dummy channel sacrificial layer 3 is preferably 5 nm or less, for example, 1 - 4 nm and preferably 2 nm 0
  • a channel layer 4 is formed on the bottom of the trench 2TP, and on the sidewalls of the dummy channel sacrificial layer 3 (and preferably on top of the stacked structure 2).
  • the material of the channel layer 4 may include semiconductor materials such as single crystal silicon, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal germanium, SiGe, Si:C, SiGe:C, SiGe:H, and the deposition process is as described above.
  • the channel layer 4 is deposited in such a manner as to partially fill the sidewalls of the trench 2TP to form a hollow cylindrical shape having an air gap.
  • the deposition of the channel layer 4 is selected to completely or partially fill the trench 2TP to form a solid pillar, a hollow ring, or a hollow ring filled insulating layer (not shown).
  • the horizontal section of the channel layer 4 has a shape similar to that of the aperture 2TP and is preferably conformal, and may be a solid rectangle, a square, a diamond, a circle, a semicircle, an ellipse, a triangle, a pentagon, a pentagon, or a hexagon.
  • Various geometric shapes such as a shape, an octagon, and the like, or a hollow annular, barrel-like structure obtained by the above-described geometric shape (and the inside thereof may be filled with an insulating layer).
  • a buffer layer 5A is formed on the channel layer 4 (on the side facing away from the side wall of the stacked structure 2, that is, on the back side of the channel layer 4), so as to be later grooved.
  • the surface defects are further reduced during the surface treatment of the channel layer, for example, the interface state density can be reduced.
  • Forming processes such as thermal oxidation, LPCVD, PECVD, HDPCVD, MBE, ALD, etc., buffer layer 5A material such as silicon oxide, silicon nitride, silicon oxynitride, and the like, and combinations thereof, for example, 0.5 to 5 nm, preferably 1 to 3 nm, most Good 2nm.
  • the steps of forming the buffer layer 5A/5B on both sides of the channel layer 4 as shown in FIG. 5 and later FIG. 11 are optional, that is, the buffer layer may be a single side on the channel layer. Or a double-sided buffer protection structure, or a buffer layer may not be formed.
  • a first annealing process is performed to treat the back surface of the channel layer 4 (the side on which the buffer layer 5A is formed, that is, the side facing away from the stacked structure 2), In order to suppress interface state defects on the back surface of the channel layer 4, the reliability of the device is improved.
  • the annealing process can be carried out in an atmosphere in which an interfacial processing gas is added, and the gas includes a nitrogen group, a fluorine group, a chlorine group, a bromine group gas, and the like, and combinations thereof, such as NH 3 , N 2 , NO, F 2 , NF 3 , HF, HBr, One or more of BCI 3 , HCI, etc.
  • the annealing process is, for example, peak annealing, laser annealing, rapid annealing, etc., and the annealing temperature is, for example, 500 to 1000 degrees Celsius and preferably 650 to 850 degrees Celsius, for example, 10 seconds to 60 minutes and preferably 30 seconds to 5 minutes, 10 minutes to 30 minutes. It is to be noted that the annealing processes shown in FIG. 6 and later in FIG. 12 are optional, that is, an annealing process may be performed on any side, and/or both sides of the channel layer 4.
  • the channel layer 4 is filled with an insulating spacer 6, and the insulating spacer 6 is made of a material such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
  • layers 4, 5A and 6 are planarized by a process such as CMP until the top of stacked structure 2 is exposed.
  • the top layer 5A and the layer 6 are partially etched to expose the top of the channel layer 4, and the material of the channel layer 4 is the same or similar (for example, SiGe, SiC, etc. similar to Si), so as to improve the lattice constant.
  • the material of the carrier mobility, thereby controlling the driving performance of the cell device is deposited on top to form the drain region 4D of the memory device cell transistor.
  • an insulating mask layer 7 is deposited on top of the entire device for later defining the gate region in Fig. 9.
  • the insulating mask layer 7 is made of, for example, silicon nitride, and a deposition process such as PECVD, HDPCVD.
  • the insulating mask layer 7 is used as a mask, and an anisotropic dry etching process is used to sequentially etch the layers 2B and 2A of the stacked structure 2 vertically until the substrate 1 is exposed. A plurality of discrete stacked structures are left on one. Further, an anisotropic selective etching process (preferably wet etching) is used to remove a certain type of layer in the stacked structure 2, for example, removing the layer 2B as shown in FIG. 9, leaving a plurality of layers on the substrate 1.
  • an anisotropic dry etching process preferably wet etching
  • each vertical stacked structure constituting a memory cell region of the device, and a stacked structure
  • the area between them serves as a common source forming area in the future.
  • the layer 2B may be removed by hot phosphoric acid wet etching; when the material of the layer 2B is, for example, silicon oxide, an HF-based etching solution may be used; when the layer 2B is made of polycrystalline silicon or amorphous silicon When the microcrystalline silicon is used, a strong alkaline etching solution such as KOH or TMAH may be used; when the layer 2B material is a carbon-based material such as amorphous carbon or DLC, the layer 2Bo may be removed by oxygen plasma dry etching to remove the layer 2B. A lateral groove is left between the plurality of layers 2A for later forming a gate stack structure. As shown in FIG. 10, the dummy channel sacrificial layer 3 is removed. For example, the layer 3 of silicon nitride or silicon oxynitride is removed by a hot phosphoric acid etching solution.
  • a buffer layer 5B is formed on the front surface of the channel layer 4 (toward the stacking side of the layer 2A remaining in the stacked structure).
  • the formation process and material of layer 5B are similar or identical to layer 5A shown in FIG.
  • layer 5B is also optional, i.e., layer 5A and layer 5B may be arbitrarily present only one, or both may be double-sided buffer layers, or may be absent.
  • a second anneal is performed on the front side of the channel layer 4 to further reduce interface state defects on the surface.
  • the annealing process and parameters of Figure 12 are similar or identical to the first annealing process illustrated in Figure 6.
  • both the second anneal and the first anneal are optional, i.e., the two anneals may be either one or two, but preferably at least one.
  • the tunneling layer 8A comprises Si ⁇ 2 or high-k materials, wherein the high-k materials include, but are not limited to, nitrides (eg, SiN, AIN, TiN), metal oxides (mainly sub-groups and lanthanide metal element oxides, eg MgO, Al2 ⁇ 3, Ta2 ⁇ 5, Ti ⁇ 2, ZnO, Zr02, Hf ⁇ 2, Ce ⁇ 2, ⁇ 2 ⁇ 3, La2 ⁇ 3), nitrogen oxides (such as HfSiON), perovskite phase oxides (For example, PbZr x Th- x 0 3 (PZT), BaxSn-xTiOs (BST)), etc.
  • the tunneling layer 8A may be a single layer structure or a multilayer stack structure of the above materials.
  • the process of depositing 8A includes PECVD, HDPCVD, MOCVD, MBE, ALD, and the like.
  • a memory layer 8B and a barrier layer 8C are sequentially formed on the tunnel oxide layer 8A.
  • the memory layer 8B is a dielectric material having charge trapping ability, such as SiN, HfO, ZrO, etc., and combinations thereof, and may also be a single layer structure or a multilayer stack structure of the above materials.
  • the barrier layer 8C may be a single layer structure or a multilayer stack structure of a dielectric material such as silicon oxide, aluminum oxide or hafnium oxide. Layers 8A, 8B, and 8C together form the gate dielectric layer (stack) of the device cell region transistors.
  • a gate conductive layer 9 is formed between the lateral grooves on the layer 8C and between the layers 2A.
  • the gate conductive layer 9 may be polysilicon, polysilicon, or metal, wherein the metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, lr Metals such as Eu, Nd, Er, and La, or alloys of these metals, and nitrides of these metals, the gate conductive layer 9 may be doped with elements such as C, F, N, 0, B, P, and As. To adjust the work function.
  • a metal nitride (not shown) is also preferably formed between the gate dielectric layer 8 and the gate conductive layer 9 by a conventional method such as PVD, CVD, ALD, or the like.
  • the material is M x N y , MxSiyNz MxAlyNz MaAlxSiyNz, where M is Ta, Ti, Hf, Zr, Mo, W or other elements.
  • layer 9 can be a single layer structure or a multilayer stack structure.
  • a common source region 1 S is formed in the substrate 1 between adjacent vertical stacked structures.
  • the (common) source region 1 S may be formed by ion implantation doping, and preferably further forming a metal silicide (not shown) on the surface.
  • Metal silicide e.g. NiSi2- y, Nii-xPtxSi 2 -y CoSi2- y or Nii-xCoxSi 2 - y, wherein x is greater than 0 and less than 1, y is equal to greater than 0 and less than 1.
  • I LD interlayer dielectric layer 10 of insulating material (material such as silicon oxide, low-k material) is deposited over the entire device, filling the gap between the discrete vertical structures to ensure electrical communication between the individual transistor stacks in the lateral direction. Insulated isolation.
  • insulating material material such as silicon oxide, low-k material
  • the I LD layer 10 and the insulating mask layer 7 are etched to form a word line contact hole exposing the drain region 4D, and a metal material is filled to form the contact plug 1 1 and formed over the contact plug 1 1 for the device.
  • the I LD layer 10 can be filled between the contact plug 1 1 and the metal wiring 12 .
  • the device structure thus formed is as shown in Fig. 17, and includes a channel layer 4 which protrudes vertically from the substrate 1; an interlayer insulating layer 2A and a gate stack structure 8A/8B/8C/9 along the channel layer 4 side
  • the walls are alternately stacked, wherein a buffer layer 5A/5B is formed on at least one surface of the channel layer 4 for reducing surface interface state defects of the channel layer 4, thereby improving device reliability.
  • FIG. 1 A flowchart of a method of manufacturing a semiconductor device is shown in FIG. It is to be noted that the flowchart is only a preferred embodiment of the present invention, and the present invention can be carried out as long as a buffer layer is formed on at least one surface of the channel layer 4 and annealed to reduce surface defects.
  • FIGS. 1 to 17 may include the steps of depositing a stacked structure of the first and second material layers 2A/2B as shown in FIG. 1, wherein the first material layer is The material of the gate conductive layer 9 as described above, for example, a doped semiconductor or conductive structure containing polysilicon, amorphous silicon, microcrystalline silicon, or metal for controlling the gate electrode, and the other layer is an insulating dielectric material to form a layer Inter-insulating layer; etching defines a channel region as shown in FIG.
  • the first material layer is The material of the gate conductive layer 9 as described above, for example, a doped semiconductor or conductive structure containing polysilicon, amorphous silicon, microcrystalline silicon, or metal for controlling the gate electrode, and the other layer is an insulating dielectric material to form a layer Inter-insulating layer; etching defines a channel region as shown in FIG.
  • the atmosphere of the surface treatment gas is to reduce the surface defects of the channel layer 4; the insulating layer 6 is formed by filling the buffer layer 5 surrounded by the channel layer 4 with an insulating material.
  • another embodiment employs a front gate process (the gate structure is included in the stacked structure 2), and one surface of the channel layer 4 is annealed to reduce the interface state defect density.
  • the introduction of the dummy channel sacrificial layer to interface the channel surface and the back surface suppresses the formation of the interface state, and/or the introduction of the channel surface and the back surface buffer layer during processing is lowered.
  • Roughness of the channel surface improves the channel
  • the mobility improves the reliability of the memory cell while increasing the channel current.

Abstract

一种三维半导体器件制造方法，包括步骤：在存储单元区的衬底上形成第一材料层与第二材料层的堆叠结构；刻蚀所述堆叠结构形成多个孔槽；在所述多个孔槽中形成沟道层；对沟道层的至少一个表面进行退火处理，以降低表面粗糙度和界面态。依照所述三维半导体器件制造方法，引入伪沟道牺牲层对沟道表面和背表面进行界面处理抑制了界面态形成，和/或在处理过程中引入沟道表面和背表面缓冲层降低了沟道表面的粗糙度，提高了沟道迁移率，在提高沟道电流的同时提高了存储单元的可靠性。

Description

说 明 书
三维半导体器件制造方法 技术领域
本发明涉及一种半导体器件制造方法，特别是涉及一种能够有效 提高沟道载流子迁移率的三维半导体器件制造方法。 背景技术
为了改善存储器件的密度，业界已经广泛致力于研发减小二维布 置的存储器单元的尺寸的方法。 随着二维（ 2D )存储器件的存储器单 元尺寸持续縮减，信号冲突和干扰会显著增大，以至于难以执行多电 平单元（ MLC )操作。 为了克服 2D存储器件的限制，业界已经研发了 具有三维（ 3D )结构的存储器件，通过将存储器单元三维地布置在衬 底之上来提高集成密度。
具体地， 可以首先在衬底上沉积多层叠层结构（例如氧化物和氮 化物交替的多个 ON结构） ；通过各向异性的刻蚀工艺对衬底上多层 叠层结构刻蚀而形成沿着存储器单元字线（ WL )延伸方向分布、 垂 直于衬底表面的多个沟道通孔（可直达衬底表面或者具有一定过刻 蚀 ) ；在沟道通孔中沉积多晶硅等材料形成柱状沟道；沿着 WL方向 刻蚀多层叠层结构形成直达衬底的沟槽，露出包围在柱状沟道周围的 多层叠层；湿法去除叠层中的某一类型材料（例如热磷酸去除氮化硅， 或 HF去除氧化硅 ) ，在柱状沟道周围留下横向分布的突起结构；在沟 槽中突起结构的侧壁沉积栅极介质层（例如高 k介质材料）以及栅极 导电层（例如 Ti、 W、 Cu、 Mo等 )形成栅极堆叠； 垂直各向异性刻 蚀去除突起侧平面之外的栅极堆叠， 直至露出突起侧面的栅极介质 层；刻蚀叠层结构形成源漏接触并完成后端制造工艺。 此时，叠层结 构在柱状沟道侧壁留下的一部分突起形成了栅电极之间的隔离层，而 留下的栅极堆叠夹设在多个隔离层之间作为控制电极。 当向栅极施加 电压时，栅极的边缘电场会使得例如多晶硅材料的柱状沟道侧壁上感 应形成源漏区，由此构成多个串并联的 MOSFET构成的门阵列而记录 所存储的逻辑状态。 在如上的器件结构中 ，控制栅极和栅极介质层（通常为氮化硅基 介电质，采用简单工艺而具有良好的底部接触特性）包围了通常为空 心柱状的多晶硅沟道层（对于亚阈值特性控制具有更好的控制） ，柱 状沟道层内侧可以进一步填充介质层（例如氧化硅，以便于集成）。 然而，研究表明 ，后栅工艺中氧化物生长的温度可以极大影响在多晶 硅沟道层与栅极介质层以及填充介质层界面处的原生氧化物（形成多 晶硅沟道层时由于局部加热等影响形成的极薄的氧化硅层）薄化和氧 化物表面粗糙度，并且这种表面粗糙度带来的界面态缺陷、 以及多晶 硅沟道层中大量晶粒之间的间隙和间隙界面态使得器件的沟道载流 子迁移率下降，使得存储单元可靠性降低。
发明内容
由上所述，本发明的目的在于克服上述技术困难，提出一种创新 性三维半导体器件制造方法。
为此，本发明一方面提供了一种三维半导体器件制造方法，包括 步骤：在存储单元区的衬底上形成第一材料层与第二材料层的堆叠结 构；刻蚀所述堆叠结构形成多个孔槽；在所述多个孔槽中形成沟道层； 对沟道层的至少一个表面进行退火处理， 以降低表面粗糙度和界面 态。
其中 ，在形成所述沟道层之前进一步包括，在所述多个孔槽的 侧壁上形成伪沟道牺牲层。
其中 ，所述伪沟道牺牲层材质包括氮化硅、 氮氧化硅或其组合， 并且与所述第一材料层和 /或第二材料层的材质具有高选择刻蚀比。
其中 ，在形成所述沟道层之后、 所述退火处理之前进一步包括， 在所述沟道层的至少一个表面上形成缓冲层。
其中 ，所述缓冲层材质包括氧化硅、 氮化硅、 氮氧化硅及其组 口 o
其中 ，所述缓冲层形成在所述沟道层的朝向和 /或背离所述堆叠 结构的表面上。
其中 ，所述退火处理在含有氮基、 氟基、 氯基、 溴基或其组合 的气体氛围下进行。 其中 ，对沟道层背离所述堆叠结构的表面进行退火处理之后， 在所述沟道层中填充绝缘隔离层，并且形成器件晶体管的漏区。
其中 ，形成所述漏区之后进一步包括，选择性去除第二材料层， 在衬底上留下分立的垂直堆叠结构，暴露沟道层朝向所述第一材料层 的表面。
其中 ，对沟道层朝向所述第一材料层的表面进行退火处理。
其中 ，在对沟道层朝向所述第一材料层的表面进行退火处理之 前，进一步包括，在沟道层朝向所述第一材料层的表面上形成缓冲层。
其中 ，在所述对沟道层的至少一个表面进行退火处理之后 ，进 一步包括，在所述堆叠结构中、 所述多个孔槽的侧壁形成横向的多个 凹槽，在所述多个凹槽中形成栅极介质层与栅极导电层的栅极堆叠结 构；在所述衬底中形成源极。
其中 ，所述栅极介质层进一步包括隧穿层、 存储层、 阻挡层。 其中 ，所述栅极介质层与所述栅极导电层之间还可以包括金属氮 化物层。
其中 ，所述沟道层的平行于衬底表面的截面形状包括选自矩形、 方形、 菱形、 圆形、 半圆形、 椭圆形、 三角形、 五边形、 五角形、 六 边形、 八边形及其组合的几何形状，以及包括选自所述几何形状演化 得到的实心几何图形、 空心环状几何图形、 或者空心环状外围层与绝 缘层中心的组合图形。
其中 ，所述第一材料层与第二材料层材质均包括绝缘材料，并 且所述第一材料层具有第一刻蚀选择性，所述第二材料层具有不同于 第一刻蚀选择性的第二刻蚀选择性。
其中 ，所述第一材料层材质包括绝缘材料，所述第二材料层材 质也可以包括掺杂半导体或导电材料以用于形成控制栅极。
依照本发明的三维半导体器件制造方法，引入伪沟道牺牲层对沟 道表面和背表面进行界面处理抑制了界面态形成，和 /或在处理过程中 引入沟道表面和背表面缓冲层降低了沟道表面的粗糙度，提高了沟道 迁移率，在提高沟道电流的同时提高了存储单元的可靠性。 附图说明
以下参照附图来详细说明本发明的技术方案，其中 ： 图 1至图 17为依照本发明的三维半导体器件制造方法的各个步骤 的剖视图 ；以及
图 18为依照本发明的三维半导体器件制造方法的示意性流程图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方 案的特征及其技术效果，公开了有效提高器件可靠性的半导体器件制 造方法。 需要指出的是，类似的附图标记表示类似的结构，本申请中 所用的术语" 第一" 、 " 第二" 、 " 上" 、 " 下" 等等可用于修饰各 种器件结构或制造工序。 这些修饰除非特别说明并非暗示所修饰器件 结构或制造工序的空间、 次序或层级关系。
如图 1所示，在衬底 1上交替形成第一材料层 2A与第二材料层 2B的堆叠结构 2。 衬底 1材质可以包括体硅（ bulk Si )、 体锗（ bulk Ge )、 绝缘体上硅（ SOI )、 绝缘体上锗（ GeOI )或者是其他化合 物半导体衬底，例如 SiGe、 SiC、 GaN、 GaAs、 InP等等，以及这些 物质的组合。 为了与现有的 IC制造工艺兼容，衬底 1优选地为含硅 材质的衬底，例如 Si、 SOU SiGe、 Si:C等。 堆叠结构 2的选自以下 材料的组合并且至少包括一种绝缘介质：如氧化硅、氮化硅、 多晶硅、 非晶硅、 非晶碳、 类金刚石无定形碳（ DLC )、 氧化锗、 氧化铝、 氮 化铝、 金属等及其组合。 第一材料层 2A具有第一刻蚀选择性，第二 材料层 2B具有第二刻蚀选择性并且不同于第一刻蚀选择性。 在本发 明一个优选实施例中 ，叠层结构 2A/2B均为绝缘材料，层 2A/层 2B 的组合例如氧化硅与氮化硅的组合、 氧化硅与多晶硅或非晶硅的组 合、 氧化硅或氮化硅与非晶碳的组合等等。 在本发明另一优选实施例 中 ，叠层结构 2A/2B中的一个为金属、 金属合金、 金属氮化物、 多晶 硅（优选掺杂）等用于形成前栅工艺中控制栅极的材料，另一个为如 上所述绝缘介质之一以用于形成前栅工艺中控制栅极之间的绝缘隔 离层。 在本发明一个优选实施例中 ，层 2A与层 2B在湿法腐蚀条件 或者在氧等离子干法刻蚀条件下具有较大的刻蚀选择比（例如大于 5: 1 )。 层 2A、 层 2B的沉积方法包括 PECVD、 LPCVD、 HDPCVD、 MOCVD、 MBE、 ALD、 热氧化、 蒸发、 溅射等各种工艺。 在如图 2 所示实施例的结构中 ， 2A层例如为氧化硅， 2B层例如为氮化硅。
如图 2所示，刻蚀堆叠结构 2直至露出衬底 1 ，形成垂直穿通堆 叠结构的孔槽 2TP以用于定义沟道区。 优选地，采用 RI E或等离子 干法刻蚀各向异性刻蚀层 2A/层 2B的堆叠结构 2，露出衬底 1以及衬 底 1上交替堆叠的层 2A/层 2B的侧壁。 更优选地，控制各向异性刻 蚀堆叠结构 2的工艺条件以使得横向刻蚀速度显著小于纵向刻蚀速度 而得到高深宽比（例如深宽比 AR大于等于 10: 1 )的垂直的深孔或深 槽 2TP。 平行于衬底 1表面切得的孔槽 2Τ的截面形状可以为矩形、 方形、 菱形、 圆形、 半圆形、 椭圆形、 三角形、 五边形、 五角形、 六 边形、 八边形等等各种几何形状。
如图 3所示，在孔槽 2ΤΡ侧壁形成伪沟道牺牲层 3。通过 PECVD、 HDPCVD、 MBE、 ALD、 蒸发、 溅射等工艺在孔槽 2TP侧壁沉积伪 沟道牺牲层 3，其材质优选与所述第一材料层和 /或第二材料层的材质 具有高选择刻蚀比，例如为氮化硅、 氮氧化硅或其组合，以便于在稍 后各个工艺中临时性保护沟道层朝向孔槽 2TP侧壁的一侧 ，从而减小 该侧面上未来沟道层的界面缺陷。伪沟道牺牲层 3厚度优选为小于等 于 5nm，例如 1 - 4nm并优选 2nm0
如图 4所示，在孔槽 2TP底部、 以及伪沟道牺牲层 3侧壁上（以 及优选地在堆叠结构 2顶部上 )形成沟道层 4。 沟道层 4的材质可以 包括单晶硅、非晶硅、多晶硅、微晶硅、单晶锗、 SiGe、 Si:C、 SiGe:C、 SiGe:H等半导体材料，沉积工艺如上所述。 在本发明图 4所示一个 实施例中 ，沟道层 4的沉积方式为局部填充孔槽 2TP的侧壁而形成为 具有空气隙的中空柱形。 在本发明图中未示出的其他实施例中 ，选择 沟道层 4的沉积方式以完全或者局部填充孔槽 2TP，形成实心柱、 空 心环、 或者空心环内填充绝缘层（未示出）的核心 -外壳结构。沟道层 4的水平截面的形状与孔槽 2TP类似并且优选地共形，可以为实心的 矩形、 方形、 菱形、 圆形、 半圆形、 椭圆形、 三角形、 五边形、 五角 形、 六边形、 八边形等等各种几何形状，或者为上述几何形状演化得 到的空心的环状、 桶状结构（并且其内部可以填充绝缘层）。
任选地，如图 5所示，在沟道层 4上（图中背离堆叠结构 2侧壁 一侧 ， 也即沟道层 4的背面上）形成缓冲层 5A，以便于在稍后对沟 道层表面处理过程中进一步减小表面缺陷 ，例如可以减小界面态密 度。形成工艺例如热氧化、 LPCVD、 PECVD、 HDPCVD、 MBE、 ALD 等，缓冲层 5A材质例如氧化硅、 氮化硅、 氮氧化硅等及其组合，其 厚度例如 0.5 - 5nm、 优选 1 ~ 3nm、 最佳 2nm。值得注意的是，图 5 以及稍后图 1 1所示在沟道层 4两个侧面上形成缓冲层 5A/5B步骤均 是任选的 ，也即缓冲层可以为沟道层上的单面、 或者双面缓冲保护结 构，或者也可以不形成缓冲层。 随后，任选地，如图 6所示，执行第一次退火工艺，对沟道层 4 背表面（形成了缓冲层 5A的那一侧 ， 也即背离堆叠结构 2的一侧 ) 进行处理，以便抑制沟道层 4背表面上界面态缺陷 ，从而提高器件的 可靠性。 退火工艺可以在添加界面处理气体的气氛下进行，气体包括 氮基、 氟基、 氯基、 溴基气体等及其组合，例如 NH3、 N2、 NO、 F2、 NF3、 HF、 HBr、 BCI3、 HCI等一种或多种。 退火工艺例如尖峰退火、 激光退火、快速退火等，退火温度例如 500至 1000摄氏度并优选 650 至 850摄氏度 火时间例如 10秒至 60分钟并优选 30秒至 5分钟、 10分钟至 30分钟。 值得注意的是， 图 6以及稍后图 12所示的退火 工艺均是任选地，也即可以对沟道层 4任意的一侧、和 /或两侧执行退 火工艺。
如图 7所示，在孔槽 2TP中、 沟道层 4上填充绝缘隔离层 6，绝 缘隔离层 6材质例如氧化硅、 氮化硅、 氮氧化硅及其组合。 优选地， 采用 CMP等工艺平坦化层 4、 5A以及 6，直至暴露堆叠结构 2顶部。 优选地，部分刻蚀顶部的层 5A和层 6以露出沟道层 4顶部，采用与 沟道层 4材质相同或者相近（例如与 Si相近的材质 SiGe、 SiC等， 以便微调晶格常数而提高载流子迁移率，从而控制单元器件的驱动性 能 )的材质沉积在顶部而形成存储器件单元晶体管的漏区 4D。
如图 8所示，在整个器件顶部沉积绝缘掩模层 7，以用于稍后图 9 定义栅区域。绝缘掩模层 7材质例如氮化硅，沉积工艺例如 PECVD、 HDPCVD。
如图 9所示，以绝缘掩模层 7为掩模，采用各向异性的干法刻蚀 工艺，依次垂直刻蚀堆叠结构 2的层 2B和层 2A，直至露出衬底 1 ， 在衬底 1上留下多个分立的堆叠结构。 进一步地，采用各向异性的选 择性刻蚀工艺（优选湿法腐蚀） ，去除堆叠结构 2中的某一类型层， 例如如图 9所示去除层 2B，在衬底 1上留下由多个层 2A以及伪沟道 牺牲层 3、 沟道层 4、 缓冲层 5A、 绝缘隔离层 6等构成的多个分立垂 直的堆叠结构，各个垂直堆叠结构构成了器件的存储单元区，堆叠结 构之间的区域用作将来公用源极形成区域。 当层 2B材质例如为氮化 硅材质时，可以采用热磷酸湿法腐蚀去除层 2B；当层 2B材质例如为 氧化硅时，可以采用 HF基腐蚀液；当层 2B材质为多晶硅、 非晶硅、 微晶硅时，可以采用 KOH、 TMAH等强碱性腐蚀液；当层 2B材质例 如为非晶碳、 DLC等碳基材质时，可以采用氧等离子干法刻蚀去除层 2Bo 移除 2B之后，在多个层 2A之间留下了横向的凹槽，用于稍后 形成栅极堆叠结构。 如图 10所示，移除伪沟道牺牲层 3。例如采用热磷酸腐蚀液去除 氮化硅、 氮氧化硅材质的层 3。
任选地，如图 1 1所示，在沟道层 4正面（朝向堆叠结构中剩余 的层 2A堆叠一侧）形成缓冲层 5B。 层 5B的形成工艺与材质类似于 或者等同于图 5所示的层 5A。 类似的 ，层 5B也是任选的 ， 也即层 5A与层 5B可以任意地仅存在一个，或者均存在为两面缓冲层 ，或者 也可以均不存在。
任选地，如图 12所示，对沟道层 4正面进行第二次退火，以进 一步减小该表面上的界面态缺陷。 图 12的退火工艺以及参数类似于 或者等同于图 6所示的第一次退火工艺。 类似的 ，第二次退火与第一 次退火均是任选的 ，也即两次退火可以任选其一、或者采用两次退火， 但是优选地至少进行一次退火。
如图 13所示，在剩余结构上（也即绝缘掩模层 7顶部上、 第一 材料层 2A侧壁以及底面上、 缓冲层 5B侧壁上，换言之，在层 2A之 间的横向凹槽的表面）形成隧穿氧化层 8A。其中隧穿层 8A包括 Si〇2 或高 k材料，其中高 k材料包括但不限于氮化物（例如 SiN、 AIN、 TiN )、 金属氧化物（主要为副族和斓系金属元素氧化物，例如 MgO、 Al2〇3、 Ta2〇5、 Ti〇2、 ZnO、 Zr02、 Hf〇2、 Ce〇2、 丫2〇3、 La2〇3 )、 氮氧化物（如 HfSiON )、钙钛矿相氧化物（例如 PbZrxTh-x03( PZT )、 BaxSn-xTiOs ( BST ) )等，隧穿层 8A可以是上述材料的单层结构或 多层堆叠结构。 沉积 8A的工艺包括 PECVD、 HDPCVD、 MOCVD、 MBE、 ALD等。
如图 14所示，在隧穿氧化层 8A上依次形成存储层 8B和阻挡层 8C。 存储层 8B是具有电荷俘获能力的介质材料，例如 SiN、 HfO、 ZrO等及其组合， 同样可以是上述材料的单层结构或多层堆叠结构。 阻挡层 8C可以是氧化硅、 氧化铝、 氧化铪等介质材料的单层结构或 多层堆叠结构。 层 8A、 8B和 8C共同构成了器件单元区晶体管的栅 极介质层（堆叠）。
如图 15所示，在层 8C上、 层 2A之间横向凹槽之间填充形成栅 极导电层 9。 栅极导电层 9可以是多晶硅、 多晶锗硅、 或金属 ，其中 金属可包括 Co、 Ni、 Cu、 Al、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 lr、 Eu、 Nd、 Er、 La等金属单质、 或这些金属的合金以 及这些金属的氮化物，栅极导电层 9中还可掺杂有 C、 F、 N、 0、 B、 P、 As等元素以调节功函数。栅极介质层 8与栅极导电层 9之间还优 选通过 PVD、 CVD、 ALD等常规方法形成金属氮化物（未示出 ) ， 材质为 MxNy、 MxSiyNz MxAlyNz MaAlxSiyNz，其中 M为 Ta、 Ti、 Hf、 Zr、 Mo、 W或其它元素。 同样地，层 9可以是单层结构也可以 是多层堆叠结构。
如图 16所示，在衬底 1 中、 相邻垂直堆叠结构之间形成共用的 源区 1 S。 可以通过离子注入掺杂、 以及优选地进一步在表面形成金 属硅化物（未示出）而形成（公用的）源区 1 S。金属硅化物例如 NiSi2-y、 Nii-xPtxSi2-y CoSi2-y或 Nii-xCoxSi2-y，其中 x均大于 0小于 1 ， y均 大于等于 0小于 1。 随后，在整个器件上沉积绝缘材料的层间介质层 ( I LD ) 10 (材质例如氧化硅、 低 k材料） ，填充了各个分立垂直结 构之间的间隙，确保横向的各个晶体管堆叠之间电绝缘隔离。
如图 17所示，刻蚀 I LD层 10以及绝缘掩模层 7，形成暴露漏区 4D的字线接触孔，填充金属材料形成接触塞 1 1 ，并在接触塞 1 1上 方形成用于器件单元中字线（ bit-line )的金属布线 12。 接触塞 1 1与 金属布线 12之间可以采用 I LD层 10，填充。
由此形成的器件结构如图 17所示，包括沟道层 4，垂直地从衬底 1突起；层间绝缘层 2A与栅极堆叠结构 8A/8B/8C/9沿着沟道层 4侧 壁交替层叠，其中 ，沟道层 4的至少一个表面上形成有缓冲层 5A/5B， 以用于减小沟道层 4表面界面态缺陷 ，提高器件可靠性。
半导体器件的制造方法的流程图如图 18所示。值得注意的是，该 流程图仅为本发明一个优选实施例，而只要是在沟道层 4的至少一个 表面上形成缓冲层并且退火处理以降低表面缺陷即可实施本发明。
此外， 图 1至图 17中未示出的另一个本发明优选实施方式可以 包括以下步骤：如图 1所示沉积第一和第二材料层 2A/2B的堆叠结构， 其中第一材料层为如上所述的栅极导电层 9的材质，例如包含多晶硅、 非晶硅、 微晶硅、 或金属的掺杂半导体或导电结构以用于控制栅极， 另一层为绝缘介质材料而构成层间绝缘层；如图 2所示刻蚀定义沟道 区；在沟槽 2TP中沉积沟道层 4；任选的在沟道层 4背面沉积缓冲层 5；执行退火（任选的采用包含上述表面处理气体的气氛）以降低沟 道层 4表面缺陷 ；在沟道层 4包围的缓冲层 5上填充绝缘材料形成绝 缘隔离层 6。 换言之，另一个实施例采用的前栅工艺（堆叠结构 2中 包含了栅极堆叠结构） ，并对于沟道层 4的一个表面进行了退火处理 以降低界面态缺陷密度。
依照本发明的三维半导体器件制造方法，引入伪沟道牺牲层对沟 道表面和背表面进行界面处理抑制了界面态形成，和 /或在处理过程中 引入沟道表面和背表面缓冲层降低了沟道表面的粗糙度，提高了沟道 迁移率，在提高沟道电流的同时提高了存储单元的可靠性。 尽管已参照一个或多个示例性实施例说明本发明 ，本领域技术人 员可以知晓无需脱离本发明范围而对器件结构或方法流程做出各种 合适的改变和等价方式。 此外，由所公开的教导可做出许多可能适于 特定情形或材料的修改而不脱离本发明范围。 因此，本发明的目的不 在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施 例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所 有实施例。

Claims

权 利 要 求 书
1 . 一种三维半导体器件制造方法，包括步骤：
在存储单元区的衬底上形成第一材料层与第二材料层的堆叠结 构；
刻蚀所述堆叠结构形成多个孔槽；
在所述多个孔槽中形成沟道层；
对沟道层的至少一个表面进行退火处理，以降低表面粗糙度和界 面态。
2 . 如权利要求 1所述的三维半导体器件制造方法，其中 ，在形成所 述沟道层之前进一步包括，在所述多个孔槽的侧壁上形成伪沟道 牺牲层。
3 . 如权利要求 2所述的三维半导体器件制造方法，其中 ，所述伪沟 道牺牲层材质包括氮化硅、氮氧化硅或其组合，并且与所述第一 材料层和 /或第二材料层的材质具有高选择刻蚀比。
4 . 如权利要求 1所述的三维半导体器件制造方法，其中 ，在形成所 述沟道层之后、所述退火处理之前进一步包括，在所述沟道层的 至少一个表面上形成缓冲层。
5 . 如权利要求 4所述的三维半导体器件制造方法，其中 ，所述缓冲 层材质包括氧化硅、 氮化硅、 氮氧化硅或其组合。
6 . 如权利要求 4所述的三维半导体器件制造方法，其中 ，所述缓冲 层形成在所述沟道层的朝向和 /或背离所述堆叠结构的表面上。
7 . 如权利要求 1所述的三维半导体器件制造方法，其中 ，所述退火 处理在含有氮基、氟基、氯基、溴基或其组合的气体氛围下进行。
8 . 如权利要求 1所述的三维半导体器件制造方法，其中 ，对沟道层 背离所述堆叠结构的表面进行退火处理之后，在所述沟道层中填 充绝缘隔离层，并且形成器件晶体管的漏区。
9 . 如权利要求 8所述的三维半导体器件制造方法，其中 ，形成所述 漏区之后进一步包括，选择性去除第二材料层，在衬底上留下分 立的垂直堆叠结构，暴露沟道层朝向所述第一材料层的表面。
10 . 如权利要求 9所述的三维半导体器件制造方法，其中 ，对沟道层 朝向所述第一材料层的表面进行退火处理。
1 1 . 如权利要求 10所述的三维半导体器件制造方法，其中 ，在对沟 道层朝向所述第一材料层的表面进行退火处理之前，进一步包 括，在沟道层朝向所述第一材料层的表面上形成缓冲层。
12 . 如权利要求 1所述的三维半导体器件制造方法，其中 ，在所述对 沟道层的至少一个表面进行退火处理之后，进一步包括，在所述 堆叠结构中、所述多个孔槽的侧壁形成横向的多个凹槽，在所述 多个凹槽中形成栅极介质层与栅极导电层的栅极堆叠结构；在所 述衬底中形成源极。
13 . 如权利要求 12所述的三维半导体器件制造方法，其中 ，所述栅 极介质层进一步包括隧穿层、 存储层、 阻挡层。
14 . 如权利要求 12所述的三维半导体器件制造方法，其中 ，所述栅 极介质层与所述栅极导电层之间可以包括金属氮化物层。
15 . 如权利要求 1所述的三维半导体器件制造方法，其中 ，所述沟道 层的平行于衬底表面的截面形状包括选自矩形、 方形、菱形、 圆 形、 半圆形、 椭圆形、 三角形、 五边形、 五角形、 六边形、 八边 形及其组合的几何形状，以及包括选自所述几何形状演化得到的 实心几何图形、空心环状几何图形、或者空心环状外围层与绝缘 层中心的组合图形。
16 . 如权利要求 1所述的三维半导体器件制造方法，其中 ，所述第一 材料层与第二材料层材质均包括绝缘材料，并且所述第一材料层 具有第一刻蚀选择性，所述第二材料层具有不同于第一刻蚀选择 性的第二刻蚀选择性。
17. 如权利要求 1所述的三维半导体器件制造方法，其中 ，所述第一 材料层材质包括绝缘材料，所述第二材料层材质可以包括掺杂半 导体或导电材料以用于形成控制栅极。
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