WO2017028387A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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WO2017028387A1
WO2017028387A1 PCT/CN2015/095245 CN2015095245W WO2017028387A1 WO 2017028387 A1 WO2017028387 A1 WO 2017028387A1 CN 2015095245 W CN2015095245 W CN 2015095245W WO 2017028387 A1 WO2017028387 A1 WO 2017028387A1
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layer
amorphous
channel layer
substrate
forming
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PCT/CN2015/095245
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French (fr)
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叶甜春
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中国科学院微电子研究所
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Priority to US15/753,376 priority Critical patent/US10483279B2/en
Publication of WO2017028387A1 publication Critical patent/WO2017028387A1/zh

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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02587—Structure
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a three-dimensional memory polycrystalline channel layer.
  • three-dimensional memory cannot use single crystal (silicon) materials and can only use polycrystalline (silicon) materials as channels.
  • the grain size of the polycrystalline (silicon) material and the trap of the grain boundary become the key to restrict the channel conduction capability.
  • the high interface state makes the leakage of the channel larger, and the characteristics have a great influence on the temperature.
  • a stack of different dielectric materials 2A/2B is deposited on the substrate 1 to serve as a dummy gate, and an opening filling insulating material is etched between the plurality of dummy gate stacks to form an insulating isolation layer 3 between the memory cells.
  • the isolation layer 3 surrounds a plurality of active regions, and the dummy gate stack in the etch active region forms a trench trench in which the gate dielectric 4 is deposited.
  • the film thickness of the layer 5 is small, for example, only 0.2 to 5 nm, the film quality is poor, the thickness is uneven, and there are a large number of defects on the surface.
  • the gate dielectric 4 is etched until the substrate 1 is exposed.
  • the dry etching gas is laterally etched in addition to the gate dielectric 4 at the bottom of the trench trench.
  • the channel layer 5 is further increased in surface defects and damage.
  • damage defects on the surface of the first amorphous channel layer 5 are retained, forming a poorer relationship with the second amorphous channel layer 7.
  • the object of the present invention is to overcome the above technical difficulties and to provide a three-dimensional memory manufacturing method capable of effectively reducing the interface state and damage defects of the polycrystalline channel layer and effectively improving the reliability of the device.
  • an aspect of the present invention provides a semiconductor device manufacturing method including the steps of: forming a gate dielectric layer and a first amorphous channel layer on a substrate; thinning the first amorphous channel layer; etching first An amorphous channel layer, a gate dielectric layer until the substrate is exposed; a second amorphous channel layer is formed on the first amorphous channel layer and the substrate; and annealed such that the first amorphous channel layer and the second amorphous layer The channel layer is transformed into a polycrystalline channel layer; the polycrystalline channel layer is thinned.
  • the gate dielectric layer comprises a plurality of sub-layers selected from the group consisting of a tunneling layer, a storage layer and a barrier layer.
  • the first amorphous channel layer is selected from the group consisting of amorphous Si and amorphous Ge.
  • the second amorphous channel layer is selected from the group consisting of amorphous Ge, amorphous SiGe, amorphous SiC, amorphous SiGeC, amorphous C, III-V or II-VI amorphous compound semiconductor, and combinations thereof.
  • the second amorphous channel layer comprises a dopant, and the annealing activates the dopant.
  • the protective layer is a single layer or a multilayer structure.
  • forming the gate dielectric layer and the first amorphous channel layer on the substrate includes forming a dummy gate stack on the substrate, and etching the dummy gate stack to form a plurality of trench trenches of the vertical substrate, A gate dielectric layer and a first amorphous channel layer are sequentially deposited in the trenches.
  • the thinning the polycrystalline channel layer further includes forming source and drain regions at upper and lower ends of the polycrystalline channel layer, removing the dummy gate stack, and forming a gate conductive layer on a side of the gate dielectric layer.
  • the annealing temperature is 300 to 850 ° C, and the annealing time is 1 minute to 10 hours.
  • an amorphous thick film is deposited and then thinned and annealed to increase the grain size of the polycrystalline film, and an additional protective layer is used to avoid sidewall etching damage, and the polycrystalline channel layer can be effectively reduced.
  • the interface state and damage defects improve the reliability of the device.
  • 1 to 4 are cross-sectional views showing respective steps of a method of fabricating a three-dimensional memory device of the prior art
  • 5 to 11 are cross-sectional views showing respective steps of a method of fabricating a three-dimensional memory device of the present invention.
  • FIG. 12 is a schematic flow chart of a method of fabricating a three-dimensional memory device of the present invention.
  • a gate dielectric 4 and a first amorphous channel layer 5 are formed in a trench of the substrate 1.
  • a stacked structure 2 of the first material layer 2A and the second material layer 2B is alternately formed on the substrate 1.
  • the material of the substrate 1 may include bulk silicon, bulk Ge, silicon-on-insulator (SOI), germanium on insulator (GeOI) or other compound semiconductor substrates such as SiGe, SiC, GaN, GaAs, InP, etc., and combinations of these substances.
  • substrate 1 is preferably a silicon-containing substrate such as Si, SOI, SiGe, Si:C, and the like.
  • the stack structure 2 is selected from the group consisting of the following materials and includes at least one insulating medium such as silicon oxide, silicon nitride, amorphous carbon, diamond-like amorphous carbon (DLC), cerium oxide, aluminum oxide, and the like, and combinations thereof.
  • the first material layer 2A has a first etch selectivity
  • the second material layer 2B has a second etch selectivity and is different from the first etch selectivity (eg, an etch selectivity ratio between the two materials is greater than 5:1 And preferably greater than 10:1).
  • the stacked structures 2A/2B are all non-conductive materials, the combination of layers 2A/ 2B such as a combination of silicon oxide and silicon nitride, silicon oxide and (undoped) polycrystalline silicon or amorphous A combination of silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, and the like.
  • layer 2A and layer 2B have a greater etch selectivity (e.g., greater than 5:1) under wet etching conditions or under oxygen plasma dry etching conditions.
  • layer 2A and layer 2B include PECVD, LPCVD, HDPCVD, MOCVD, Various processes such as MBE, ALD, thermal oxidation, evaporation, sputtering, and the like.
  • layer 2A is silicon dioxide and layer 2B is silicon nitride.
  • Etching the stacked structure 2 in the array region until the substrate 1 is exposed, forming a dummy gate opening (or first opening, centered in FIG. 5) and forming a filling layer 3 therein (filled layer)
  • the underlying substrate will form a future common source region).
  • the stacked structure 2 of the anisotropically etched layer 2A/layer 2B is etched by RIE or plasma dry etching to form an opening which exposes the substrate 1 and the sidewalls of the layer 2A/layer 2B which are alternately stacked on the substrate 1. (not shown).
  • Etching gas for example, a fluorocarbon-based etching gas for materials such as silicon dioxide and silicon nitride, and forming a temporary protective sidewall formed of a C-containing polymer on the sidewall by increasing a carbon-to-fluorine ratio, and finally obtaining a better Vertical side walls.
  • the etching gas is preferably a gas having a relatively high C content such as C 3 F 6 or C 4 F 8 and further preferably controls the sidewall morphology by adding an oxidizing gas such as O 2 , CO or the like.
  • the cross-sectional shape of the hole cut parallel to the surface of the substrate 1 may be rectangular, square, diamond, circular, semi-circular, elliptical, triangular, pentagonal, pentagon, hexagonal, octagonal, etc. Geometric shapes.
  • the filling layer 3 deposition method includes PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, etc., and the material is preferably a material having high selectivity to both the layer 2A and the layer 2B of the stacked structure 2, such as layer 3, layer 2A, The etching selectivity ratio between each of the two layers 2B is greater than or equal to 5:1.
  • layer 2A is silicon oxide
  • layer 2B is silicon nitride
  • filling layer 3 is amorphous germanium, amorphous carbon, DLC silicon oxynitride, etc., and vice versa.
  • Etching gas for example, a fluorocarbon-based etching gas for materials such as silicon dioxide and silicon nitride, and forming a temporary protective sidewall formed of a C-containing polymer on the sidewall by increasing a carbon-to-fluorine ratio, and finally obtaining a better Vertical side walls.
  • the etching gas is preferably a gas having a relatively high C content such as C 3 F 6 or C 4 F 8 and further preferably controls the sidewall morphology by adding an oxidizing gas such as O 2 , CO or the like.
  • the size (e.g., diameter) of the first opening for exposing the common source region is greater than or equal to the second opening for forming the channel region.
  • the size for example, the ratio of the two dimensions (the ratio of the diameter or the maximum span of the polygon) is greater than 1.5 and preferably greater than or equal to two.
  • the deposition method of the gate dielectric layer 4 includes PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, and the like.
  • layer 4 preferably further comprises a plurality of sub-layers, such as a tunneling layer, a storage layer, a barrier layer.
  • the tunneling layer comprises SiO 2 or a high-k material, wherein the high-k material includes, but is not limited to, nitrides (eg, SiN, SiON, AlN, TiN), metal oxides (mainly sub-groups and lanthanide metal element oxides, eg MgO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZnO, ZrO 2 , HfO 2 , CeO 2 , Y 2 O 3 , La 2 O 3 ), nitrogen oxides (eg HfSiON), perovskite phase oxidation
  • the tunneling layer may be a single layer structure or a multilayer stack structure of the above materials (for example, PbZr x Ti 1-x O 3 (PZT), Ba x Sr 1-x TiO 3 (BST)) or the like.
  • the memory layer is a dielectric material having charge trapping ability, such as SiN, HfO x , ZrO x , YO x , and the like, and combinations thereof, and may also be a single layer structure or a multilayer stack structure of the above materials.
  • the barrier layer may be a single layer structure or a multilayer stack structure of a dielectric material such as silicon oxide, aluminum oxide, or cerium oxide.
  • the gate dielectric layer 4 is, for example, an ONO structure composed of silicon oxide, silicon nitride, or silicon oxide.
  • a first amorphous channel layer 5' is formed on the gate dielectric layer 4.
  • the material of the first amorphous channel layer 5' is, for example, amorphous silicon or amorphous germanium, and the deposition process includes LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, and the like.
  • the first amorphous channel layer 5' is deposited in such a manner as to partially fill the sidewalls of the second opening to form a hollow cylindrical shape having an air gap.
  • the deposition manner of the first amorphous channel layer 5' is selected to completely or partially fill the second opening to form a solid pillar, a hollow ring, or a hollow ring filled insulating layer (not shown).
  • the shape of the horizontal section of the first amorphous channel layer 5' is similar to and preferably conformal to the second opening, and may be a solid rectangle, a square, a diamond, a circle, a semicircle, an ellipse, a triangle, and a five sides.
  • geometric shapes such as a shape, a pentagon, a hexagon, an octagon, etc., or a hollow annular, barrel-like structure obtained by the above-described geometric shape (and the inside thereof may be filled with an insulating layer).
  • the process shown in FIG. 5 differs from the process shown in FIG. 1 in that the applicant has realized through strict theoretical derivation and rigorous experimental verification that the thickness of the first amorphous channel layer of the prior art is too thin, and the quality of the deposited film is Poor, the grain size is too small, and the density of the defect state of the polycrystalline film formed by subsequent annealing is too large. Therefore, the applicant intentionally increases the thickness of the first amorphous channel layer 5' (preferably larger than the maximum grain size of the amorphous material obtained by the deposition process), for example, 5 to 30 nm, which is larger than that of FIG. 1 and FIG. The thickness of the first amorphous channel layer 5 is required.
  • the amorphous material has sufficient time and space to be merged into crystallites at a position close to the gate dielectric layer 4, or the average size of the crystal grains is increased, so that the closer to the gate dielectric layer 4. The better the film quality of the amorphous layer 5'.
  • the first amorphous channel layer 5' is thinned to become the first amorphous channel layer 5.
  • an isotropic etching process is used, such as KOH, TMAH for amorphous silicon, or a mixed solution of strong acid and strong oxidizing agent for amorphous germanium, which will be the first non-
  • the thickness of the crystal channel layer 5' is reduced from 5 to 30 nm to 0.2 to 5 nm of the first amorphous channel layer 5, that is, the thickness of the nucleation layer or the interface layer required for the subsequent process (the thickness may be close to or smaller than The maximum grain size of the amorphous material obtained by the deposition process shown in FIG. In this process, since the film quality close to the gate dielectric layer 4 is significantly better, the amorphous channel layer 5 left after thinning will have a better average film quality than the original thick film 5', which facilitates the subsequent film. Growth.
  • a protective layer 6 is formed on the thinned first amorphous channel layer 5.
  • the material of the protective layer 6 is selected to have a higher etching selectivity with the layer 5 (for example, an etching selectivity ratio of 5:1 or more, preferably 10:1 or more, preferably 15:1 or more), such as silicon oxide. , silicon nitride, silicon oxynitride, amorphous carbon, DLC, ta-C, and the like.
  • the protective layer 6 may be a single layer structure or a multilayer structure composed of a plurality of materials.
  • the thickness of the protective layer 6 is preferably thin, for example, 1 to 5 nm.
  • the deposition process of the protective layer 6 is preferably conformal deposition, such as LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, magnetron sputtering, and the like.
  • the protective layer 6, the first amorphous channel layer 5, and the gate dielectric layer 4 are etched until the substrate 1 is exposed.
  • the etching process is preferably an anisotropic dry etching, such as plasma dry etching, reactive ion etching (RIE), an etching gas such as a fluorocarbon-based gas, optionally further including an oxidizing gas to adjust the etching. rate.
  • RIE reactive ion etching
  • the ratio of the etching gas is adjusted such that the etching rate in the vertical direction is significantly greater than the lateral etching rate in the horizontal direction, for example, the speed ratio is greater than or equal to 5, preferably greater than or equal to 10, and most preferably greater than or equal to 15.
  • the sidewall of the first amorphous channel layer 5 is not eroded by the etching gas due to the protection of the etching gas by the protective layer 6, thereby reducing interface defects with respect to FIG. 2 of the prior art. Further improved device reliability.
  • the protective layer 6 is completely removed by an isotropic wet process to expose the surface of the first amorphous channel layer 5.
  • a second amorphous channel layer 7 is formed on the first amorphous channel layer 5.
  • the second amorphous channel layer 7 is deposited by a process similar to that of the first amorphous channel layer 5, such as LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, or the like.
  • layer 7 is of the same material as layer 5, such as amorphous Si or amorphous Ge. In other embodiments of the present invention, the material of the layer 7 may be different from the material of the layer 5.
  • the layer 7 is amorphous Ge, amorphous SiGe, amorphous SiC, amorphous SiGeC, amorphous.
  • C either a III-V or II-VI group amorphous compound semiconductor, or layer 7 is a laminate of amorphous silicon and the other amorphous materials described above.
  • the channel layer formed after subsequent polycrystallization will have stress due to lattice mismatch between different materials, thereby improving carrier mobility and improving device driving performance.
  • layer 7 may be doped after implantation, or doped in situ, with n Or p-type impurities to form different types of MOSFETs. Similar to the process shown in FIG.
  • the thickness of the layer 7 is significantly larger than the thickness of the amorphous layer finally required, thereby increasing the grain size at the interface and reducing the grain size as the thickness of the deposited film changes. Defect density at the small interface.
  • layer 7 has a thickness of 5 to 100 nm.
  • the first amorphous layer 5 and the second amorphous layer in FIG. 9 are obtained by increasing the initial film thickness, increasing the interface grain size, and FIG. 7 and FIG. 8 using the protective layer to reduce the etching damage.
  • the interface quality of the amorphous material between the layers 7 is good (no longer indicated by thick solid lines as shown in Figs. 3 and 4, but instead a dotted line is used), and the interface state defect density is reduced.
  • the first amorphous channel layer 5 and the second amorphous channel layer 7 are transformed into a polycrystalline channel layer 8/8' by annealing.
  • layer 8/8' is polysilicon.
  • the layer 8/8' may be a lamination or mixing of polycrystalline Si with other polycrystalline materials (material diffusion or reactive alloying during annealing), and other polycrystalline materials including polycrystalline Ge, polycrystalline SiGe, polycrystalline SiC, polycrystalline SiGeC, or a III-V or II-VI polycrystalline compound semiconductor.
  • the thickness of the polycrystalline layer 8 is approximately equal to the thickness of the layer 7, for example also 5 to 100 nm, or has a thickness difference of less than 10%, preferably less than 5%.
  • annealing if layer 7 has a dopant, polycrystallization annealing also activates the dopant simultaneously, such that the channel layer has a certain substrate doping concentration.
  • the annealing temperature is, for example, 300 to 850 ° C, and the grain size of the channel is controlled by a low temperature process to reduce leakage current.
  • the annealing time is, for example, 1 minute to 10 hours.
  • the polycrystalline channel layer 8/8' is thinned.
  • an isotropic etching process is used to thin the polycrystalline channel layer to a desired level of, for example, 5 to 20 nm. Thereafter, the subsequent process can be further performed to complete the device fabrication.
  • an insulating isolation layer (not shown) is filled inside the channel layer 8, and a silicon oxide layer is formed, for example, by LPCVD, PECVD, HDPCVD, or the like for supporting, insulating, and isolating the channel layer 8. Thereafter, a drain contact is deposited on top of the channel layer 8.
  • a material which is the same as or similar to the material of the channel layer 8 for example, a material similar to Si, SiGe, SiC, etc., in order to fine-tune the lattice constant to improve carrier mobility, thereby controlling the driving performance of the cell device
  • a drain region of the memory device cell transistor is formed at the top of the second opening, and a silicide (not shown) may be further formed to lower the contact resistance.
  • the filling layer 3 is selectively etched to re-expose the first opening, and the second material layer (pseudo-gate layer) 2B in the stacked structure is removed by lateral etching using the first opening. Subsequently, using an isotropic dry etch process, the layer 2B is laterally etched away leaving a lateral recess between the layers 2A. For example, the carbon-to-fluorine ratio is reduced to laterally etch the layer 2B of silicon nitride, or the layer 2B of silicon nitride is etched with hot phosphoric acid. Alternatively, when layer 2A is silicon nitride and layer 2B is silicon oxide, layer 2B may be etched using HF-based etching solution.
  • a common source region is formed at the bottom of the first opening, and a gate conductive layer (not shown) is formed in the recess.
  • the source region may be formed by ion implantation doping, and preferably further forming a metal silicide (not shown) on the surface.
  • a metal silicide such as NiSi 2-y , Ni 1-x Pt x Si 2-y , CoSi 2-y or Ni 1-x Co x Si 2-y , wherein x is greater than 0 and less than 1, and y is greater than or equal to 0. 1.
  • the gate conductive layer may be polysilicon, polysilicon, or metal, wherein the metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Metals such as Eu, Nd, Er, and La, or alloys of these metals, and nitrides of these metals, the gate conductive layer may be doped with elements such as C, F, N, O, B, P, and As to adjust Work function.
  • a barrier layer (not shown) of nitride is preferably formed between the gate insulating layer 4 and the gate conductive layer by a conventional method such as PVD, CVD, ALD, etc., and the barrier layer is made of M x N y , M x Si y N z M x Al y N z , M a Al x Si y N z , wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements.
  • the gate conductive layer may be a single layer structure or a multilayer stacked structure. Thereafter, a source-drain contact and an interlayer dielectric layer are formed to complete the contact interconnection of the device.
  • an amorphous thick film is deposited and then thinned and annealed to increase the grain size of the polycrystalline film, and an additional protective layer is used to avoid sidewall etching damage, and the polycrystalline channel layer can be effectively reduced.
  • the interface state and damage defects improve the reliability of the device.

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Abstract

一种半导体器件制造方法，包括步骤：在衬底上形成栅介质层和第一非晶沟道层；减薄第一非晶沟道层；刻蚀第一非晶沟道层、栅介质层直至暴露衬底；在第一非晶沟道层和衬底上形成第二非晶沟道层；退火，使得第一非晶沟道层和第二非晶沟道层转变为多晶沟道层；减薄多晶沟道层。依照本发明的半导体器件制造方法，沉积非晶厚膜再减薄退火以提高多晶薄膜的晶粒大小，并利用额外的保护层避免侧壁刻蚀损伤，能够有效地降低多晶沟道层的界面态、损伤缺陷，从而提高器件的可靠性。

Description

半导体器件制造方法 技术领域
本发明涉及一种半导体器件制造方法，特别是涉及一种三维存储器多晶沟道层的制造方法。
背景技术
为了改善存储器件的密度，业界已经广泛致力于研发减小二维布置的存储器单元的尺寸的方法。随着二维(2D)存储器件的存储器单元尺寸持续缩减，信号冲突和干扰会显著增大，以至于难以执行多电平单元(MLC)操作。为了克服2D存储器件的限制，业界已经研发了具有三维(3D)结构的存储器件，通过将存储器单元三维地布置在衬底之上来提高集成密度。
三维存储器由于其特殊的三维结构和复杂的工艺继承，无法使用单晶(硅)材料而只能用多晶(硅)材料作为沟道。其中，多晶(硅)材料的晶粒大小、晶粒边界的陷阱多少成为制约沟道导通能力的关键。高的界面态使得沟道的漏电较大，同时特性随温度的变化影响很大。
附图1至4示出了现有技术中三维存储器的制造方法。具体的，在衬底1上沉积不同介质材料2A/2B构成的堆叠以用作伪栅极，在多个伪栅极堆叠之间刻蚀开口填充绝缘材料形成存储器单元之间的绝缘隔离层3。隔离层3包围了多个有源区，刻蚀有源区内的伪栅极堆叠形成沟道沟槽，在沟槽中沉积栅介质4。在栅介质4上共形沉积第一非晶沟道层5，例如非晶硅，用作后续沟道层的成核层或界面层。层5的薄膜厚度很小，例如仅0.2～5nm，其薄膜质量较差，厚度不均匀、表面存在大量缺陷。随后如图2所示，刻蚀栅介质4直至露出衬底1，此刻蚀过程中，干法刻蚀气体除了刻蚀去除沟道沟槽底部的栅介质4之外，还会同时侧向腐蚀沟道层5，使其表面缺陷、损伤进一步增大。在图3所示沉积第二非晶沟道层7的过程中，第一非晶沟道层5表面的损伤缺陷会保留，形成了与第二非晶沟道层7之间的较差的非晶-非晶界面， 如图3中粗实线所示。因此，在后续图4所示退火将非晶转变为多晶沟道层的过程中，这种较高的界面态将影响多晶沟道层8/8’的特性。
发明内容
由上所述，本发明的目的在于克服上述技术困难，提出一种三维存储器制造方法，能够有效地降低多晶沟道层的界面态、损伤缺陷，有效提高器件的可靠性。
为此，本发明一方面提供了一种半导体器件制造方法，包括步骤：在衬底上形成栅介质层和第一非晶沟道层；减薄第一非晶沟道层；刻蚀第一非晶沟道层、栅介质层直至暴露衬底；在第一非晶沟道层和衬底上形成第二非晶沟道层；退火，使得第一非晶沟道层和第二非晶沟道层转变为多晶沟道层；减薄多晶沟道层。
其中，栅介质层包括选自隧穿层、存储层、阻挡层的多个子层。
其中，第一非晶沟道层选自非晶Si、非晶Ge。
其中，第二非晶沟道层选自非晶Ge、非晶SiGe、非晶SiC、非晶SiGeC、非晶C、III-V族或II-VI族非晶化合物半导体及其组合。
其中，第二非晶沟道层包含掺杂剂，退火激活了所述掺杂剂。
其中，减薄第一非晶沟道层之后、刻蚀第一非晶沟道层之前进一步包括，在第一非晶沟道层上形成保护层。
其中，保护层为单层或多层结构。
其中，刻蚀暴露衬底之后、形成第二非晶沟道层之前进一步包括，刻蚀去除保护层。
其中，在衬底上形成栅介质层和第一非晶沟道层包括，在衬底上形成伪栅极堆叠，刻蚀伪栅极堆叠形成垂直衬底的多个沟道沟槽，在每个沟道沟槽中依次沉积栅介质层和第一非晶沟道层。
其中，减薄多晶沟道层之后进一步包括，在多晶沟道层上下两端形成源漏区，去除伪栅极堆叠，在栅介质层侧面形成栅极导电层。
其中，退火温度为300～850℃，退火时间为1分钟～10小时。
依照本发明的半导体器件制造方法，沉积非晶厚膜再减薄退火以提高多晶薄膜的晶粒大小，并利用额外的保护层避免侧壁刻蚀损伤，能够有效地降低多晶沟道层的界面态、损伤缺陷，从而提高器件的可靠性。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1至图4为现有技术的三维存储器件制造方法的各个步骤的剖视图；
图5至图11为本发明的三维存储器件制造方法的各个步骤的剖视图；以及
图12为本发明的三维存储器件制造方法的示意性流程图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了能有效地提高器件可靠性的三维存储器制造方法。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
如图12和图5所示，在衬底1上的沟道沟槽中形成栅介质4和第一非晶沟道层5。
在衬底1上交替形成第一材料层2A与第二材料层2B的堆叠结构2。衬底1材质可以包括体硅(bulk Si)、体锗(bulk Ge)、绝缘体上硅(SOI)、绝缘体上锗(GeOI)或者是其他化合物半导体衬底，例如SiGe、SiC、GaN、GaAs、InP等等，以及这些物质的组合。为了与现有的IC制造工艺兼容，衬底1优选地为含硅材质的衬底，例如Si、SOI、SiGe、Si:C等。堆叠结构2的选自以下材料的组合并且至少包括一种绝缘介质：如氧化硅、氮化硅、非晶碳、类金刚石无定形碳(DLC)、氧化锗、氧化铝、等及其组合。第一材料层2A具有第一刻蚀选择性，第二材料层2B具有第二刻蚀选择性并且不同于第一刻蚀选择性(例如两种材料之间的刻蚀选择比大于5:1并优选大于10:1)。在本发明一个优选实施例中，叠层结构2A/2B均为非导电材料，层2A/层2B的组合例如氧化硅与氮化硅的组合、氧化硅与(未掺杂)多晶硅或非晶硅的组合、氧化硅或氮化硅与非晶碳的组合等等。在本发明另一优选实施例中，层2A与层2B在湿法腐蚀条件或者在氧等离子干法刻蚀条件下具有较大的刻蚀选择比(例如大于5:1)。层2A、层2B的沉积方法包括PECVD、LPCVD、HDPCVD、MOCVD、 MBE、ALD、热氧化、蒸发、溅射等各种工艺。在本发明一个最优实施例中，层2A为二氧化硅，层2B为氮化硅。
在阵列区域刻蚀(伪栅极)堆叠结构2直至暴露衬底1，形成伪栅极开孔(或称第一开孔，图5中位于中心位置)并在其中形成填充层3(填充层3下方的衬底将形成未来的共源区)。优选地，采用RIE或等离子干法刻蚀各向异性刻蚀层2A/层2B的堆叠结构2，形成露出衬底1以及衬底1上交替堆叠的层2A/层2B的侧壁的开孔(未示出)。刻蚀气体例如针对二氧化硅和氮化硅等材质的碳氟基刻蚀气体，并且通过增加碳氟比而在侧壁形成由含C聚合物形成的临时保护侧壁，最终获得较好的垂直侧壁。在本发明一个优选实施例中刻蚀气体优选C3F6、C4F8等含C量比较高的气体并进一步优选通过增加氧化性气体如O2、CO等控制侧壁形貌。平行于衬底1表面切得的孔槽的截面形状可以为矩形、方形、菱形、圆形、半圆形、椭圆形、三角形、五边形、五角形、六边形、八边形等等各种几何形状。填充层3沉积方法包括PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等，材质优选为与堆叠结构2的层2A、层2B均具有高选择性的材料，例如层3、层2A、层2B三者之间每两个之间的刻蚀选择比均大于等于5：1。在本发明一个优选实施例中，层2A为氧化硅，层2B为氮化硅，填充层3为非晶锗、非晶碳、DLC氮氧化硅等，反之亦然。
接着，与刻蚀形成第一开孔的工艺类似，RIE或等离子干法刻蚀各向异性刻蚀层2A/层2B的堆叠结构2，在第一开孔的周围形成多个露出衬底1以及衬底1上交替堆叠的层2A/层2B的侧壁的第二开孔(图5中暴露的开孔，位于图5中边缘位置)。刻蚀气体例如针对二氧化硅和氮化硅等材质的碳氟基刻蚀气体，并且通过增加碳氟比而在侧壁形成由含C聚合物形成的临时保护侧壁，最终获得较好的垂直侧壁。在本发明一个优选实施例中刻蚀气体优选C3F6、C4F8等含C量比较高的气体并进一步优选通过增加氧化性气体如O2、CO等控制侧壁形貌。在本发明一个优选实施例中(图5中并未示出)，用于暴露共源区的第一开孔的尺寸(例如直径)要大于或等于用于形成沟道区的第二开孔尺寸，例如两者尺寸(直径或者多边形的最大跨距的比值)比大于1.5并优选大于等于2。在本发明一个实施例中，每一个第一开孔周围具有六个第二开孔，以便于提高稍后侧向刻蚀层2B的效率以及均匀性。
此后，在第二开孔中形成栅介质层4。栅介质层4的沉积方法包括PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等。如 图中所示，层4优选地进一步包括多个子层，例如隧穿层、存储层、阻挡层。其中隧穿层包括SiO2或高k材料，其中高k材料包括但不限于氮化物(例如SiN、SiON、AlN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物，例如MgO、Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3)、氮氧化物(如HfSiON)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST))等，隧穿层可以是上述材料的单层结构或多层堆叠结构。存储层是具有电荷俘获能力的介质材料，例如SiN、HfOx、ZrOx、YOx等及其组合，同样可以是上述材料的单层结构或多层堆叠结构。阻挡层可以是氧化硅、氧化铝、氧化铪等介质材料的单层结构或多层堆叠结构。在本发明一个实施例中，栅介质层4例如是氧化硅、氮化硅、氧化硅组成的ONO结构。
接着，在栅介质层4上形成第一非晶沟道层5’。第一非晶沟道层5’的材料例如为非晶硅、非晶锗，沉积工艺包括LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD等。在本发明一个实施例中，第一非晶沟道层5’的沉积方式为局部填充第二开孔的侧壁而形成为具有空气隙的中空柱形。在本发明其他实施例中，选择第一非晶沟道层5’的沉积方式以完全或者局部填充第二开孔，形成实心柱、空心环、或者空心环内填充绝缘层(未示出)的核心-外壳结构。第一非晶沟道层5’的水平截面的形状与第二开孔类似并且优选地共形，可以为实心的矩形、方形、菱形、圆形、半圆形、椭圆形、三角形、五边形、五角形、六边形、八边形等等各种几何形状，或者为上述几何形状演化得到的空心的环状、桶状结构(并且其内部可以填充绝缘层)。
图5所示工艺与图1所示工艺不同之处在于，申请人通过严格的理论推导和严密的实验验证认识到，现有技术的第一非晶沟道层厚度太薄，沉积的薄膜质量较差、晶粒尺寸太小，后续退火形成的多晶薄膜缺陷态密度过大。因此，申请人特意设置增大了第一非晶沟道层5’的厚度(优选大于沉积工艺所得非晶材料的最大晶粒尺寸)，例如为5～30nm，大于图1、图6实际所需的第一非晶沟道层5的厚度。如此，可以使得在连续的沉积循环周期中，非晶材料在靠近栅介质层4的位置处具有足够的时间和空间融合为微晶、或者增大晶粒的平均尺寸，使得越靠近栅介质层4、非晶层5’的薄膜质量越好。
随后，如图12和图6所示，减薄第一非晶沟道层5’，使其成为第一非晶沟道层5。优选采用各向同性的刻蚀工艺，例如KOH、TMAH针对非晶硅，或者强酸、强氧化剂的混合溶液针对非晶锗，将第一非 晶沟道层5’的厚度从5～30nm减薄至第一非晶沟道层5的0.2～5nm，也即后续工艺所需的成核层或界面层的厚度(该厚度可以接近或小于图5所示沉积工艺所得非晶材料的最大晶粒尺寸)。在此过程中，由于靠近栅介质层4的薄膜质量明显更好，减薄之后留下的非晶沟道层5将具有比原来的厚膜5’更好的平均薄膜质量，这利于后续薄膜的生长。
任选地，如图12和图7所示，在减薄后的第一非晶沟道层5上形成保护层6。保护层6的材料选择为与层5具有较高刻蚀选择性(例如刻蚀选择比大于等于5:1、优选大于等于10:1、最佳大于等于15:1)的材料，例如氧化硅、氮化硅、氮氧化硅、非晶碳、DLC、ta-C等。保护层6可以是单层结构，或者多种材料构成的多层结构。保护层6的厚度优选地较薄，例如1～5nm。保护层6的沉积工艺优选共形沉积，例如LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD、磁控溅射等。
随后，如图12和图8所示，刻蚀保护层6、第一非晶沟道层5、栅介质层4直至暴露衬底1。刻蚀工艺优选各向异性的干法刻蚀，例如等离子体干法刻蚀、反应离子刻蚀(RIE)，刻蚀气体例如碳氟基气体，任选地进一步包括氧化性气体以调节刻蚀速率。调节刻蚀气体的配比，使得垂直方向刻蚀速率明显大于水平方向的侧向腐蚀速率，例如速度比大于等于5、优选大于等于10、最佳大于等于15。如此，由于保护层6对刻蚀气体的防护，第一非晶沟道层5的侧壁并未受到刻蚀气体的侵蚀，因此相对于现有技术的图2而言减小了界面缺陷，进一步提高了器件可靠性。暴露衬底1之后，采用各向同性的湿法工艺完全去除保护层6，暴露第一非晶沟道层5的表面。
接着，如图12和图9所示，在第一非晶沟道层5上形成第二非晶沟道层7。采用与第一非晶沟道层5类似的工艺，如LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD等，沉积第二非晶沟道层7。在本发明一个优选实施例中，层7与层5材料相同，例如均为非晶Si或非晶Ge。在本发明其他实施例中，层7的材料可以与层5的材料不同，例如层5为非晶Si时，层7为非晶Ge、非晶SiGe、非晶SiC、非晶SiGeC、非晶C，或者为III-V族或II-VI族非晶化合物半导体，或者层7为非晶硅与上述其他非晶材料的层叠。如此，后续多晶化之后所形成的沟道层将由于不同材料之间的晶格失配而具有应力，从而提高载流子迁移率、提高器件的驱动性能。在本发明的另外其他实施例中，层7可以沉积之后掺杂、或者原位掺杂，具有n 或p型杂质以形成不同类型的MOSFET。与图5所示工艺类似，在本发明优选实施例中，层7的厚度明显大于最终需要的非晶层厚度，从而利用晶粒大小随沉积膜厚的变化而提高界面处晶粒大小、减小界面处缺陷密度。例如，层7的厚度为5～100nm。由于图5、图6通过增大初始膜厚、增大界面晶粒尺寸，以及图7、图8采用保护层减小刻蚀损伤，因此图9中第一非晶层5与第二非晶层7之间的非晶材料界面质量较好(不再如图3、4所示采用粗实线表示，而是替代地采用虚线)，减小了界面态缺陷密度。
随后，如图12和图10所示，退火将第一非晶沟道层5、第二非晶沟道层7转变为多晶沟道层8/8’。当层5、7均为非晶Si时，层8/8’为多晶硅。当层5、7材质不同时，层8/8’可以为多晶Si与其他多晶材料的层叠或混合(退火时物质扩散或者反应合金化)，其他多晶材料包括多晶Ge、多晶SiGe、多晶SiC、多晶SiGeC，或者为III-V族或II-VI族多晶化合物半导体。多晶层8的厚度近似等于层7的厚度，例如也为5～100nm，或者具有小于10％、优选小于5％的厚度差。退火的同时，如果层7具有掺杂剂，则多晶化退火也同时激活了掺杂剂，使得沟道层具有一定的基底掺杂浓度。退火温度例如为300～850℃，通过低温工艺控制沟道的晶粒大小，减小漏电流。退火时间例如1分钟至10小时。
接着，如图12和图11所示，减薄多晶沟道层8/8’。例如采用各向同性刻蚀工艺，将多晶沟道层减薄至所需的例如5～20nm。此后可以进一步执行后续工艺，完成器件制造。
例如，在沟道层8内侧填充绝缘隔离层(未示出)，例如通过LPCVD、PECVD、HDPCVD等工艺形成氧化硅层，用于支撑、绝缘并隔离沟道层8。此后，在沟道层8顶部沉积漏区接触。优选地，采用与沟道层8材质相同或者相近(例如与Si相近的材质SiGe、SiC等，以便微调晶格常数而提高载流子迁移率，从而控制单元器件的驱动性能)的材质沉积在第二开口的顶部而形成存储器件单元晶体管的漏区，并且可以进一步形成硅化物(未示出)以降低接触电阻。
选择性刻蚀去除填充层3，重新露出第一开孔，利用第一开孔侧向刻蚀去除堆叠结构中的第二材料层(伪栅极层)2B。随后，采用各向同性干法刻蚀工艺，横向刻蚀去除层2B，在层2A之间留下了侧向凹槽。例如减小碳氟比以横向刻蚀氮化硅的层2B、或者采用热磷酸腐蚀氮化硅的层2B。备选地，当层2A为氮化硅、层2B为氧化硅时，可以采用HF基腐蚀液腐蚀层2B。
在第一开孔底部形成共源区，在凹槽中形成栅极导电层(未示出)。可以通过离子注入掺杂、以及优选地进一步在表面形成金属硅化物(未示出)而形成源区。金属硅化物例如NiSi2-y、Ni1-xPtxSi2-y、CoSi2-y或Ni1-xCoxSi2-y，其中x均大于0小于1，y均大于等于0小于1。栅极导电层可以是多晶硅、多晶锗硅、或金属，其中金属可包括Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er、La等金属单质、或这些金属的合金以及这些金属的氮化物，栅极导电层中还可掺杂有C、F、N、O、B、P、As等元素以调节功函数。栅极绝缘层4与栅极导电层之间还优选通过PVD、CVD、ALD等常规方法形成氮化物的阻挡层(未示出)，阻挡层材质为MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz，其中M为Ta、Ti、Hf、Zr、Mo、W或其它元素。同样地，栅极导电层可以是单层结构也可以是多层堆叠结构。此后形成源漏接触和层间介质层，完全器件的接触互联。
依照本发明的半导体器件制造方法，沉积非晶厚膜再减薄退火以提高多晶薄膜的晶粒大小，并利用额外的保护层避免侧壁刻蚀损伤，能够有效地降低多晶沟道层的界面态、损伤缺陷，从而提高器件的可靠性。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构或方法流程做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (10)

  1. 一种半导体器件制造方法，包括步骤：
    在衬底上形成栅介质层和第一非晶沟道层；
    减薄第一非晶沟道层；
    刻蚀第一非晶沟道层、栅介质层直至暴露衬底；
    在第一非晶沟道层和衬底上形成第二非晶沟道层；
    退火，使得第一非晶沟道层和第二非晶沟道层转变为多晶沟道层；
    减薄多晶沟道层。
  2. 如权利要求1的方法，其中，栅介质层包括选自隧穿层、存储层、阻挡层的多个子层。
  3. 如权利要求1的方法，其中，第一非晶沟道层选自非晶Si、非晶Ge。
  4. 如权利要求1的方法，其中，第二非晶沟道层选自非晶Ge、非晶SiGe、非晶SiC、非晶SiGeC、非晶C、III--V族或II--VI族非晶化合物半导体及其组合。
  5. 如权利要求1的方法，其中，第二非晶沟道层包含掺杂剂，退火激活了所述掺杂剂。
  6. 如权利要求1的方法，其中，减薄第一非晶沟道层之后、刻蚀第一非晶沟道层之前进一步包括，在第一非晶沟道层上形成保护层，保护层为单层或多层结构。
  7. 如权利要求6的方法，其中，刻蚀暴露衬底之后、形成第二非晶沟道层之前进一步包括，刻蚀去除保护层。
  8. 如权利要求1的方法，其中，在衬底上形成栅介质层和第一非晶沟道层包括，在衬底上形成伪栅极堆叠，刻蚀伪栅极堆叠形成垂直衬底的多个沟道沟槽，在每个沟道沟槽中依次沉积栅介质层和第一非晶沟道层。
  9. 如权利要求8的方法，其中，减薄多晶沟道层之后进一步包括，在多晶沟道层上下两端形成源漏区，去除伪栅极堆叠，在栅介质层侧面形成栅极导电层。
  10. 如权利要求1的方法，其中，退火温度为300～850℃，退火时间为1分钟～10小时。
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