WO2015161569A1 - 三维半导体器件及其制造方法 - Google Patents

三维半导体器件及其制造方法 Download PDF

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Publication number
WO2015161569A1
WO2015161569A1 PCT/CN2014/081926 CN2014081926W WO2015161569A1 WO 2015161569 A1 WO2015161569 A1 WO 2015161569A1 CN 2014081926 W CN2014081926 W CN 2014081926W WO 2015161569 A1 WO2015161569 A1 WO 2015161569A1
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layer
semiconductor device
gate
dimensional semiconductor
forming
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PCT/CN2014/081926
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English (en)
French (fr)
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霍宗亮
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中国科学院微电子研究所
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Priority to US15/306,179 priority Critical patent/US10373968B2/en
Publication of WO2015161569A1 publication Critical patent/WO2015161569A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7889—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and, in particular, to a three-dimensional semiconductor device and a method of fabricating the same. Background technique
  • a plurality of stacked structures may be first deposited on the substrate; and the multilayer stacked structure on the substrate is etched by an anisotropic etching process to form an edge a plurality of channel vias extending perpendicular to the surface of the substrate (either directly to the surface of the substrate or having a certain overetch); a material such as polysilicon is deposited in the via hole to form a columnar shape Channel; etching the multilayer stack structure along the WL direction to form a trench directly to the substrate, exposing a multilayer stack surrounding the columnar channel; wet removing a certain type of material in the stack (eg, hot phosphoric acid to remove nitrogen) Silicon, or HF to remove silicon oxide), leaving a laterally distributed protrusion structure around the columnar channel; depositing a gate dielectric layer (eg, a high-k dielectric material) and a gate conductive layer on the sidewalls
  • a gate dielectric layer eg, a high-k dielectric material
  • a portion of the protrusions of the stacked structure left on the side walls of the columnar channel form an isolation layer between the gate electrodes, and the remaining gate stack is sandwiched between the plurality of isolation layers as a control electrode.
  • the edge electric field of the gate causes a source/drain region to be induced on the columnar channel sidewall of, for example, a polysilicon material, thereby forming a gate array of a plurality of series-parallel MOSFETs to record the stored logic. status.
  • the resistance of the channel region composed of a material such as polysilicon rises remarkably, and the method and device structure in which a source/drain region is induced in the channel region by applying a voltage to the gate region is faced.
  • the problem of reduced induction efficiency, reduced inductive strength, and increased series resistance directly affects the read current and read speed of the memory array.
  • the potential at the location away from the memory cell read node may not be sufficient to induce source and drain regions in the channel region, thereby resulting in the entire The storage unit is invalid and the data cannot be read.
  • an aspect of the present invention provides a three-dimensional semiconductor device including a plurality of memory cells and a plurality of selection transistors, each of the plurality of memory cells including: a channel layer distributed in a direction perpendicular to a surface of the substrate a plurality of interlayer insulating layers and a plurality of gate stack structures alternately stacked along sidewalls of the channel layer; a plurality of floating gates located on sides of the plurality of interlayer insulating layers and the channel layer Between the walls; a drain at the top of the channel layer; and a source located in the substrate between adjacent two memory cells of the plurality of memory cells.
  • the material of the channel layer comprises single crystal silicon, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal germanium, SiGe, Si:C, SiGe:C, SiGe:H and combinations thereof.
  • the cross-sectional shape of the channel layer parallel to the surface of the substrate comprises a shape selected from the group consisting of a rectangle, a square, a diamond, a circle, a semicircle, an ellipse, a triangle, a pentagon, a pentagon, a hexagon, and an octagon.
  • the material of the plurality of interlayer insulating layers comprises silicon oxide, silicon nitride, amorphous carbon, diamond-like amorphous carbon (DLC), cerium oxide, aluminum oxide, aluminum nitride, and combinations thereof.
  • each of the plurality of gate stack structures comprises a gate dielectric layer and a gate conductive layer.
  • the gate dielectric layer further includes a tunneling layer, a storage layer, and a barrier layer.
  • the tunneling layer comprises a single layer or a multi-layer structure of SiO 2 , a high-k material, and a combination thereof; wherein the high-k material includes, but is not limited to, a nitride selected from the group consisting of SiN, AIN, TiN, and combinations thereof, Since MgO, Al2 ⁇ 3, Ta2 ⁇ 5, Ti ⁇ 2, ZnO, Zr02, Hf ⁇ 2, Ce ⁇ 2, ⁇ 2 ⁇ 3, La2 ⁇ 3 and combinations of metal oxides, nitrogen oxides, selected from PZT, BST and Its combination of perovskite phase oxides.
  • the storage layer comprises a single layer or a multi-layer structure of a dielectric material having a charge trapping ability selected from the group consisting of SiN, HfO, ZrO, and combinations thereof.
  • the barrier layer comprises a single layer or a multilayer structure of a dielectric material selected from the group consisting of silicon oxide, aluminum oxide, cerium oxide and combinations thereof.
  • the gate conductive layer comprises a single layer or a multilayer structure of a conductive material, the conductive material comprising polysilicon, polysilicon, or metal, or an alloy of the metal, or a nitride of the metal, wherein
  • the metal includes a metal selected from the group consisting of Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, lr, Eu, Nd, Er, La, and combinations thereof
  • a barrier layer of nitride is further included between the gate dielectric layer and the gate conductive layer, and the nitride is M x Ny, MxSiyN z , MxAlyN z , MaAlxSiyNz, where M is Ta, Ti, Hf , Zr, Mo, W, and combinations thereof, x, y are greater than or equal to 0 and less than or equal to 1.
  • the plurality of floating gates comprise a single layer or a multi-layer structure of a floating gate material layer;
  • the material of the floating gate material layer comprises a material selected from the group consisting of single crystal silicon, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal germanium, a SiGe, Si:C, SiGe:C, SiGe:H, and combinations thereof, or a conductive material selected from the group consisting of a metal, a nitride of the metal, a silicide of the metal, wherein the metal is selected from the group consisting of Al , Co, Ni, Cu, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, lr, Eu, Nd, Er, La, and combinations thereof, or include selected from the group consisting of SiN, HfO, ZrO, and A combination of dielectric materials having charge trapping capabilities.
  • each of the plurality of floating gates further has a floating gate isolation layer between the channel layer and/or the gate stack structure.
  • each of the plurality of sources includes a metal silicide.
  • the plurality of selection transistors include or do not include a floating gate.
  • Another aspect of the present invention provides a method of fabricating a three-dimensional semiconductor device, comprising the steps of: forming a stacked structure of a first material layer and a second material layer on a substrate of a memory cell region; etching the stacked structure to form a plurality of a hole groove; selectively etching a sidewall of the plurality of holes, forming a plurality of grooves in the first or second material layer; forming a plurality of floating gates and a plurality of grooves in the plurality of grooves Floating gate isolation layer.
  • first and second material layers are selected from one or a combination of the following materials: oxygen Silicon, silicon nitride, polycrystalline silicon, amorphous silicon, microcrystalline silicon, amorphous carbon, diamond-like amorphous carbon (DLC), cerium oxide, aluminum oxide, aluminum nitride, metals, metal alloys, metal nitrides.
  • the plurality of floating gates comprise a single layer or a multi-layer structure of a floating gate material layer;
  • the material of the floating gate material layer comprises a material selected from the group consisting of single crystal silicon, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal germanium, a SiGe, Si:C, SiGe:C, SiGe:H, and combinations thereof, or a conductive material selected from the group consisting of a metal, a nitride of the metal, a silicide of the metal, wherein the metal is selected from the group consisting of Al , Co, Ni, Cu, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, lr, Eu, Nd, Er, La, and combinations thereof, or include selected from the group consisting of SiN, HfO, ZrO, and A combination of dielectric materials having charge trapping capabilities.
  • the floating gate isolation layer is formed before and/or after forming the plurality of floating gates.
  • the floating gate isolation layer is formed by performing a deposition process on the plurality of floating gate sidewalls and/or the bottom, or performing an oxidation or nitridation process on the plurality of floating gates.
  • first and second material layers are insulating materials having different etching selectivity.
  • the plurality of floating gates further comprising: forming a plurality of channel layers in the plurality of holes; filling a plurality of drains on top of the plurality of channel layers; selectively etching to remove the unformed portions thereof a first or second material layer of the plurality of grooves or a plurality of floating gates, leaving a lateral trench; forming a gate stack structure of the gate dielectric layer and the gate conductive layer in the lateral trench; A source is formed in the substrate.
  • the gate dielectric layer further includes a tunneling layer, a storage layer, and a barrier layer.
  • the tunneling layer comprises a single layer or a multi-layer structure of SiO 2 , a high-k material, and a combination thereof; wherein the high-k material includes, but is not limited to, a nitride selected from the group consisting of SiN, AIN, TiN, and combinations thereof, selected from MgO, Metal oxides of Al2 ⁇ 3, Ta2 ⁇ 5, ⁇ 0 2 , ⁇ , Zr02, Hf ⁇ 2, Ce ⁇ 2, ⁇ 2 ⁇ 3, La2 ⁇ 3 and combinations thereof, nitrogen oxides, selected from PZT, BST and Its combination of perovskite phase oxides.
  • the storage layer comprises a single layer or a multi-layer structure of a dielectric material having a charge trapping ability selected from the group consisting of SiN, HfO, ZrO, and combinations thereof.
  • the barrier layer comprises a single layer or a multilayer structure of a dielectric material selected from the group consisting of silicon oxide, aluminum oxide, cerium oxide and combinations thereof.
  • the gate conductive layer comprises a single layer or a multilayer structure of a conductive material, the conductive material comprising polysilicon, polysilicon, or metal, or an alloy of the metal, or a nitride of the metal, wherein
  • the metal includes a group selected from the group consisting of Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, lr, Eu, Nd, Er, La, and the like Combined metal.
  • a barrier layer of nitride is further included between the gate dielectric layer and the gate conductive layer, and the nitride is M x Ny, MxSiyN z , M x AlyNz , MaAlxSiyNz , where M is Ta, Ti, Hf, Zr, Mo, W, and combinations thereof, x, y are all greater than or equal to 0 and less than or equal to 1.
  • one of the first and second material layers forming the groove is an insulating material, and the other one not forming the groove is a semiconductor or a conductive material.
  • Forming the floating gate further includes: forming a gate insulating layer on a sidewall of the first or second material layer where the recess is not formed, and forming a gate together with the first or second material layer not forming the recess a stacked structure; a plurality of channel layers are formed on the gate stack structure in the plurality of holes; a plurality of drains are formed on top of the plurality of channel layers; and a source is formed in the substrate .
  • the material of the channel layer comprises single crystal silicon, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal germanium, SiGe, Si:C, SiGe:C, SiGe:H and combinations thereof.
  • the cross-sectional shape of the channel layer parallel to the surface of the substrate comprises a shape selected from the group consisting of a rectangle, a square, a diamond, a circle, a semicircle, an ellipse, a triangle, a pentagon, a pentagon, a hexagon, and an octagon.
  • the floating gate is implanted in the vertical channel sidewall, and the opening and closing of the source-drain region induced on the vertical channel sidewall is controlled by the coupling between the gate electrode and the floating gate.
  • the induction efficiency and intensity of the source and drain regions are improved, and the source-drain resistance of the memory cell is reduced, thereby improving the read current and the read speed of the memory array.
  • FIG. 1 to 10 are cross-sectional views showing respective steps of a method of fabricating a three-dimensional semiconductor device in accordance with the present invention
  • Figure 1 is a partial enlarged view of the vicinity of the floating gate in Figure 9 or Figure 10;
  • Figure 12 is a schematic flow chart of a method of fabricating a three-dimensional semiconductor device in accordance with the present invention.
  • Figure 13 is a cross-sectional view showing another embodiment of a three-dimensional semiconductor device in accordance with the present invention.
  • detailed description DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 13 shows a cross-sectional view showing another embodiment of a three-dimensional semiconductor device in accordance with the present invention.
  • a stacked structure 2 of a first material layer 2A and a second material layer 2B is alternately formed on a substrate 1.
  • the material of the substrate 1 may include bulk silicon, bulk Ge, silicon-on-insulator (SOI), germanium on insulator (GeOI) or other compound semiconductor substrates such as SiGe, SiC, GaN, GaAs, InP, etc., and combinations of these substances.
  • the substrate 1 is preferably a silicon-containing substrate such as Si, SOU SiGe, Si:C or the like.
  • the stacked structure 2 is selected from the group consisting of the following materials and includes at least one insulating medium: silicon oxide, silicon nitride, polycrystalline silicon, amorphous silicon, amorphous carbon, diamond-like amorphous carbon (DLC), cerium oxide, aluminum oxide. , aluminum nitride, metal, etc. and combinations thereof.
  • the first material layer 2A has a first etch selectivity
  • the second material layer 2B has a second etch selectivity and is different from the first etch selectivity.
  • the stacked structures 2A/2B are all insulating materials, the combination of layers 2A/ 2B such as a combination of silicon oxide and silicon nitride, a combination of silicon oxide and polysilicon or amorphous silicon, silicon oxide Or a combination of silicon nitride and amorphous carbon, and the like.
  • layer 2A and layer 2B have a greater etch selectivity (e.g., greater than 5:1) under wet etching conditions or under oxygen plasma dry etching conditions.
  • the deposition method of the layer 2A and the layer 2B includes various processes such as PECVD, LPCVD, HDPCVD, MOCVD, MBE, ALD, thermal oxidation, evaporation, sputtering, and the like.
  • the stacked structure 2 is etched until the substrate 1 is exposed, forming a via 2TP vertically penetrating the stacked structure for defining the channel region.
  • the stacked structure 2 of the anisotropically etched layer 2A/layer 2B is etched by RI E or plasma dry etching to expose the sidewalls of the substrate 1 and the layer 2A/layer 2B alternately stacked on the substrate 1.
  • the process conditions of the anisotropic etch stack structure 2 are controlled such that the lateral etch rate is significantly smaller than the longitudinal etch rate to obtain a vertical deep hole having a high aspect ratio (for example, an aspect ratio AR of 10:1 or more) Or deep groove 2TP.
  • the cross-sectional shape of the hole 2 ⁇ cut parallel to the surface of the substrate 1 may be rectangular, square, diamond, circular, semicircular, elliptical, triangular, pentagonal, pentagonal, hexagonal, octagonal, etc. Various geometric shapes.
  • the second material layer 2 ⁇ in the stacked structure 2 is selectively etched (for example, etched back), and a plurality of grooves 2R are formed in the sidewalls of the hole 2 ⁇ for defining the floating gate region later.
  • Etching methods include wet etching and dry etching.
  • the wet etching solution that can be selected includes an HF-based etching solution for silicon oxide, a hot phosphoric acid etching solution for silicon nitride, and a strong alkali etching solution such as KOH or TMAH for polycrystalline silicon or amorphous silicon.
  • the recess 2R may have a recess relative to the layer 2A as shown in FIG. 3 (ie, the layer 2A has a protrusion 2AP with respect to the layer 2B), or may be etched differently from the layer 2A as shown in FIG. The resulting recess relative to layer 2B.
  • a floating gate material layer 3 is deposited in the bottom and sidewalls of the trench 2TP and in the sidewall of the recess 2R.
  • the material of the floating gate material layer 3 may include semiconductor materials such as single crystal silicon, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal germanium, SiGe, Si:C, SiGe:C, SiGe:H (in situ doping)
  • a conductive material such as a metal, a metal nitride, a metal silicide, wherein the metal may be selected from the group consisting of Al, Co, Ni, Cu, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr Further, W, lr, Eu, Nd, Er, La, etc.
  • the floating gate material layer 3 may also be a dielectric material such as SiN, HfO, ZrO or the like having a charge trapping ability.
  • the floating gate material layer 3 shown in FIG. 4 is a single layer structure, in other embodiments of the present invention, the layer 3 may be a combination of the above various materials, including a stack, a hybrid, an embedded, an alloy, etc., and the layer 3 may be The single layer structure may also be a multilayer stack structure.
  • the layer 3 deposition process includes PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, etc., and the deposition process first occurs in the recess 2R, completely filling the plurality of grooves 2R of the sidewall of the trench 2TP, and then continuing to fill the holes The bottom and side walls of the trough 2TP.
  • the deposition of layer 3 may fill the aperture 2TP completely or partially (as shown in Figure 4).
  • a floating gate 3F and an optional floating gate isolation layer 4 are formed on the sidewalls of the trenches 2''.
  • the floating gate material layer 3 is anisotropically etched until the protruding portion of the stacked structure 2, that is, the outermost side of the recess 2R (corresponding to the sidewall protruding portion 2 ⁇ of the layer 2 ⁇ in FIG. 3) is exposed, thereby leaving a floating gate in the recess 2R 3F.
  • the floating gate material layer 3 is made of a dielectric material having a charge trapping ability, it is not necessary to additionally form the floating gate isolation layer 4, and the outermost layer 3 of the recess 2R is used as the floating gate isolation layer 4.
  • the floating gate material layer 3 When the floating gate material layer 3 is made of other (preferably doped) semiconductor material or metal-based conductive material, it may be additionally floated by performing thermal oxidation, nitridation process on the floating gate 3F or various deposition processes as described above.
  • a floating gate isolation layer 4 is formed on the side of the gate 3F.
  • the floating gate isolation layer 4 may be a corresponding oxide or nitride of the floating gate material layer 3, such as silicon oxide, hafnium oxide, hafnium silicon oxide, titanium oxide, hafnium oxide, hafnium oxide, zirconium oxide, silicon nitride, and nitride. Hey and so on.
  • a channel layer 5 is formed on the surface of the floating gate 3F and the optional sidewall of the floating gate spacer 4 and the bottom of the trench 2TP.
  • the material of the channel layer 5 may include a single crystal Semiconductor materials such as silicon, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal germanium, SiGe, Si:C, SiGe:C, SiGe:H, and the deposition process is as described above.
  • the channel layer 5 is deposited in such a manner as to partially fill the sidewalls of the trench 2TP to form a hollow cylindrical shape having an air gap.
  • the deposition of the channel layer 5 is selected to completely or partially fill the trench 2TP to form a solid pillar, a hollow ring, or a hollow ring filled insulating layer (not shown).
  • the horizontal section of the channel layer 5 has a shape similar to that of the aperture 2TP and is preferably conformal, and may be a solid rectangle, a square, a diamond, a circle, a semicircle, an ellipse, a triangle, a pentagon, a pentagon, or a hexagon.
  • Various geometric shapes such as a shape, an octagon, and the like, or a hollow annular, barrel-like structure obtained by the above-described geometric shape (and the inside thereof may be filled with an insulating layer).
  • the top of the hole 2TP is further filled to form a drain region 5D.
  • a material which is the same as or similar to the material of the channel layer 5 for example, a material similar to Si, such as SiGe, SiC, etc., to fine-tune the lattice constant to improve carrier mobility, thereby controlling the driving performance of the unit device
  • the drain portion 5D of the memory device cell transistor is formed at the top of the hole 2TP.
  • the step shown in Fig. 7 can be omitted, and the portion of the channel layer 5 at the top of the device constitutes a corresponding drain region 5D.
  • the first material layer 2A is selectively etched away, and a plurality of lateral trenches 2TL are left between the first material layers 2B.
  • the trenches 2TL are in contact with the first material layer 2B, one side and
  • the channel layer 5 is in contact and the other side is exposed to the air, and at the same time the surface of the substrate 1 is exposed.
  • wet etching is used, for example, an HF-based etching solution for silicon oxide, a hot phosphoric acid etching solution for silicon nitride, and a strong alkali etching solution such as KOH or TMAH for polycrystalline silicon or amorphous silicon.
  • layer 2B is silicon oxide and layer 2A is silicon nitride.
  • the layer 2A of silicon nitride is removed by hot phosphoric acid as shown in FIG.
  • the various first wet etching solutions may be used to remove the corresponding first material layer 2A.
  • the layer 2A when the layer 2A is made of amorphous carbon or DLC, it can be removed by oxygen plasma dry etching.
  • the remaining first material layer 2B is later used as the interlayer insulating layer 2B between the gate stacks.
  • a gate stack structure 6 is formed in the trench 2TL, including a gate dielectric layer 6A and a gate conductive layer 6B.
  • the deposition method includes PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, and the like.
  • layer 6A preferably further includes a plurality of sub-layers, such as tunneling layer 6A1, memory layer 6B2, and barrier layer 6B3.
  • the tunneling layer 6A1 comprises Si ⁇ 2 or high-k materials, wherein the high-k materials include, but are not limited to, nitrides (eg, SiN, AIN, TiN), metal oxides (mainly sub-groups and lanthanide metal element oxides, eg MgO, ⁇ 2 ⁇ 3 , Ta2 ⁇ 5 , Ti ⁇ 2, ZnO, Zr ⁇ 2, Hf ⁇ 2, Ce ⁇ 2 Y 2 0 3 , La 2 0 3 ), nitrogen oxides (such as HfSiON), perovskite phase oxides (such as PbZr x Tii-x03 (PZT), BaxSn-xTiOs (BST)), etc.
  • tunneling layer 6A1 can It is a single layer structure or a multilayer stack structure of the above materials.
  • the memory layer 6B2 is a dielectric material having charge trapping ability, such as SiN, HfO, ZrO, etc., and combinations thereof, and may also be a single layer structure or a multilayer stack structure of the above materials.
  • the barrier layer 6B3 may be a single layer structure or a multilayer stack structure of a dielectric material such as silicon oxide, aluminum oxide, or cerium oxide.
  • the gate conductive layer 6B may be polysilicon, polysilicon, or metal, wherein the metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, lr a metal element such as Eu, Nd, Er, or La, or an alloy of these metals and a nitride of these metals, and the gate conductive layer 6B may be doped with elements such as C, F, N, 0, B, P, and As. To adjust the work function.
  • a barrier layer (not shown) of nitride is preferably formed between the gate dielectric layer 6A and the gate conductive layer 6B by a conventional method such as PVD, CVD, ALD, etc., and the barrier layer is made of M x Ny, MxSiyNz MxAlyNz M a Al x Si y N z , wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements.
  • layer 6B may be a single layer structure or a multilayer stack structure.
  • a common source region 1 S is formed in the substrate 1.
  • the source region 1 S may be formed by ion implantation doping, and preferably further forming a metal silicide (not shown) on the surface.
  • Metal silicides such as NiSi2- y , Nii-xPtxSi 2 -y CoSi2- y or
  • Nii-xCoxSi 2 - y wherein x is greater than 0 and less than 1, and y is greater than or equal to 0 and less than 1.
  • the finally obtained device includes a channel layer 5 which protrudes vertically from the substrate 1; the interlayer insulating layer 2A and the gate stack structure 6A/6B are alternately stacked along the channel layer 5; wherein the interlayer insulating Between layer 2A and the sidewalls of channel layer 5 there is a floating gate 3F and an optional floating gate isolation layer 4.
  • a control voltage is applied to the gate conductive layer 6B in the gate stack structure 6, the potential on the floating gate 3F will rise, and the source-drain region of the memory cell will be accelerated due to electrostatic coupling. form.
  • the induction efficiency and intensity of the source and drain regions are effectively improved, and the source-drain resistance of the memory cell is reduced, thereby improving the read current and the read speed of the memory array.
  • FIG. 1 A flowchart of a method of manufacturing a semiconductor device is shown in FIG. It is to be noted that the flowchart is only a preferred embodiment of the present invention, and the present invention can be implemented as long as it has a floating gate 3F between the gates 6B.
  • FIGS. 1 through 11 may include the steps of depositing a stacked structure of first and second material layers 2A/2B as shown in FIG. 1, wherein the first material layer For the material of the gate conductive layer 6B as described above, for example, doped semiconductor or conductive structure containing polysilicon, amorphous silicon, microcrystalline silicon, or metal for controlling the gate, and the other layer 2B constitutes interlayer insulation.
  • Layer as shown in Figure 2, etching defines the channel region;
  • the second material layer 2B is etched to form the recess 2R as shown in FIG. 3; similarly to FIG. 4, the floating gate 3F and the floating gate isolation layer 4 are formed as shown in FIG. 5, except that the floating gate isolation layer 4 is formed first.
  • the floating gate isolation layer 4 is deposited on the side so that the layer 4 completely wraps the floating gate 3F and the layer 2A, and the layer 4 serves as the gate insulating layer of the gate 2A at the same time; in addition, a layer similar to the layer 6A may be deposited on the sidewall of the gate 2A.
  • a gate insulating layer (not shown); then, as shown in FIGS. 6 and 7, the channel layer 5 is filled and a drain region 5D is formed; subsequently, as shown in FIG. 10, a source region 1 S is formed.
  • the resulting device structure is shown in Figure 13.
  • the floating gate material layer 3 when the floating gate material layer 3 is deposited in FIG. 4, not only the floating gate is formed in the device memory cell region as shown in the figure, but also the floating gate is formed in the (drive) selection cell region. In other words, the floating of the present invention
  • the gate structure 3F/4 will be located in the memory cell and/or select transistor ⁇ .
  • the floating gate is implanted in the vertical channel sidewall, and the opening of the source and drain regions induced on the vertical channel sidewall is controlled by the coupling between the gate electrode and the floating gate.
  • the induction efficiency and intensity of the source and drain regions are effectively improved, and the source-drain resistance of the memory cell is reduced, thereby improving the read current and the read speed of the memory array.

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Abstract

一种三维半导体器件，包括多个存储单元和多个选择晶体管，所述多个存储单元的每一个包括：沟道层，沿垂直于衬底表面的方向分布；多个层间绝缘层与多个栅极堆叠结构，沿着所述沟道层的侧壁交替层叠；多个浮栅，位于所述多个层间绝缘层与所述沟道层的侧壁之间；漏极，位于所述沟道层的顶部；以及源极，位于所述多个存储单元的相邻两个存储单元之间的所述衬底中。上述三维半导体器件及其制造方法，在垂直沟道侧壁植入浮栅，通过栅电极与浮栅之间的耦合控制垂直沟道侧壁上感应生成的源漏区的开启，有效提高了源漏区的感应效率和强度，减小了存储单元的源漏电阻，从而提高了存储阵列的读取电流和读取速度。

Description

说 明 书
三维半导体器件及其制造方法 技术领域
本发明涉及一种半导体器件及其制造方法，特别是涉及一种三维 半导体器件及其制造方法。 背景技术
为了改善存储器件的密度，业界已经广泛致力于研发减小二维布 置的存储器单元的尺寸的方法。 随着二维（ 2D )存储器件的存储器单 元尺寸持续縮减，信号冲突和干扰会显著增大，以至于难以执行多电 平单元（ MLC )操作。 为了克服 2D存储器件的限制，业界已经研发了 具有三维（ 3D )结构的存储器件，通过将存储器单元三维地布置在衬 底之上来提高集成密度。
具体地， 可以首先在衬底上沉积多层叠层结构（例如氧化物和氮 化物交替的多个 ONO结构） ；通过各向异性的刻蚀工艺对衬底上多层 叠层结构刻蚀而形成沿着存储器单元字线（ WL )延伸方向分布、 垂 直于衬底表面的多个沟道通孔（可直达衬底表面或者具有一定过刻 蚀 ) ；在沟道通孔中沉积多晶硅等材料形成柱状沟道；沿着 WL方向 刻蚀多层叠层结构形成直达衬底的沟槽，露出包围在柱状沟道周围的 多层叠层；湿法去除叠层中的某一类型材料（例如热磷酸去除氮化硅， 或 HF去除氧化硅 ) ，在柱状沟道周围留下横向分布的突起结构；在沟 槽中突起结构的侧壁沉积栅极介质层（例如高 k介质材料）以及栅极 导电层（例如 Ti、 W、 Cu、 Mo等 )形成栅极堆叠； 垂直各向异性刻 蚀去除突起侧平面之外的栅极堆叠， 直至露出突起侧面的栅极介质 层；刻蚀叠层结构形成源漏接触并完成后端制造工艺。 此时，叠层结 构在柱状沟道侧壁留下的一部分突起形成了栅电极之间的隔离层，而 留下的栅极堆叠夹设在多个隔离层之间作为控制电极。 当向栅极施加 电压时，栅极的边缘电场会使得例如多晶硅材料的柱状沟道侧壁上感 应形成源漏区，由此构成多个串并联的 MOSFET构成的门阵列而记录 所存储的逻辑状态。 随着器件尺寸进一步縮减至例如 22nm、 乃至 10nm节点， 多晶硅 等材料构成的沟道区电阻显著上升，通过在栅极施加电压以在沟道区 感应形成源漏区的方法和器件结构面临着感应效率降低、 感应强度减 小、 串联电阻上升的问题，直接影响了存储阵列的读取电流和读取速 度。 在极端情形下，远离存储单元读取节点（例如堆叠结构顶部的位 线 BL或者衬底中源区金属硅化物）处的电势可能不足以在沟道区感应 生成源漏区， 由此导致整个存储单元失效，数据无法读取。
发明内容
由上所述，本发明的目的在于克服上述技术困难，提出一种创新 性三维半导体器件及其制造方法。
为此，本发明一方面提供了一种三维半导体器件，包括多个存储 单元和多个选择晶体管，所述多个存储单元的每一个包括：沟道层， 沿垂直于衬底表面的方向分布 ； 多个层间绝缘层与多个栅极堆叠结 构，沿着所述沟道层的侧壁交替层叠；多个浮栅，位于所述多个层间 绝缘层与所述沟道层的侧壁之间 ；漏极，位于所述沟道层的顶部；以 及源极，位于所述多个存储单元的相邻两个存储单元之间的所述衬底 中。
其中 ，所述沟道层的材质包括单晶硅、 非晶硅、 多晶硅、 微晶 硅、 单晶锗、 SiGe、 Si:C、 SiGe:C、 SiGe:H及其组合。
其中 ，所述沟道层的平行于衬底表面的截面形状包括选自矩形、 方形、 菱形、 圆形、 半圆形、 椭圆形、 三角形、 五边形、 五角形、 六 边形、 八边形及其组合的几何形状，以及包括选自所述几何形状演化 得到的实心几何图形、 空心环状几何图形、 或者空心环状外围层与绝 缘层中心的组合图形。
其中 ，所述多个层间绝缘层的材质包括氧化硅、 氮化硅、 非晶 碳、 类金刚石无定形碳（ DLC )、 氧化锗、 氧化铝、 氮化铝及其组合。
其中 ，所述多个栅极堆叠结构的每一个包括栅极介质层与栅极 导电层。其中 ，所述栅极介质层进一步包括隧穿层、 存储层、 阻挡层。 其中 ，所述隧穿层包括 Si02、 高 k材料及其组合的单层或多层结构 ； 其中高 k材料包括但不限于选自 SiN、 AIN、 TiN及其组合的氮化物，选 自 MgO、 Al2〇3、 Ta2〇5、 Ti〇2、 ZnO、 Zr02、 Hf〇2、 Ce〇2、 Ύ2Ο3, La2〇3及其组合的金属氧化物，氮氧化物、 选自 PZT、 BST及其组合 的钙钛矿相氧化物。 其中 ，所述存储层包括具有电荷俘获能力的介质 材料的单层或多层结构，所述介质材料选自 SiN、 HfO、 ZrO及其组合。 其中 ，所述阻挡层的包括选自氧化硅、 氧化铝、 氧化铪及其组合的介 质材料的单层或多层结构。
其中 ，所述栅极导电层包括导电材料的单层或多层结构 ，所述 导电材料包括多晶硅、 多晶锗硅、 或金属、 或所述金属的合金、 或所 述金属的氮化物，其中所述金属包括选自 Co、 Ni、 Cu、 Al、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 lr、 Eu、 Nd、 Er、 La及其组 合的金属 o
其中 ，所述栅极介质层与所述栅极导电层之间还包括氮化物的 阻挡层，所述氮化物为 MxNy、 MxSiyNz、 MxAlyNz、 MaAlxSiyNz，其中 M为 Ta、 Ti、 Hf、 Zr、 Mo、 W及其组合， x、 y均大于等于 0且小于等 于 1。
其中 ，所述多个浮栅包括浮栅材料层的单层或多层结构 ；所述 浮栅材料层的材质包括选自单晶硅、 非晶硅、 多晶硅、 微晶硅、 单晶 锗、 SiGe、 Si:C、 SiGe:C、 SiGe:H及其组合的半导体材料，或者包 括选自金属、 所述金属的氮化物、 所述金属的硅化物的导电材料，其 中所述金属选自 Al、 Co、 Ni、 Cu、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 lr、 Eu、 Nd、 Er、 La及其组合，或者包括选自 SiN、 HfO、 ZrO及其组合的具有电荷俘获能力的介质材料。
其中 ，所述多个浮栅的每一个与所述沟道层和 /或所述栅极堆叠 结构之间还具有浮栅隔离层。
其中 ，所述多个源极的每一个顶部包含金属硅化物。
其中 ，所述多个选择晶体管包括或者不包括浮栅。
本发明另一方面提供了一种三维半导体器件的制造方法，包括 步骤：在存储单元区的衬底上形成第一材料层与第二材料层的堆叠结 构；刻蚀所述堆叠结构形成多个孔槽；选择性刻蚀在所述多个孔槽的 侧壁、 在所述第一或第二材料层中形成多个凹槽；在所述多个凹槽中 形成多个浮栅以及多个浮栅隔离层。
其中 ，所述第一、 第二材料层选自以下材料之一或其组合：氧 化硅、 氮化硅、 多晶硅、 非晶硅、 微晶硅、 非晶碳、 类金刚石无定形 碳（ DLC )、 氧化锗、 氧化铝、 氮化铝、 金属、 金属合金、 金属氮化 物。
其中 ，所述多个浮栅包括浮栅材料层的单层或多层结构 ；所述 浮栅材料层的材质包括选自单晶硅、 非晶硅、 多晶硅、 微晶硅、 单晶 锗、 SiGe、 Si:C、 SiGe:C、 SiGe:H及其组合的半导体材料，或者包 括选自金属、 所述金属的氮化物、 所述金属的硅化物的导电材料，其 中所述金属选自 Al、 Co、 Ni、 Cu、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 lr、 Eu、 Nd、 Er、 La及其组合，或者包括选自 SiN、 HfO、 ZrO及其组合的具有电荷俘获能力的介质材料。
其中 ，在形成所述多个浮栅之前和 /或之后形成所述浮栅隔离层。 其中 ，通过在所述多个浮栅侧壁和 /或底部执行沉积工艺、 或者对 所述多个浮栅执行氧化或氮化工艺形成所述浮栅隔离层。
其中 ，所述第一、 第二材料层为具有不同刻蚀选择性的绝缘材 质。 形成所述多个浮栅之后进一步包括：在所述多个孔槽中形成多个 沟道层；填充所述多个沟道层顶部形成多个漏极；选择性刻蚀去除其 中未形成所述多个凹槽或多个浮栅的第一或第二材料层，留下横向的 沟槽；在所述横向的沟槽中形成栅极介质层与栅极导电层的栅极堆叠 结构；在所述衬底中形成源极。
其中 ，所述栅极介质层进一步包括隧穿层、 存储层、 阻挡层。 其 中 ，所述隧穿层包括 Si02、 高 k材料及其组合的单层或多层结构 ；其 中高 k材料包括但不限于选自 SiN、 AIN、 TiN及其组合的氮化物，选自 MgO、 Al2〇3、 Ta2〇5、 \02, ΖηΟ、 Zr02、 Hf〇2、 Ce〇2、丫2〇3、 La2〇3 及其组合的金属氧化物，氮氧化物、 选自 PZT、 BST及其组合的钙钛 矿相氧化物。 其中 ，所述存储层包括具有电荷俘获能力的介质材料的 单层或多层结构，所述介质材料选自 SiN、 HfO、 ZrO及其组合。其中 ， 所述阻挡层的包括选自氧化硅、 氧化铝、 氧化铪及其组合的介质材料 的单层或多层结构。
其中 ，所述栅极导电层包括导电材料的单层或多层结构 ，所述导 电材料包括多晶硅、 多晶锗硅、 或金属、 或所述金属的合金、 或所述 金属的氮化物，其中所述金属包括选自 Co、 Ni、 Cu、 Al、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 lr、 Eu、 Nd、 Er、 La及其组 合的金属。 其中 ，所述栅极介质层与所述栅极导电层之间还包括氮化 物的阻挡层，所述氮化物为 MxNy、 MxSiyNz、 MxAlyNz、 MaAlxSiyNz , 其中 M为 Ta、 Ti、 Hf、 Zr、 Mo、 W及其组合， x、 y均大于等于 0且小 于等于 1。
其中 ，所述第一、 第二材料层中形成了凹槽的一个为绝缘材质 ， 未形成凹槽的另一个为半导体或导电材质。 形成所述浮栅之后进一步 包括：在未形成凹槽的第一或第二材料层的侧壁形成栅极绝缘层，与 所述未形成凹槽的第一或第二材料层共同构成栅极堆叠结构；在所述 多个孔槽中、 所述栅极堆叠结构上形成多个沟道层；在所述多个沟道 层顶部形成多个漏极；在所述衬底中形成源极。
其中 ，所述沟道层的材质包括单晶硅、 非晶硅、 多晶硅、 微晶 硅、 单晶锗、 SiGe、 Si:C、 SiGe:C、 SiGe:H及其组合。
其中 ，所述沟道层的平行于衬底表面的截面形状包括选自矩形、 方形、 菱形、 圆形、 半圆形、 椭圆形、 三角形、 五边形、 五角形、 六 边形、 八边形及其组合的几何形状，以及包括选自所述几何形状演化 得到的实心几何图形、 空心环状几何图形、 或者空心环状外围层与绝 缘层中心的组合图形。
依照本发明的三维半导体器件及其制造方法，在垂直沟道侧壁植 入浮栅，通过栅电极与浮栅之间的耦合控制垂直沟道侧壁上感应生成 的源漏区的开启 ，有效提高了源漏区的感应效率和强度，减小了存储 单元的源漏电阻，从而提高了存储阵列的读取电流和读取速度。 附图说明
以下参照附图来详细说明本发明的技术方案，其中 ：
图 1至图 10为依照本发明的三维半导体器件制造方法的各个步骤 的剖视图 ；
图 1 1为图 9或图 10中浮栅附近的局部放大示意图 ；
图 12为依照本发明的三维半导体器件制造方法的示意性流程图 ； 以及
图 13为依照本发明的三维半导体器件的另一实施例的剖视图。 具体实施方式 以下参照附图并结合示意性的实施例来详细说明本发明技术方 案的特征及其技术效果，公开了有效提高器件可靠性的半导体器件制 造方法。 需要指出的是，类似的附图标记表示类似的结构，本申请中 所用的术语" 第一" 、 " 第二" 、 " 上" 、 " 下" 等等可用于修饰各 种器件结构或制造工序。 这些修饰除非特别说明并非暗示所修饰器件 结构或制造工序的空间、 次序或层级关系。
如图 1所示，在衬底 1上交替形成第一材料层 2A与第二材料层 2B的堆叠结构 2。 衬底 1材质可以包括体硅（ bulk Si )、 体锗（ bulk Ge )、 绝缘体上硅（ SOI )、 绝缘体上锗（ GeOI )或者是其他化合 物半导体衬底，例如 SiGe、 SiC、 GaN、 GaAs、 InP等等，以及这些 物质的组合。 为了与现有的 IC制造工艺兼容，衬底 1优选地为含硅 材质的衬底，例如 Si、 SOU SiGe、 Si:C等。 堆叠结构 2的选自以下 材料的组合并且至少包括一种绝缘介质：如氧化硅、氮化硅、 多晶硅、 非晶硅、 非晶碳、 类金刚石无定形碳（ DLC )、 氧化锗、 氧化铝、 氮 化铝、 金属等及其组合。 第一材料层 2A具有第一刻蚀选择性，第二 材料层 2B具有第二刻蚀选择性并且不同于第一刻蚀选择性。 在本发 明一个优选实施例中 ，叠层结构 2A/2B均为绝缘材料，层 2A/层 2B 的组合例如氧化硅与氮化硅的组合、 氧化硅与多晶硅或非晶硅的组 合、 氧化硅或氮化硅与非晶碳的组合等等。 在本发明另一优选实施例 中 ，层 2A与层 2B在湿法腐蚀条件或者在氧等离子干法刻蚀条件下 具有较大的刻蚀选择比（例如大于 5: 1 )。 层 2A、 层 2B的沉积方法 包括 PECVD、 LPCVD、 HDPCVD、 MOCVD、 MBE、 ALD、 热氧化、 蒸发、 溅射等各种工艺。
如图 2所示，刻蚀堆叠结构 2直至露出衬底 1 ，形成垂直穿通堆 叠结构的孔槽 2TP以用于定义沟道区。 优选地，采用 RI E或等离子 干法刻蚀各向异性刻蚀层 2A/层 2B的堆叠结构 2，露出衬底 1以及衬 底 1上交替堆叠的层 2A/层 2B的侧壁。 更优选地，控制各向异性刻 蚀堆叠结构 2的工艺条件以使得横向刻蚀速度显著小于纵向刻蚀速度 而得到高深宽比（例如深宽比 AR大于等于 10: 1 )的垂直的深孔或深 槽 2TP。 平行于衬底 1表面切得的孔槽 2Τ的截面形状可以为矩形、 方形、 菱形、 圆形、 半圆形、 椭圆形、 三角形、 五边形、 五角形、 六 边形、 八边形等等各种几何形状。
如图 3所示，选择性刻蚀（例如回刻 )堆叠结构 2中的第二材料 层 2Β，在孔槽 2ΤΡ的侧壁形成多个凹槽 2R以用于稍后定义浮栅区。 刻蚀方法包括湿法腐蚀以及干法刻蚀。 根据层 2Α/层 2Β的材质不同 ， 可以选择的湿法腐蚀液包括，针对氧化硅材质的 HF基腐蚀液，针对 氮化硅材质的热磷酸腐蚀液，针对多晶硅或非晶硅材质的 KOH或 TMAH等强碱腐蚀液。另外还可以针对非晶碳、 DLC等碳基材质选用 氧等离子干法刻蚀，使得 0与 C反应形成气体而抽出。 凹槽 2R可以 如图 3所示为刻蚀层 2B得到相对于层 2A的凹入（也即层 2A相对于 层 2B具有突出部 2AP ) ， 也可以与图 3所示不同而刻蚀层 2A得到 的相对于层 2B的凹入。
如图 4所示，在孔槽 2TP底部和侧壁以及凹槽 2R侧壁中沉积浮 栅材料层 3。浮栅材料层 3的材质可以包括单晶硅、 非晶硅、 多晶硅、 微晶硅、 单晶锗、 SiGe、 Si:C、 SiGe:C、 SiGe:H等半导体材料（可 原位掺杂） ；也可以包括导电材料，例如金属、 金属氮化物、 金属硅 化物，其中所述金属可以选自 Al、 Co、 Ni、 Cu、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 lr、 Eu、 Nd、 Er、 La等及其组合；此外 浮栅材料层 3还可以是介质材料，例如 SiN、 HfO、 ZrO等具有电荷 俘获能力的介质材料。 虽然图 4所示浮栅材料层 3为单层结构，但是 在本发明其他实施例中层 3可以为上述各种材料的组合，组合形式包 括堆叠、 混杂、 嵌入、 合金等等，层 3可以是单层结构也可以是多层 堆叠结构。 层 3沉积工艺包括 PECVD、 HDPCVD、 MOCVD、 MBE、 ALD、 蒸发、 溅射等，沉积过程首先发生在凹槽 2R中 ，完全填充了 孔槽 2TP侧壁的多个凹槽 2R，然后继续填充孔槽 2TP的底部和侧壁。 在本发明一个实施例中 ，层 3的沉积可以完全或者部分（如图 4所示 ) 填充孔槽 2TP。
如图 5所示，在孔槽 2ΤΡ侧壁形成浮栅 3F以及任选的浮栅隔离 层 4。 各向异性刻蚀浮栅材料层 3直至露出堆叠结构 2的突出部分也 即凹槽 2R的最外侧（对应于图 3中层 2Β的侧壁突出部分 2ΒΡ ) ， 从而在凹槽 2R中留下浮栅 3F。当浮栅材料层 3材质为具有电荷俘获 能力的介质材料时，可以无需额外形成浮栅隔离层 4，而采用凹槽 2R 中层 3的最外侧作为浮栅隔离层 4。 当浮栅材料层 3材质为其他（优 选为掺杂的）半导体材料或者金属基导电材料时，可以通过对浮栅 3F 执行热氧化、 氮化工艺或者如上所述各种沉积工艺额外的在浮栅 3F 侧面形成浮栅隔离层 4。 浮栅隔离层 4材质可以为浮栅材料层 3的相 应氧化物或氮化物，例如氧化硅、 氧化锗、 氧化锗硅、 氧化钛、 氧化 钽、 氧化铪、 氧化锆以及氮化硅、 氮化锗等等。
如图 6所示，在浮栅 3F以及任选的浮栅隔离层 4侧壁以及孔槽 2TP底部、 衬底 1表面形成沟道层 5。 沟道层 5的材质可以包括单晶 硅、非晶硅、多晶硅、微晶硅、单晶锗、 SiGe、 Si:C、 SiGe:C、 SiGe:H 等半导体材料，沉积工艺如上所述。在本发明图 6所示一个实施例中 ， 沟道层 5的沉积方式为局部填充孔槽 2TP的侧壁而形成为具有空气隙 的中空柱形。 在本发明图中未示出的其他实施例中 ，选择沟道层 5的 沉积方式以完全或者局部填充孔槽 2TP，形成实心柱、 空心环、 或者 空心环内填充绝缘层（未示出）的核心 -外壳结构。沟道层 5的水平截 面的形状与孔槽 2TP类似并且优选地共形，可以为实心的矩形、方形、 菱形、 圆形、 半圆形、 椭圆形、 三角形、 五边形、 五角形、 六边形、 八边形等等各种几何形状，或者为上述几何形状演化得到的空心的环 状、 桶状结构（并且其内部可以填充绝缘层）。
如图 7所示，进一步填充孔槽 2TP顶部形成漏区 5D。 优选地， 采用与沟道层 5材质相同或者相近（例如与 Si相近的材质 SiGe、 SiC 等，以便微调晶格常数而提高载流子迁移率，从而控制单元器件的驱 动性能）的材质沉积在孔槽 2TP的顶部而形成存储器件单元晶体管的 漏区 5D。 自然，如果与图 6所示不同 ，沟道层 5为完全填充的实心 结构，则图 7所示的步骤可以省略，沟道层 5在整个器件顶部的部分 则构成相应的漏区 5D。
如图 8所示，选择性刻蚀去除第一材料层 2A，在第一材料层 2B 之间留下多个横向的沟槽 2TL，沟槽 2TL上下与第一材料层 2B接触， 一个侧面与沟道层 5接触而另一个侧面则暴露在空气中 ，并且同时露 出了衬底 1表面。 优选地，采用湿法腐蚀，例如针对氧化硅材质的 HF基腐蚀液，针对氮化硅材质的热磷酸腐蚀液，针对多晶硅或非晶 硅材质的 KOH或 TMAH等强碱腐蚀液。 在本发明一个实施例中 ，层 2B是氧化硅、层 2A是氮化硅，如图 8所示步骤采用热磷酸去除氮化 硅的层 2A。 此外，在其他实施例中 ， 也可以采用上述各种湿法腐蚀 液去除相应的第一材料层 2A。 进一步地，在本发明其他实施例中 ， 当层 2A是非晶碳、 DLC材质时， 可以采用氧等离子干法刻蚀去除。 留下的第一材料层 2B稍后用作栅极堆叠之间的层间绝缘层 2B。
如图 9所示，在沟槽 2TL中形成栅极堆叠结构 6，包括栅极介质 层 6A与栅极导电层 6B。沉积方法包括 PECVD、HDPCVD、MOCVD、 MBE、 ALD、 蒸发、 溅射等。 如图 1 1所示，层 6A优选地进一步包 括多个子层，例如隧穿层 6A1、 存储层 6B2、 阻挡层 6B3。 其中隧穿 层 6A1包括 Si〇2或高 k材料，其中高 k材料包括但不限于氮化物（例 如 SiN、 AIN、 TiN )、 金属氧化物（主要为副族和斓系金属元素氧化 物，例如 MgO、 Αΐ2θ3、 Ta2〇5、 Ti〇2、 ZnO、 Zr〇2、 Hf〇2、 Ce〇2、 Y203、 La203 )、 氮氧化物（如 HfSiON )、 钙钛矿相氧化物（例如 PbZrxTii-x03 ( PZT )、 BaxSn-xTiOs ( BST ) )等，隧穿层 6A1可以 是上述材料的单层结构或多层堆叠结构。存储层 6B2是具有电荷俘获 能力的介质材料，例如 SiN、 HfO、 ZrO等及其组合， 同样可以是上 述材料的单层结构或多层堆叠结构。阻挡层 6B3可以是氧化硅、氧化 铝、 氧化铪等介质材料的单层结构或多层堆叠结构。 栅极导电层 6B 可以是多晶硅、 多晶锗硅、 或金属 ，其中金属可包括 Co、 Ni、 Cu、 Al、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 lr、 Eu、 Nd、 Er、 La等金属单质、 或这些金属的合金以及这些金属的氮化物，栅极 导电层 6B中还可掺杂有 C、 F、 N、 0、 B、 P、 As等元素以调节功 函数。栅极介质层 6A与栅极导电层 6B之间还优选通过 PVD、 CVD、 ALD等常规方法形成氮化物的阻挡层（未示出 )，阻挡层材质为 MxNy、 MxSiyNz MxAlyNz MaAlxSiyNz，其中 M为 Ta、 Ti、 Hf、 Zr、 Mo、 W或其它元素。 同样地，层 6B可以是单层结构也可以是多层堆叠结 构。
如图 10所示，在衬底 1 中形成共用的源区 1 S。 可以通过离子注 入掺杂、 以及优选地进一步在表面形成金属硅化物（未示出）而形成 源区 1 S。 金属硅化物例如 NiSi2-y、 Nii-xPtxSi2-y CoSi2-y或
Nii-xCoxSi2-y，其中 x均大于 0小于 1 ， y均大于等于 0小于 1。
最终获得的器件如图 10所示，包括沟道层 5，垂直地从衬底 1突 起；层间绝缘层 2A与栅极堆叠结构 6A/6B沿着沟道层 5交替层叠； 其中层间绝缘层 2A与沟道层 5侧壁之间具有浮栅 3F以及任选的浮 栅隔离层 4。 如图 1 1放大的局部图所示， 当向栅极堆叠结构 6中的 栅极导电层 6B施加控制电压时，浮栅 3F上的电势将上升，由于静电 耦合将加速存储单元源漏区的形成。 有效提高了源漏区的感应效率和 强度，减小了存储单元的源漏电阻，从而提高了存储阵列的读取电流 和读取速度。
半导体器件的制造方法的流程图如图 12所示。值得注意的是，该 流程图仅为本发明一个优选实施例， 而只要是在栅极 6B之间具有浮 栅 3F即可实施本发明。
例如 ， 图 1至图 1 1 中未示出的另一个本发明优选实施方式可以 包括以下步骤：如图 1所示沉积第一和第二材料层 2A/2B的堆叠结构， 其中第一材料层为如上所述的栅极导电层 6B的材质，例如包含多晶 硅、 非晶硅、 微晶硅、 或金属的掺杂半导体或导电结构以用于控制栅 极，另一层 2B则构成层间绝缘层；如图 2所示刻蚀定义沟道区；如 图 3所示回刻第二材料层 2B形成凹槽 2R；类似于图 4、 如图 5所示 形成浮栅 3F和浮栅隔离层 4，不同之处在于只是先形成浮栅隔离层 4 以覆盖凹槽 2R的底部和侧面、 也即同时覆盖了层 2A，然后在层 4之 上填充沉积浮栅材料层 3并刻蚀形成浮栅 3F； 随后更优选地继续在 浮栅 3F以及层 2A的侧面沉积浮栅隔离层 4，以使得层 4完全包裹浮 栅 3F和层 2A，层 4同时作为栅极 2A的栅极绝缘层 ；此外， 也可以 在栅极 2A侧壁沉积类似于层 6A的栅极绝缘层（未示出） ；接着如 图 6、 7所示，填充沟道层 5以及形成漏区 5D；后续如图 10所示， 形成源区 1 S。 最终得到的器件结构如图 13所示。
此外，还可以在图 4沉积浮栅材料层 3时，不仅在如图中所示器 件存储单元区形成浮栅，也同时在（驱动器）选择单元区中形成浮栅， 换言之，本发明的浮栅结构 3F/4将位于存储单元中和 /或选择晶体管 ψ。
° 依照本发明的三维半导体器件及其制造方法，在垂直沟道侧壁植 入浮栅，通过栅电极与浮栅之间的耦合控制垂直沟道侧壁上感应生成 的源漏区的开启 ，有效提高了源漏区的感应效率和强度，减小了存储 单元的源漏电阻，从而提高了存储阵列的读取电流和读取速度。
尽管已参照一个或多个示例性实施例说明本发明 ，本领域技术人 员可以知晓无需脱离本发明范围而对器件结构或方法流程做出各种 合适的改变和等价方式。 此外，由所公开的教导可做出许多可能适于 特定情形或材料的修改而不脱离本发明范围。 因此，本发明的目的不 在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施 例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所 有实施例。

Claims

权 利 要 求 书 顯 201404001(1725110420140116)
1 . 一种三维半导体器件，包括多个存储单元和多个选择晶体管，所 述多个存储单元的每一个包括：
沟道层，沿垂直于衬底表面的方向分布；
多个层间绝缘层与多个栅极堆叠结构 ，沿着所述沟道层的侧壁 交替层叠；
多个浮栅，位于所述多个层间绝缘层与所述沟道层的侧壁之间 ； 漏极，位于所述沟道层的顶部；以及
源极，位于所述多个存储单元的相邻两个存储单元之间的所述 衬底中。
2 . 如权利要求 1所述的三维半导体器件，其中 ，所述沟道层的平行 于衬底表面的截面形状包括选自矩形、 方形、 菱形、 圆形、 半圆 形、 椭圆形、 三角形、 五边形、 五角形、 六边形、 八边形及其组 合的几何形状，以及包括选自所述几何形状演化得到的实心几何 图形、空心环状几何图形、或者空心环状外围层与绝缘层中心的 组合图形。
3 . 如权利要求 1所述的三维半导体器件，其中 ，所述多个栅极堆叠 结构的每一个包括栅极介质层与栅极导电层。
4 . 如权利要求 3所述的三维半导体器件，其中 ，所述栅极介质层进 一步包括隧穿层、 存储层、 阻挡层。
5 . 如权利要求 3所述的三维半导体器件，其中 ，所述栅极介质层与 所述栅极导电层之间还包括氮化物的阻挡层。
6 . 如权利要求 1所述的三维半导体器件，其中 ，所述多个浮栅包括 浮栅材料层的单层或多层结构；所述浮栅材料层的材质包括半导 体材料，或者导电材料，或者包括具有电荷俘获能力的介质材料。
7 . 如权利要求 1所述的三维半导体器件，其中 ，所述多个浮栅的每 一个与所述沟道层和 /或所述栅极堆叠结构之间还具有浮栅隔离 层 o
8 . 如权利要求 1所述的三维半导体器件，其中 ，所述多个源极的每 一个顶部包含金属硅化物。
9 . 如权利要求 1所述的三维半导体器件，其中 ，所述多个选择晶体 管包括或者不包括浮栅。
10 . 一种三维半导体器件的制造方法，包括步骤：
在存储单元区的衬底上形成第一材料层与第二材料层的堆叠结 构；
刻蚀所述堆叠结构形成多个孔槽；
选择性刻蚀在所述多个孔槽的侧壁、在所述第一或第二材料层中 形成多个凹槽；
在所述多个凹槽中形成多个浮栅以及多个浮栅隔离层。
1 1 . 如权利要求 10所述的三维半导体器件制造方法，其中 ，所述多 个浮栅包括浮栅材料层的单层或多层结构；所述浮栅材料层的材 质包括半导体材料，或者包括导电材料，或者包括具有电荷俘获 能力的介质材料。
12 . 如权利要求 10所述的三维半导体器件制造方法，其中 ，在形成 所述多个浮栅之前和 /或之后形成所述浮栅隔离层。
13 . 如权利要求 10所述的三维半导体器件制造方法，其中 ，通过在 所述多个浮栅侧壁和 /或底部执行沉积工艺、 或者对所述多个浮 栅执行氧化或氮化工艺形成所述浮栅隔离层。
14 . 如权利要求 10所述的三维半导体器件制造方法，其中 ，所述第 一、 第二材料层为具有不同刻蚀选择性的绝缘材质。
15 . 如权利要求 14所述的三维半导体器件制造方法，形成所述多个 浮栅之后进一步包括：
在所述多个孔槽中形成多个沟道层；
填充所述多个沟道层顶部形成多个漏极；
选择性刻蚀去除其中未形成所述多个凹槽或多个浮栅的第一或 第二材料层，留下横向的沟槽；
在所述横向的沟槽中形成栅极介质层与栅极导电层的栅极堆叠 结构；
在所述衬底中形成源极。
16 . 如权利要求 15所述的三维半导体器件制造方法，其中 ，所述栅 极介质层进一步包括隧穿层、 存储层、 阻挡层。
17 . 如权利要求 15所述的三维半导体器件制造方法，其中 ，所述栅 极介质层与所述栅极导电层之间还包括氮化物的阻挡层。
18 . 如权利要求 10所述的三维半导体器件制造方法，其中 ，所述第 一、第二材料层中形成了凹槽的一个为绝缘材质，未形成凹槽的 另一个为半导体或导电材质。
19 . 如权利要求 18所述的三维半导体器件制造方法，形成所述浮栅 之后进一步包括：
在未形成凹槽的第一或第二材料层的侧壁形成栅极绝缘层 ，与 所述未形成凹槽的第一或第二材料层共同构成栅极堆叠结构；
在所述多个孔槽中、 所述栅极堆叠结构上形成多个沟道层； 在所述多个沟道层顶部形成多个漏极；
在所述衬底中形成源极。
20. 如权利要求 15或 19所述的三维半导体器件制造方法，其中 ，所述 沟道层的平行于衬底表面的截面形状包括选自矩形、方形、菱形、 圆形、 半圆形、 椭圆形、 三角形、 五边形、 五角形、 六边形、 八 边形及其组合的几何形状，以及包括选自所述几何形状演化得到 的实心几何图形、 空心环状几何图形、 或者空心环状外围层与绝
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