WO2016023260A1 - 三维存储器及其制造方法 - Google Patents

三维存储器及其制造方法 Download PDF

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Publication number
WO2016023260A1
WO2016023260A1 PCT/CN2014/087478 CN2014087478W WO2016023260A1 WO 2016023260 A1 WO2016023260 A1 WO 2016023260A1 CN 2014087478 W CN2014087478 W CN 2014087478W WO 2016023260 A1 WO2016023260 A1 WO 2016023260A1
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layer
forming
etching
opening
openings
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PCT/CN2014/087478
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English (en)
French (fr)
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霍宗亮
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中国科学院微电子研究所
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Priority to US15/503,833 priority Critical patent/US10475807B2/en
Publication of WO2016023260A1 publication Critical patent/WO2016023260A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and, in particular, to a high-density three-dimensional memory and a method of fabricating the same.
  • a commonly used 3D memory device structure in the industry is a tera-cell array transistor (TCAT).
  • TCAT tera-cell array transistor
  • a plurality of stacked structures eg, a plurality of ONO structures in which oxide and nitride are alternated
  • the multilayer laminated structure on the substrate is etched by an anisotropic etching process to form an edge a plurality of channel vias extending perpendicular to the surface of the substrate (either directly to the surface of the substrate or having a certain overetch); a material such as polysilicon is deposited in the via of the memory to form a columnar shape Channel; etching the multilayer stack structure along the WL direction to form a trench directly to the substrate, exposing the multilayer stack surrounding the columnar channel; for etching selectivity between adjacent layers in the stack, selective etching Corrosion selects a relatively high etching solution to wet the second type of material in the stack, leaving a laterally distributed protrusion structure of the first type
  • the fringe electric field of the gate causes a source/drain region to be induced on the columnar channel sidewall of, for example, a polysilicon material, thereby forming a gate array of a plurality of series-parallel flash memory cells to record the stored Logic state.
  • a padded polysilicon material is deposited on top of the columnar channel to form a drain region, and a metal contact plug electrically connected to the drain region is formed to further electrically connect to the upper bit-line (BL).
  • BL bit-line
  • a common source region with metal silicide contacts is formed in the substrate between the plurality of vertical cylindrical channels. In the cell-on state, current flows from the common source region to the surrounding vertical channel region, and passes through a plurality of sources induced in the vertical channel under the control voltage applied by the control gate (connected to the word line WL). The drain region further flows to the upper bit line through the drain region at the top of the channel.
  • the TCAT device structure has a bulk erase (changing the control gate can cause a change in potential between the source and drain regions of the sensing source and the floating gate), and the metal gate can be used to control the work function of the metal material to adjust the transistor. Threshold) and many other advantages.
  • the top select transistor USG, located above the memory transistor cell string
  • the remaining gate and word line (WL) connections are shared by the etched holes and are gated.
  • the etch removes the dummy gate to form a gate opening and deposits a metal gate.
  • This very high aspect ratio (AR, for example, typically greater than 40:1 or even 100:1) deep contact vias and gate openings will result from the deposition of a multilayer film.
  • the width is increased, which in turn makes the memory cell density of TCAT not effectively reduced further.
  • the etching of deep trenches and the etching of deep-hole trenches are etching of the multilayer stack, and the process complexity is high. The difference in shape between deep holes and deep trenches also changes the etching process.
  • a bit cost reduction (BiCS) NAND structure which increases the integration density by three-dimensionally arranging memory cells on a substrate, wherein the channel layer is vertically erected at On the substrate, the gate is divided into a lower selection gate, a middle control gate, and an upper selection gate, and the crosstalk between the signals is reduced by distributing the gate signals in the three sets of gate electrodes.
  • BiCS bit cost reduction
  • the upper and lower devices are used as selection transistors - vertical MOSFETs with large gate height/thickness
  • the gate dielectric layer is a conventional single-layer high-k material
  • the middle device is used as a memory cell string
  • the gate height / The thickness is small
  • the gate dielectric layer is a stacked structure of a tunneling layer, a storage layer, and a barrier layer.
  • the specific fabrication process of the BiCS-based NAND structure device generally includes depositing a lower selection gate electrode layer on the silicon substrate, etching the lower selection gate electrode layer to form a hole directly into the substrate to deposit the lower portion of the channel layer and the lower gate Leading contact of the electrode, depositing a control gate layer thereon, etching control gate layer forming an intermediate channel region as a memory cell region and an extraction contact of the middle layer control gate electrode, etching to form a control gate, according to word lines, bits Line division requires dividing the entire device into multiple regions, depositing upper layer selection on top The gate is etched and deposited to form an upper channel and an upper layer is brought out to contact, and then the device is fabricated by a subsequent process.
  • all of the lower gate electrodes may be flat, which avoids the deep trench and deep hole contact process with respect to TCAT, and is advantageous for increasing the memory density.
  • the most critical etching step is only the lithography for the intermediate layer memory channel region and the extraction contact, which directly determines the integration of the entire device and the signal anti-interference ability.
  • the BiCS structure utilizes the control gate threshold by stacking the memory array and the selection transistor, and the complicated process of avoiding the contact hole or gate opening of the excessive aspect ratio by layer-connecting the gate, it can only pass The gate-induced drain leakage current (GIDL) of the polysilicon material is erased, and the body erase cannot be performed, and the read/write efficiency is low.
  • GIDL gate-induced drain leakage current
  • an aspect of the present invention provides a three-dimensional memory manufacturing method including the steps of: forming a stacked structure of a first material layer and a second material layer on a substrate; etching the stacked structure to expose the substrate to form a plurality of vertical a first opening; forming a filling layer in each of the first openings; etching the stacked structure around each of the first openings to expose the substrate to form a plurality of vertical second openings; Forming a vertical channel layer and a drain in the hole; selectively etching to remove the filling layer, re-exposing the first opening; laterally etching or completely removing the second material layer, leaving a groove; forming in the groove a gate stack structure; a common source is formed on and/or in the substrate at the bottom of each first opening.
  • the first material layer, the second material layer and the filling layer have different etching selectivitys.
  • the first material layer, the second material layer, and the filling layer material are selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon, amorphous germanium, DLC, amorphous carbon, and combinations thereof.
  • the size of the first opening is greater than or equal to the size of the second opening.
  • the channel layer is a hollow structure including an insulator at the center.
  • the forming the common source further includes forming an insulating layer on each of the sidewalls of the first opening, and forming a contact layer contacting the common source region on the sidewall of the insulating layer and the bottom of each of the first openings.
  • the method further comprises: controlling the deposition process parameters or etching back such that the top surface of the contact layer is lower than the bottom surface of the topmost layer of the gate stack structure, and backfilling with an insulating layer.
  • the forming the contact layer further includes: etching and removing a portion of the first material layer, the gate stack structure to form a third opening, and depositing an insulating material in the third opening to form an isolation insulation from the topmost layer of the gate stack structure Area.
  • the forming the isolation insulating region further includes forming an interlayer dielectric layer on the device, and etching the interlayer dielectric layer to form a fourth opening until the contact layer is exposed, and the filling metal forms a common source line lead.
  • the method further includes etching the stacked structure to form a step in the word line contact region around the array region, and sequentially exposing the ends of each of the first material layer and the second material layer.
  • Another aspect of the present invention provides a three-dimensional memory manufacturing method comprising the steps of: forming a stacked structure of a first material layer and a second material layer on a substrate; etching the stacked structure to expose the substrate while forming a plurality of vertical An opening and a plurality of second openings around each of the first openings; forming a filling layer in each of the first openings; forming a vertical channel layer and a drain in each of the second openings; Selectively etching to remove the filling layer, re-exposing the first opening; laterally etching part or completely removing the second material layer, leaving a groove; forming a gate stack structure in the groove; at each first opening A common source is formed on and/or in the bottom substrate.
  • Yet another aspect of the present invention provides a three-dimensional memory comprising: a plurality of common source leads vertically distributed on a substrate, in contact with a common source in and/or on the substrate; around each common source lead a plurality of channel layers distributed perpendicular to the substrate, each channel layer having a drain at the top; a plurality of insulating isolation layers on each of the channel layer sidewalls and a plurality of gates between each of the insulating isolation layers Extremely stacked structure.
  • the word line deep groove of the TCAT three-dimensional device is replaced by deep hole etching to perform the same function, the integration density is improved, the etching process of the stacked structure is simplified, and the metal gate control performance is retained.
  • 1 to 10 are cross-sectional and/or top views of respective steps of a method of fabricating a three-dimensional semiconductor memory device in accordance with the present invention.
  • a stacked structure 2 of a first material layer 2A and a second material layer 2B is alternately formed on a substrate 1.
  • the material of the substrate 1 may include bulk silicon, bulk Ge, silicon-on-insulator (SOI), germanium on insulator (GeOI) or other compound semiconductor substrates such as SiGe, SiC, GaN, GaAs, InP, etc., and combinations of these substances.
  • substrate 1 is preferably a silicon-containing substrate such as Si, SOI, SiGe, Si:C, and the like.
  • the stack structure 2 is selected from the group consisting of the following materials and includes at least one insulating medium such as silicon oxide, silicon nitride, amorphous carbon, diamond-like amorphous carbon (DLC), cerium oxide, aluminum oxide, and the like, and combinations thereof.
  • the first material layer 2A has a first etch selectivity
  • the second material layer 2B has a second etch selectivity and is different from the first etch selectivity (eg, an etch selectivity ratio between the two materials is greater than 5:1 And preferably greater than 10:1).
  • the stacked structures 2A/2B are all non-conductive materials, the combination of layers 2A/ 2B such as a combination of silicon oxide and silicon nitride, silicon oxide and (undoped) polycrystalline silicon or amorphous A combination of silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, and the like.
  • layer 2A and layer 2B have a greater etch selectivity (e.g., greater than 5:1) under wet etching conditions or under oxygen plasma dry etching conditions.
  • the deposition methods of the layers 2A and 2B include various processes such as PECVD, LPCVD, HDPCVD, MOCVD, MBE, ALD, thermal oxidation, evaporation, sputtering, and the like.
  • layer 2A is silicon dioxide and layer 2B is silicon nitride.
  • the lowest layer 2B will be used for the formation of the bottommost select gate electrode in the future, hence the label LSG
  • the topmost layer 2B will be used for the formation of the topmost select gate electrode in the future, hence the USG
  • the stacked structure 2A/2B is etched, and the side ends of a portion of the layers 2A/2B are sequentially exposed to form a stepped word line pad region (WL).
  • WLPR stepped word line pad region
  • AR the central area
  • layer 2A above the top USG is sequentially exposed: USG
  • the steps of Figures 3 to 10 below will be made for the central array area in Figure 2, in other words each top view shows only a portion of the area 2A:AR.
  • a dummy gate (SiN) as a layer 2B is exposed by performing deep trench etching, and then removed.
  • the dummy gate of layer 2B completes the gate stack dielectric layer and metal electrode deposition steps to complete the preparation of the memory cell; then the sidewall formation, implantation and silicidation are used to complete the formation of the common source region; then the deep trench oxide fill, CMP, The source region CSL contact hole is etched and filled, and the metal line is connected to complete the CSL connection.
  • such post-formed deep trenches are often difficult to achieve both aspect ratio and metal fill rate, which tends to cause device failure.
  • an embodiment of the present invention does not use deep trenches and uses deep hole etching as shown in FIG. 3, such that the process is the same as the trench formation process, after completion of the fabrication of the memory cell, directly through the sidewall spacers, silicidation, and The deep hole filling of the metal completes the contact of the common source region, and then the leads complete the CSL connection.
  • the multilayer dielectric etching process is simple, the density of the memory array is increased, and the contact hole extraction process in the common source region is simpler.
  • the original silicon dioxide fills the deep trench and planarizes, etches the contact hole, and fills the contact hole. The way is directly replaced by deep hole sidewall insulation and metal contact hole filling
  • the stacked structure 2 is etched in the array region until the substrate 1 is exposed (this region will form a future common source region), forming a first opening as a dummy gate opening.
  • a hole (not shown) and a filling layer 3 are formed in the dummy gate opening.
  • the first opening will serve as an inlet region for forming the common source region 1S and laterally etching the partial layer 2B.
  • the stacked structure 2 of the anisotropically etched layer 2A/layer 2B is etched by RIE or plasma dry etching to form a first exposed sidewall of the substrate 1 and the layer 2A/layer 2B alternately stacked on the substrate 1. Opening (not shown).
  • Etching gas for example, a fluorocarbon-based etching gas for materials such as silicon dioxide and silicon nitride, and forming a temporary protective sidewall formed of a C-containing polymer on the sidewall by increasing a carbon-to-fluorine ratio, and finally obtaining a better Vertical side walls.
  • the etching gas is preferably a gas having a relatively high C content such as C 3 F 6 or C 4 F 8 and further preferably controls the sidewall morphology by adding an oxidizing gas such as O 2 , CO or the like.
  • the cross-sectional shape of the hole cut parallel to the surface of the substrate 1 may be rectangular, square, diamond, circular, semi-circular, elliptical, triangular, pentagonal, pentagon, hexagonal, octagonal, etc. Geometric shapes.
  • the filling layer 3 deposition method includes PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, etc.
  • the material is preferably a material having high selectivity to both the layer 2A and the layer 2B of the stacked structure 2, such as layer 3, layer 2A,
  • the etching selectivity ratio between each of the two layers 2B is greater than or equal to 5:1.
  • layer 2A is silicon oxide
  • layer 2B is silicon nitride
  • the filling layer is amorphous silicon, amorphous germanium, amorphous carbon, DLC, etc., and vice versa.
  • a plurality of second openings are formed around each of the first openings and a vertical channel region 4 is formed. Similar to the process of etching to form the first opening, RIE or plasma dry etching the stacked structure 2 of the anisotropically etched layer 2A/layer 2B, forming a plurality of exposed substrates 1 and lining around the first opening A second opening (not shown) of the side walls of layer 2A/layer 2B alternately stacked on the bottom 1.
  • Etching gas for example, a fluorocarbon-based etching gas for materials such as silicon dioxide and silicon nitride, and forming a temporary protective sidewall formed of a C-containing polymer on the sidewall by increasing a carbon-to-fluorine ratio, and finally obtaining a better Vertical side walls.
  • the etching gas is preferably a gas having a relatively high C content such as C 3 F 6 or C 4 F 8 and further preferably controls the sidewall morphology by adding an oxidizing gas such as O 2 , CO or the like.
  • the size (e.g., diameter) of the first opening for exposing the common source region is greater than or equal to the second opening size used to form the channel region, such as both dimensions (diameter or polygon).
  • the ratio of the maximum span ratio is greater than 1..5 and preferably greater than or equal to 2.
  • the number of second openings that may be present around each of the first openings is 2, 3, 4, 5, 6, 7, 8, 9, or even more.
  • the material of the channel layer 4 may include a semiconductor material such as single crystal silicon, single crystal germanium, SiGe, Si:C, SiGe:C, SiGe:H, and the deposition process includes LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, and the like.
  • the channel layer 4 is deposited in such a manner as to partially fill the sidewalls of the second opening to form a hollow cylindrical shape having an air gap.
  • the deposition mode of the channel layer 4 is selected to completely or partially fill the second opening to form a solid column, a hollow ring, or a core-shell structure filled with an insulating layer (not shown) in the hollow ring. .
  • the shape of the horizontal section of the channel layer 4 is similar to and preferably conformal to the second opening, and may be a solid rectangle, a square, a diamond, a circle, a semicircle, an ellipse, a triangle, a pentagon, a pentagon, or a Various geometric shapes such as triangles, octagons, etc., or for the above geometric shapes
  • the resulting hollow annular, barrel-like structure (and the interior of which can be filled with an insulating layer).
  • the insulating layer 4B may be further filled inside the channel layer 4A, for example, a layer 4B of a silicon oxide material is formed by a process such as LPCVD, PECVD, HDPCVD, etc., for supporting and insulating.
  • the channel layer 4A is isolated.
  • a drain contact 4D is deposited on top of the channel layer 4.
  • a material which is the same as or similar to the material of the channel layer 4 for example, a material similar to Si, such as SiGe, SiC, etc., in order to fine-tune the lattice constant to improve carrier mobility, thereby controlling the driving performance of the cell device
  • the drain portion 4D of the memory device cell transistor is formed at the top of the second opening, and a silicide (not shown) may be further formed to lower the contact resistance.
  • the filling layer 3 is selectively etched, the first opening 2T is exposed again, and the second material layer in the stacked structure is removed by lateral etching using the first opening 2T (pseudo gate) Layer) 2B.
  • a vertical anisotropic etching process such as RIE or plasma dry etching (to further increase the carbon-to-fluorine ratio to etch amorphous silicon, amorphous germanium, or to remove amorphous by oxygen plasma dry etching) Carbon, DLC material filling layer 3), or for the material of the filling layer 3, the etching solution of the layer 2A, the layer 2B is substantially or completely not corroded to wet the layer 3 (for example, the layer 3 for the amorphous silicon material, Use TMAH etching solution).
  • the vertical anisotropic etch process completely removes the fill layer 3, revealing a wider vertical first opening 2T.
  • the layer 2B is laterally etched away leaving a lateral recess 2R between the layers 2A.
  • the carbon-to-fluorine ratio is reduced to laterally etch the layer 2B of silicon nitride, or the layer 2B of silicon nitride is etched with hot phosphoric acid.
  • layer 2B may be etched using HF-based etching solution.
  • a common source region 1S is formed at the bottom of the first opening 2T, and a gate stack structure 5A/5B is formed in the recess 2R.
  • the source region 1S may be formed by ion implantation doping, and preferably further forming a metal silicide (not shown) on the surface.
  • a metal silicide such as NiSi 2-y , Ni 1-x Pt x Si 2-y , CoSi 2-y or Ni 1-x Co x Si 2-y , wherein x is greater than 0 and less than 1, and y is greater than or equal to 0. 1.
  • the gate stack structure 5 includes a gate insulating layer 5A and a gate conductive layer 5B.
  • layer 5A includes PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, and the like. Not shown in the figures, layer 5A preferably further comprises a plurality of sub-layers, such as a tunneling layer, a storage layer, a barrier layer.
  • a plurality of sub-layers such as a tunneling layer, a storage layer, a barrier layer.
  • the tunneling layer comprises SiO 2 or a high-k material, wherein the high-k material includes, but is not limited to, nitrides (eg, SiN, SiON, AlN, TiN), metal oxides (mainly sub-groups and lanthanide metal element oxides, eg MgO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZnO, ZrO 2 , HfO 2 , CeO 2 , Y 2 O 3 , La 2 O 3 ), nitrogen oxides (eg HfSiON), perovskite phase oxidation
  • the tunneling layer may be a single layer structure or a multilayer stack structure of the above materials (for example, PbZr x Ti 1-x O 3 (PZT), Ba x Sr 1-x TiO 3 (BST)) or the like.
  • the memory layer is a dielectric material having charge trapping ability, such as SiN, HfO, ZrO, etc., and combinations thereof, and may also be a single layer structure or a multilayer stack structure of the above materials.
  • the barrier layer may be a single layer structure or a multilayer stack structure of a dielectric material such as silicon oxide, aluminum oxide, or cerium oxide.
  • layer 5A is, for example, an ONO structure composed of silicon oxide, silicon nitride, or silicon oxide.
  • the gate conductive layer 5B may be polysilicon, polysilicon, or metal, wherein the metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir a metal element such as Eu, Nd, Er, or La, or an alloy of these metals and a nitride of these metals, and the gate conductive layer 5B may be doped with elements such as C, F, N, O, B, P, and As. To adjust the work function.
  • a barrier layer (not shown) of nitride is preferably formed between the gate insulating layer 5A and the gate conductive layer 5B by a conventional method such as PVD, CVD, ALD, etc., and the barrier layer is made of M x N y , M x Si y N z , M x Al y N z , M a Al x Si y N z , wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements.
  • layer 5B may be a single layer structure or a multilayer stack structure.
  • a thin insulating layer 6A is formed on the sidewall of the first opening 2T and a metal is formed in the insulating layer 6A to form the source contact 6B.
  • the insulating layer 6A may be formed by a process such as thermal oxidation, chemical oxidation, PECVD, HDPCVD, etc., and the material may be silicon oxide, silicon nitride or a high-k material.
  • the layer 6A preferably covers only the sidewalls of the first opening 2T, and the thinner portion of the bottom layer can be removed by a wet etching process or an isotropic dry etching process, similar to the sidewall technology.
  • a low resistance common source contact line 6B is formed by a process such as MOCVD, MBE, ALD, evaporation, sputtering, or the like.
  • the CMP or etch back method is used, or the deposition metal process parameters are adjusted to lower the height of layer 6B so that the top is lower than the bottom surface of the topmost gate stack structure 5A/5B (the metal gate structure at the top is used for
  • the top select transistor has a top select gate line USG) and then backfills the insulating layer 6A until it is flush with the topmost layer 2A.
  • the insulating layer 6A on the top of the CSL layer 6B is etched away to expose the underlying layer 6B.
  • the size of the third opening 6T formed by the etching is larger than the size of the first opening 2T (for example, the diameter of the circle or the maximum span of the polygon), and the gate stack structure of a part of the USG layer is removed. 5A/5B.
  • the common source contact line CSL pattern is connected to the plurality of third openings 6T, and may further extend out of the memory cell region to be connected to an external circuit to form an interconnection.
  • the same insulating layer 6A is filled in the third opening 6T to form an isolation insulating region of the top selection gate line.
  • an interlayer dielectric layer (ILD) 7 is formed over the entire device.
  • ILD is formed by spraying, spin coating, CVD deposition, etc.
  • low-k materials include, but are not limited to, organic low-k materials (eg, organic polymers containing aryl or polycyclic rings), inorganic low-k materials (eg, Amorphous carbon nitride film, polycrystalline boron nitride film, fluorosilicate glass, BSG, PSG, BPSG), porous low-k material (for example, disilane trioxane (SSQ)-based porous low-k material, porous silica, porous SiOCH , C-doped silica, F-doped amorphous carbon, porous diamond, porous organic polymer).
  • SSQ disilane trioxane
  • the ILD 7 is then etched until the CSL layer 6B is exposed, a fourth opening (not shown) is formed and a metallic material is deposited to form a contact
  • bit lines are connected.
  • a second ILD 9 is deposited over the first ILD 7 using a similar process and material and etched to form contact holes exposing the channel region 4D, and the deposited metal forms a bit line connection 10.
  • FIGS. 1 to 10 only show a process according to an embodiment of the present invention, and the present invention may also employ other processes to complete the manufacture of the three-dimensional memory device.
  • the first opening for the common source region and the second opening for the channel region shown in FIGS. 3B and 4B can be photolithographically/engraved.
  • the etch patterning implementation that is, the processes shown in FIGS. 3 and 4 can be combined as long as there are a plurality of second openings around each of the first openings.
  • the layout shown in FIGS. 7B, 7B and after is in accordance with the layout shown in FIGS.
  • Etching is performed to complete the gate electrode isolation of each layer (the pattern of the isolation layer 6B of the metal layer 6A is surrounded by the center) and form a common source wiring CSL pattern. Specifically, after the etch hole completes the gate stack deposition, then the dielectric fill planarizes the entire plane, and then physically etches according to the area marked by CSL shown in FIG. 10B, similar to the step of WL-Cut in the TCAT process, and the deposition is thin. The dielectric layer side wall is then deposited with a conductive layer such as metal to form a conductive surface of the common source region.
  • a conductive layer such as metal to form a conductive surface of the common source region.
  • the channel layer 4 is different.
  • a plurality of channel layers 4 may be provided between the first openings 2T in two columns (arranged in the up and down direction in FIG. 5B), thereby increasing the first opening 2T.
  • the self-alignment of the dummy gate layer 2B completes the automatic isolation of the control gate.
  • the side faces of the gate stack structures 5A/5B between the adjacent two columns of channel layers 4 are insulated and insulated by the remaining second material layer 2B, enhancing the insulating properties of the device.
  • the word line deep groove of the TCAT three-dimensional device is replaced by deep hole etching to perform the same function, the integration density is improved, the etching process of the stacked structure is simplified, and the metal gate control performance is retained.

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Abstract

一种三维存储器制造方法，包括步骤：在衬底（1）上形成第一材料层（2A）与第二材料层（2B）的堆叠结构（2）；刻蚀堆叠结构（2）露出衬底（1），形成垂直的多个第一开孔；在每个第一开孔中形成填充层（3）；在每个第一开孔周围，刻蚀堆叠结构（2）露出衬底（1），形成垂直的多个第二开孔；在每个第二开孔中形成垂直的沟道层（4）和漏极（4D）；选择性刻蚀去除填充层（3），重新露出第一开孔；侧向刻蚀部分或者完全去除第二材料层（2B），留下凹槽（2R）；在凹槽（2R）中形成栅极堆叠结构（5A/5B）；在每个第一开孔底部的衬底上和/或中形成共源极（1S）。该三维存储器制造方法将TCAT三维器件的字线深槽替换为深孔刻蚀来完成相同的功能，提高集成密度，简化堆叠结构的刻蚀工艺，保留了金属栅控制性能。

Description

三维存储器及其制造方法 技术领域
本发明涉及一种半导体器件及其制造方法，特别是涉及一种高密度三维存储器及其制造方法。
背景技术
为了改善存储器件的密度，业界已经广泛致力于研发减小二维布置的存储器单元的尺寸的方法。随着二维(2D)存储器件的存储器单元尺寸持续缩减，信号冲突和干扰会显著增大，以至于难以执行多电平单元(MLC)操作。为了克服2D存储器件的限制，业界已经研发了具有三维(3D)结构的存储器件，通过将存储器单元三维地布置在衬底之上来提高集成密度。
业界目前一种常用的3D存储器件结构是太比特单元阵列晶体管(TCAT)。具体地，可以首先在衬底上沉积多层叠层结构(例如氧化物和氮化物交替的多个ONO结构)；通过各向异性的刻蚀工艺对衬底上多层叠层结构刻蚀而形成沿着存储器单元字线(WL)延伸方向分布、垂直于衬底表面的多个沟道通孔(可直达衬底表面或者具有一定过刻蚀)；在沟道通孔中沉积多晶硅等材料形成柱状沟道；沿着WL方向刻蚀多层叠层结构形成直达衬底的沟槽，露出包围在柱状沟道周围的多层叠层；针对叠层中相邻层之间的刻蚀选择性，选择刻蚀选择比较高的腐蚀液湿法去除叠层中的第二类型材料，在柱状沟道周围留下横向分布的第一类型材料构成的突起结构；在沟槽中突起结构的侧壁沉积高k介质材料的栅极介质层以及金属材质的栅极导电层构成的栅极堆叠；刻蚀叠层结构形成源漏接触并完成后端制造工艺。此时，叠层结构在柱状沟道侧壁留下的一部分突起形成了栅电极之间的隔离层，而留下的栅极堆叠夹设在多个隔离层之间作为控制电极。当向栅极施加电压时，栅极的边缘电场会使得例如多晶硅材料的柱状沟道侧壁上感应形成源漏区，由此构成多个串并联的闪存单元构成的门阵列而记录所存储的逻辑状态。其中，为了将单元区多个串并联 MOSFET信号引出，在柱状沟道顶部沉积填充多晶硅材料形成漏区，并形成与漏区电连接的金属接触塞以进一步电连接至上方的位线(bit-line，BL)。此外，在多个垂直柱状沟道之间衬底中形成带有金属硅化物接触的共用源区。在单元导通状态下，电流从共用源区流向周围的垂直沟道区，并在控制栅极(与字线WL相连)施加的控制电压作用下向上穿过垂直沟道中感应生成的多个源漏区，通过沟道顶部的漏区而进一步流向上方的位线。
该TCAT器件结构具有体擦除(改变控制栅极可以引起感应源漏区以及浮栅极中电势变化，能整体擦除)、金属栅极(能较方便通过控制金属材料控制功函数从而调节晶体管阈值)等诸多优点。但是另一方面，由于除了顶部的选择晶体管(USG，位于存储晶体管单元串上方)之外，其余栅极与字线(WL)连接都是通过刻蚀孔进行共享链接，并且采用后栅工艺刻蚀去除伪栅极形成栅极开口并沉积金属栅极，这种极高深宽比(AR例如通常大于40:1乃至100:1)的深接触孔以及栅极开口将由于沉积多层薄膜而使得宽度增大，进而使得TCAT的存储单元密度无法有效进一步减小。同时，深槽的刻蚀和深孔沟道的刻蚀都是对多层堆栈的刻蚀，工艺复杂度很高，深孔和深槽的形状差异使得刻蚀的工艺也要有所变化。
与TCAT技术对应的，另一种常用的器件结构例如是采用位成本可缩减(BiCS)的NAND结构，通过将存储器单元三维地布置在衬底之上来提高集成密度、其中沟道层垂直竖立在衬底上，栅极分为下层的选择栅极、中层的控制栅极以及上层的选择栅极三部分，通过将栅极信号分布在三组栅电极中以减小信号之间的串扰。具体地，上层和下层的器件用作选择晶体管——栅极高度/厚度较大的垂直MOSFET，栅极介质层为常规的单层高k材料；中层的器件用作存储单元串，栅极高度/厚度较小，栅极介质层为隧穿层、存储层、阻挡层的堆叠结构。基于BiCS的NAND结构器件的具体制造工艺一般包括，在硅衬底上沉积下层选择栅电极层，刻蚀下层选择栅电极层形成直达衬底的孔槽以沉积沟道层的下部分以及下层栅电极的引出接触，在上方沉积控制栅极层，刻蚀控制栅极层形成作为存储器单元区域的中间沟道区以及中层控制栅电极的引出接触，刻蚀形成控制栅极，按照字线、位线划分需要将整个器件分割为多个区域，在之上沉积上层选择 栅极并刻蚀、沉积形成上部沟道以及上层引出接触，之后采用后续工艺完成器件的制造。在BiCS结构中，除了最上方的选择晶体管USG之外，下方的所有栅电极都可以是平板状，相对于TCAT而言可以避免深沟槽、深孔接触工艺，有利于提高存储器密度。在这种工艺过程中，最为关键的刻蚀步骤仅在于对于中间层存储器沟道区和引出接触的光刻，这直接决定了整个器件的集成度以及信号抗干扰能力。然而，BiCS结构虽然通过存储阵列与选择晶体管堆叠放置而分别利用控制栅极阈值，并且通过分层连接栅极避免了过大深宽比的接触孔或栅极开口的复杂工艺，但是只能通过多晶硅材质的栅极诱导漏极泄漏电流(GIDL)进行擦除，无法进行体擦除，读写效率较低。
发明内容
由上所述，本发明的目的在于克服上述技术困难，一种能以较低成本实现接触互连并且保持金属栅控制性能的新型三维存储器结构的制造方法。
为此，本发明一方面提供了一种三维存储器制造方法，包括步骤：在衬底上形成第一材料层与第二材料层的堆叠结构；刻蚀堆叠结构露出衬底，形成垂直的多个第一开孔；在每个第一开孔中形成填充层；在每个第一开孔周围，刻蚀堆叠结构露出衬底，形成垂直的多个第二开孔；在每个第二开孔中形成垂直的沟道层和漏极；选择性刻蚀去除填充层，重新露出第一开孔；侧向刻蚀部分或者完全去除第二材料层，留下凹槽；在凹槽中形成栅极堆叠结构；在每个第一开孔底部的衬底上和/或中形成共源极。
其中，第一材料层、第二材料层、填充层三者之间具有各自不同的刻蚀选择性。
其中，第一材料层、第二材料层、填充层材料选自氧化硅、氮化硅、氮氧化硅、非晶硅、非晶锗、DLC、非晶碳的任意一种及其组合。
其中，第一开孔的尺寸大于或等于第二开孔的尺寸。
其中，沟道层为中心包括绝缘体的中空结构。
其中，形成共源极之后进一步包括，在每个第一开孔侧壁形成绝缘层，在绝缘层侧壁以及每个第一开孔底部形成接触共源区的接触层。
其中，形成接触层之时或者之后进一步包括，控制沉积工艺参数或者回刻使得接触层的顶面低于栅极堆叠结构最顶层的底面，并且采用绝缘层回填。
其中，形成接触层之后进一步包括，刻蚀去除部分第一材料层、栅极堆叠结构形成第三开孔，在第三开孔中沉积绝缘材料形成与栅极堆叠结构最顶层之间的隔离绝缘区。
其中，形成隔离绝缘区之后进一步包括，在器件上形成层间介质层，刻蚀层间介质层形成第四开孔直至露出接触层，填充金属形成共源线引线。
其中，形成共源线接触塞之后进一步包括，在器件上形成第二层间介质层，刻蚀第二层间介质层形成第五开孔直至暴露沟道区，填充金属形成位线接触。
其中，刻蚀形成第一开孔之前进一步包括，在阵列区域周围的字线接触区域刻蚀堆叠结构形成台阶，依次暴露每个第一材料层和第二材料层的端部。
本发明另一方面提供了一种三维存储器制造方法，包括步骤：在衬底上形成第一材料层与第二材料层的堆叠结构；刻蚀堆叠结构露出衬底，同时形成垂直的多个第一开孔以及在每个第一开孔周围的多个第二开孔；在每个第一开孔中形成填充层；在每个第二开孔中形成垂直的沟道层和漏极；选择性刻蚀去除填充层，重新露出第一开孔；侧向刻蚀部分或者完全去除第二材料层，留下凹槽；在凹槽中形成栅极堆叠结构；在每个第一开孔底部的衬底上和/或中形成共源极。
本发明又一方面提供了一种三维存储器，包括：在衬底上垂直分布的多个共源极引线，与衬底中和/或上的共源极接触；在每个共源极引线周围垂直于衬底分布的多个沟道层，每个沟道层顶部具有漏极；在每个沟道层侧壁上的多个绝缘隔离层以及在每个绝缘隔离层之间的多个栅极堆叠结构。
依照本发明的三维存储器制造方法，将TCAT三维器件的字线深槽替换为深孔刻蚀来完成相同的功能，提高集成密度，简化堆叠结构的刻蚀工艺，保留了金属栅控制性能。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1至图10为依照本发明的三维半导体存储器件制造方法的各个步骤的剖视图和/或顶视图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了能以较低成本实现接触互连并且保持金属栅控制性能的新型三维存储器结构的制造方法。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
如图1所示，在衬底1上交替形成第一材料层2A与第二材料层2B的堆叠结构2。衬底1材质可以包括体硅(bulk Si)、体锗(bulk Ge)、绝缘体上硅(SOI)、绝缘体上锗(GeOI)或者是其他化合物半导体衬底，例如SiGe、SiC、GaN、GaAs、InP等等，以及这些物质的组合。为了与现有的IC制造工艺兼容，衬底1优选地为含硅材质的衬底，例如Si、SOI、SiGe、Si:C等。堆叠结构2的选自以下材料的组合并且至少包括一种绝缘介质：如氧化硅、氮化硅、非晶碳、类金刚石无定形碳(DLC)、氧化锗、氧化铝、等及其组合。第一材料层2A具有第一刻蚀选择性，第二材料层2B具有第二刻蚀选择性并且不同于第一刻蚀选择性(例如两种材料之间的刻蚀选择比大于5:1并优选大于10:1)。在本发明一个优选实施例中，叠层结构2A/2B均为非导电材料，层2A/层2B的组合例如氧化硅与氮化硅的组合、氧化硅与(未掺杂)多晶硅或非晶硅的组合、氧化硅或氮化硅与非晶碳的组合等等。在本发明另一优选实施例中，层2A与层2B在湿法腐蚀条件或者在氧等离子干法刻蚀条件下具有较大的刻蚀选择比(例如大于5:1)。层2A、层2B的沉积方法包括PECVD、LPCVD、HDPCVD、MOCVD、MBE、ALD、热氧化、蒸发、溅射等各种工艺。在本发明一个最优实施例中，层2A为二氧化硅，层2B为氮化硅。如图1所示，最低部的层2B将用于未来最底层选择栅电极形成，因此标注为LSG，最顶部的层2B将用于未来最顶层选择栅电极形成，因此标注为USG，中部具有从WL0～WLn的多个层2B以用于n+1条位线。图1中仅示出了n＝2的情形，但是实际上n可以依照需要 为大于等于1的任何正整数。
任选的，如图2所包括的剖视图2A和顶视图2B所示，刻蚀堆叠结构2A/2B，依次露出一部分层2A/2B的侧面端部以形成台阶状的字线焊垫区域(WL-Pad Region,WLPR)，中心区域为阵列区域(Array Region，AR)。其中，在WLPR区域，依次暴露了顶层USG上方的层2A:USG、用于WL2的层2B上方的层2A:WL2、用于WL1的层2B上方的层2A:WL1、用于WL0的层2B上方的层2A:WL0、用于LSG的层2B上方的层2A:LSG、以及保护衬底1的层2A。以下图3至图10的步骤将针对图2中的中心的阵列区域进行，换言之也即各个顶视图仅示出了区域2A:AR中的一部分。
在现有技术的TCAT结构制造方法中，一般是刻蚀深孔并沉积多晶硅等沟道材料形成沟道后，通过执行深槽刻蚀暴露出作为层2B的伪栅(SiN),之后移去层2B的伪栅并完成栅堆栈介质层和金属电极沉积等步骤完成存储单元的制备；随后通过侧墙、注入和硅化来完成共源区形成；接着通过深槽的氧化物填充、CMP，共源区CSL接触孔刻蚀和填充，金属线连线来完成CSL的连线。如背景技术部分所述，这种后形成的深槽往往难以兼顾深宽比以及金属填充率，容易导致器件失效。
与之对照的，本发明的一个实例不用深槽而用如图3所示的深孔刻蚀，这样工艺和沟道形成工艺相同，在完成存储单元的制备之后，直接通过侧墙、硅化和金属的深孔填充完成共源区的接触，然后引线完成CSL连线。相对而言，多层介质刻蚀工艺简单，存储阵列的密度提高，共源区的接触孔引出工艺更加简单，原有的二氧化硅填充深槽并平坦化、刻蚀接触孔、填充接触孔的方式直接被深孔的侧墙绝缘层和金属接触孔填充所替代
如包括剖视图3A、顶视图3B的图3所示，在阵列区域刻蚀堆叠结构2直至暴露衬底1(该区域将形成未来的共源区)，形成作为伪栅极开孔的第一开孔(未示出)并在伪栅极开孔中形成填充层3。在稍后图5所示的步骤中，第一开孔将作为形成共源区1S以及侧向刻蚀去除部分层2B所用的入口区域。优选地，采用RIE或等离子干法刻蚀各向异性刻蚀层2A/层2B的堆叠结构2，形成露出衬底1以及衬底1上交替堆叠的层2A/层2B的侧壁的第一开孔(未示出)。刻蚀气体例如针对二氧化硅和氮化硅等材质的碳氟基刻蚀气体，并且通过增加碳氟比而在侧壁形成由含C聚合物形成的临时保护侧壁，最终获得较好的垂直侧壁。在本发明一个优选实施例中刻蚀气体优选C3F6、 C4F8等含C量比较高的气体并进一步优选通过增加氧化性气体如O2、CO等控制侧壁形貌。平行于衬底1表面切得的孔槽的截面形状可以为矩形、方形、菱形、圆形、半圆形、椭圆形、三角形、五边形、五角形、六边形、八边形等等各种几何形状。填充层3沉积方法包括PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等，材质优选为与堆叠结构2的层2A、层2B均具有高选择性的材料，例如层3、层2A、层2B三者之间每两个之间的刻蚀选择比均大于等于5：1。在本发明一个优选实施例中，层2A为氧化硅，层2B为氮化硅，填充层为非晶硅、非晶锗、非晶碳、DLC等，反之亦然。
接着，如包括剖视图4A、顶视图4B的图4所示，在每个第一开孔周围刻蚀形成多个第二开孔并形成垂直的沟道区4。与刻蚀形成第一开孔的工艺类似，RIE或等离子干法刻蚀各向异性刻蚀层2A/层2B的堆叠结构2，在第一开孔的周围形成多个露出衬底1以及衬底1上交替堆叠的层2A/层2B的侧壁的第二开孔(未示出)。刻蚀气体例如针对二氧化硅和氮化硅等材质的碳氟基刻蚀气体，并且通过增加碳氟比而在侧壁形成由含C聚合物形成的临时保护侧壁，最终获得较好的垂直侧壁。在本发明一个优选实施例中刻蚀气体优选C3F6、C4F8等含C量比较高的气体并进一步优选通过增加氧化性气体如O2、CO等控制侧壁形貌。如图4A、4B所示，用于暴露共源区的第一开孔的尺寸(例如直径)要大于或等于用于形成沟道区的第二开孔尺寸，例如两者尺寸(直径或者多边形的最大跨距的比值)比大于1..5并优选大于等于2。在本发明一个实施例中，每一个第一开孔周围具有六个第二开孔，以便于提高稍后侧向刻蚀层2B的效率以及均匀性。在本发明其他实施例中，每一个第一开孔周围可以具有的第二开孔的数目为2、3、4、5、6、7、8、9乃至更多。
此后，在第二开孔中形成多个垂直的沟道层4。沟道层4的材质可以包括单晶硅、单晶锗、SiGe、Si:C、SiGe:C、SiGe:H等半导体材料，沉积工艺包括LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD等。在本发明一个实施例中，沟道层4的沉积方式为局部填充第二开孔的侧壁而形成为具有空气隙的中空柱形。在本发明其他实施例中，选择沟道层4的沉积方式以完全或者局部填充第二开孔，形成实心柱、空心环、或者空心环内填充绝缘层(未示出)的核心-外壳结构。沟道层4的水平截面的形状与第二开孔类似并且优选地共形，可以为实心的矩形、方形、菱形、圆形、半圆形、椭圆形、三角形、五边形、五角形、六边形、八边形等等各种几何形状，或者为上述几何形状演 化得到的空心的环状、桶状结构(并且其内部可以填充绝缘层)。优选地，对于空心的柱状沟道层4结构，可以进一步在沟道层4A内侧填充绝缘隔离层4B，例如通过LPCVD、PECVD、HDPCVD等工艺形成例如氧化硅材质的层4B，用于支撑、绝缘并隔离沟道层4A。此后，在沟道层4顶部沉积漏区接触4D。优选地，采用与沟道层4材质相同或者相近(例如与Si相近的材质SiGe、SiC等，以便微调晶格常数而提高载流子迁移率，从而控制单元器件的驱动性能)的材质沉积在第二开口的顶部而形成存储器件单元晶体管的漏区4D，并且可以进一步形成硅化物(未示出)以降低接触电阻。
如剖视图5A和顶视图5B所示，选择性刻蚀去除填充层3，重新露出第一开孔2T，利用第一开孔2T侧向刻蚀去除堆叠结构中的第二材料层(伪栅极层)2B。首先，采用垂直的各向异性刻蚀工艺，例如采用RIE或等离子干法刻蚀工艺(进一步提高碳氟比以刻蚀非晶硅、非晶锗，或者采用氧等离子干法刻蚀去除非晶碳、DLC材质的填充层3)，或者针对填充层3的材质而选用基本或者完全不腐蚀层2A、层2B的腐蚀液来湿法腐蚀去除层3(例如针对非晶硅材质的层3，采用TMAH腐蚀液)。垂直的各向异性刻蚀工艺完全去除了填充层3，重新露出了较宽的垂直的第一开孔2T。随后，采用各向同性干法刻蚀工艺，横向刻蚀去除层2B，在层2A之间留下了侧向凹槽2R。例如减小碳氟比以横向刻蚀氮化硅的层2B、或者采用热磷酸腐蚀氮化硅的层2B。备选地，当层2A为氮化硅、层2B为氧化硅时，可以采用HF基腐蚀液腐蚀层2B。
如包括剖视图6A、顶视图6B的附图6所示，在第一开孔2T底部形成共源区1S，在凹槽2R中形成栅极堆叠结构5A/5B。可以通过离子注入掺杂、以及优选地进一步在表面形成金属硅化物(未示出)而形成源区1S。金属硅化物例如NiSi2-y、Ni1-xPtxSi2-y、CoSi2-y或Ni1-xCoxSi2-y，其中x均大于0小于1，y均大于等于0小于1。栅极堆叠结构5包括栅极绝缘层5A和栅极导电层5B。层5A的沉积方法包括PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等。图中未示出的是，层5A优选地进一步包括多个子层，例如隧穿层、存储层、阻挡层。其中隧穿层包括SiO2或高k材料，其中高k材料包括但不限于氮化物(例如SiN、SiON、AlN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物，例如MgO、Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3)、氮氧化物(如HfSiON)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3 (BST))等，隧穿层可以是上述材料的单层结构或多层堆叠结构。存储层是具有电荷俘获能力的介质材料，例如SiN、HfO、ZrO等及其组合，同样可以是上述材料的单层结构或多层堆叠结构。阻挡层可以是氧化硅、氧化铝、氧化铪等介质材料的单层结构或多层堆叠结构。在本发明一个实施例中，层5A例如是氧化硅、氮化硅、氧化硅组成的ONO结构。
栅极导电层5B可以是多晶硅、多晶锗硅、或金属，其中金属可包括Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er、La等金属单质、或这些金属的合金以及这些金属的氮化物，栅极导电层5B中还可掺杂有C、F、N、O、B、P、As等元素以调节功函数。栅极绝缘层5A与栅极导电层5B之间还优选通过PVD、CVD、ALD等常规方法形成氮化物的阻挡层(未示出)，阻挡层材质为MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz，其中M为Ta、Ti、Hf、Zr、Mo、W或其它元素。同样地，层5B可以是单层结构也可以是多层堆叠结构。
进一步地，如图6所示，在第一开孔2T侧壁形成较薄的绝缘层6A并在绝缘层6A中填充金属形成源极接触6B。绝缘层6A可以采用热氧化、化学氧化、PECVD、HDPCVD等工艺形成，材质可以为氧化硅、氮化硅或高K材料。层6A优选仅覆盖第一开孔2T侧壁，底部堆积的较薄部分可以采用湿法腐蚀工艺或者各向同性干法刻蚀工艺去除，类似于侧墙技术。随后，采用MOCVD、MBE、ALD、蒸发、溅射等工艺形成低电阻的共源极接触线6B，也称作CSL。优选地，采用CMP或者回刻方法，或者调整沉积金属工艺参数，降低层6B的高度使其顶部低于最顶部的栅极堆叠结构5A/5B的底面(顶部的该金属栅极结构即用于顶部选择晶体管的顶部选择栅线USG)，接着再回填绝缘层6A直至与最顶层的层2A齐平。
此后，优选地，如图7A剖视图和图7B顶视图所示，刻蚀去除CSL层6B顶部的绝缘层6A，露出下方的层6B。在该刻蚀步骤中，刻蚀形成的第三开孔6T尺寸要大于第一开孔2T的尺寸(例如圆形的直径或多边形的最大跨距)，去除了一部分USG层级的栅极堆叠结构5A/5B。如图7B所示，共源极接触线CSL图形连接了多个第三开孔6T，并且可以进一步延伸出存储单元区而连接至外部电路形成互连线。
如图8所示，在第三开孔6T中填充同样的绝缘层6A，形成了顶层选择栅极线的隔离绝缘区。
如图9所示，在整个器件之上形成层间介质层(ILD)7。例如采用喷涂、旋涂、CVD沉积等工艺形成低k材料的ILD 7，低k材料包括但不限于有机低k材料(例如含芳基或者多元环的有机聚合物)、无机低k材料(例如无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃、BSG、PSG、BPSG)、多孔低k材料(例如二硅三氧烷(SSQ)基多孔低k材料、多孔二氧化硅、多孔SiOCH、掺C二氧化硅、掺F多孔无定形碳、多孔金刚石、多孔有机聚合物)。随后刻蚀ILD 7直至暴露CSL层6B，形成第四开孔(未示出)并沉积金属材料形成接触塞8，连接了阵列的共源区1S。
如图10A和图10B所示，完整位线连接。在第一ILD 7之上采用类似工艺和材质沉积第二ILD 9并刻蚀形成暴露沟道区4D的接触孔，沉积金属形成位线连接10。
值得注意的是，图1至图10仅示出了根据本发明一个实施例的工艺方法，本发明还可以采用其他工序完成三维存储器件的制造。例如，在本发明一个优选的备选实施例中，图3B和图4B所示的用于共源区的第一开孔与用于沟道区的第二开孔可以通过一次光刻/刻蚀构图实现，也即图3和图4所示工艺可以合并，只要在每个第一开孔周边存在多个第二开孔即可。在本发明另一备选实施例中，在执行完成图6所示的栅极堆叠结构填充之后，在图7A、图7B以及之后所示的连线阶段按照图7B、图10B所示的版图进行刻蚀，完成各层栅电极隔离(中心包围了金属层6A的隔离层6B图形)并形成共源极连线CSL图形。具体地，在刻蚀孔完成栅堆栈沉积以后，然后介质填充平坦化整个平面，然后按照图10B所示CSL标注的区域进行物理刻蚀，类似于TCAT工艺中WL-Cut的步骤，沉积薄的介质层侧墙，然后沉积金属等导电层形成一个共源区的导电面。好处在于，前一个实例中除了USG隔离其他的WL没有隔离，这个方法可以完全像TCAT一样完成各层WL的隔离。
在本发明另一备选实施例中，可以在图5移除作为伪栅极的层2B工序之中，与图5所示相邻两个第一开孔2T直线连线之间仅有一个沟道层4不同，如图10C所示，可以在两列(沿图5B中上下方向排列)第一开孔2T之间具有多个沟道层4，由此增大了第一开孔2T之间的距离，并且在刻蚀去除层2B时仅部分去除而在凹槽2R中保留部分伪栅极层2B，利用伪栅极层2B的自对准完成了控制栅的自动隔离。换言之，相邻的两列沟道层4之间的栅极堆叠结构5A/5B的侧面通过残留的第二材料层2B而绝缘隔离，增强了器件的绝缘性能。
依照本发明的三维存储器制造方法，将TCAT三维器件的字线深槽替换为深孔刻蚀来完成相同的功能，提高集成密度，简化堆叠结构的刻蚀工艺，保留了金属栅控制性能。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构或方法流程做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (13)

  1. 一种三维存储器制造方法，包括步骤：
    在衬底上形成第一材料层与第二材料层的堆叠结构；
    刻蚀堆叠结构露出衬底，形成垂直的多个第一开孔；
    在每个第一开孔中形成填充层；
    在每个第一开孔周围，刻蚀堆叠结构露出衬底，形成垂直的多个第二开孔；
    在每个第二开孔中形成垂直的沟道层和漏极；
    选择性刻蚀去除填充层，重新露出第一开孔；
    侧向刻蚀部分或者完全去除第二材料层，留下凹槽；
    在凹槽中形成栅极堆叠结构；
    在每个第一开孔底部的衬底上和/或中形成共源极。
  2. 如权利要求1所述的三维存储器制造方法，其中，第一材料层、第二材料层、填充层三者之间具有各自不同的刻蚀选择性。
  3. 如权利要求2所述的三维存储器制造方法，其中，第一材料层、第二材料层、填充层材料选自氧化硅、氮化硅、氮氧化硅、非晶硅、非晶锗、DLC、非晶碳的任意一种及其组合。
  4. 如权利要求1所述的三维存储器制造方法，其中，第一开孔的尺寸大于或等于第二开孔的尺寸。
  5. 如权利要求1所述的三维存储器制造方法，其中，沟道层为中心包括绝缘体的中空结构。
  6. 如权利要求1所述的三维存储器制造方法，其中，形成共源极之后进一步包括，在每个第一开孔侧壁形成绝缘层，在绝缘层侧壁以及每个第一开孔底部形成接触共源区的接触层。
  7. 如权利要求6所述的三维存储器制造方法，其中，形成接触层之时或者之后进一步包括，控制沉积工艺参数或者回刻使得接触层的顶面低于栅极堆叠结构最顶层的底面，并且采用绝缘层回填。
  8. 如权利要求6所述的三维存储器制造方法，其中，形成接触层之后进一步包括，刻蚀去除部分第一材料层、栅极堆叠结构形成第三开孔，在第三开孔中沉积绝缘材料形成与栅极堆叠结构最顶层之间的隔离绝缘区。
  9. 如权利要求8所述的三维存储器制造方法，其中，形成隔离绝缘 区之后进一步包括，在器件上形成层间介质层，刻蚀层间介质层形成第四开孔直至露出接触层，填充金属形成共源线引线。
  10. 如权利要求9所述的三维存储器制造方法，其中，形成共源线接触塞之后进一步包括，在器件上形成第二层间介质层，刻蚀第二层间介质层形成第五开孔直至暴露沟道区，填充金属形成位线接触。
  11. 如权利要求1所述的三维存储器制造方法，其中，刻蚀形成第一开孔之前进一步包括，在阵列区域周围的字线接触区域刻蚀堆叠结构形成台阶，依次暴露每个第一材料层和第二材料层的端部。
  12. 一种三维存储器制造方法，包括步骤：
    在衬底上形成第一材料层与第二材料层的堆叠结构；
    刻蚀堆叠结构露出衬底，同时形成垂直的多个第一开孔以及在每个第一开孔周围的多个第二开孔；
    在每个第一开孔中形成填充层；
    在每个第二开孔中形成垂直的沟道层和漏极；
    选择性刻蚀去除填充层，重新露出第一开孔；
    侧向刻蚀部分或者完全去除第二材料层，留下凹槽；
    在凹槽中形成栅极堆叠结构；
    在每个第一开孔底部的衬底上和/或中形成共源极。
  13. 一种三维存储器，包括：
    在衬底上垂直分布的多个共源极引线，与衬底中和/或上的共源极接触；
    在每个共源极引线周围垂直于衬底分布的多个沟道层，每个沟道层顶部具有漏极；
    在每个沟道层侧壁上的多个绝缘隔离层以及在每个绝缘隔离层之间的多个栅极堆叠结构。
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